Index: uspace/drv/bus/pci/pciintel/pci.c
===================================================================
--- uspace/drv/bus/pci/pciintel/pci.c	(revision eeb5cc2d5850c270487563d1838d9f371d7f8e73)
+++ uspace/drv/bus/pci/pciintel/pci.c	(revision 46eb2c4eee45c63d2a2d1ef420c1917ec6c890fa)
@@ -256,5 +256,5 @@
 	fibril_mutex_lock(&bus->conf_mutex);
 
-	pio_write_32(bus->conf_addr_port, host2uint32_t_le(conf_addr));
+	pio_write_32(bus->conf_addr_reg, host2uint32_t_le(conf_addr));
 
 	/*
@@ -263,5 +263,5 @@
 	 * support shorter PIO reads offset from this register.
  	 */
-	val = uint32_t_le2host(pio_read_32(bus->conf_data_port));
+	val = uint32_t_le2host(pio_read_32(bus->conf_data_reg));
 
 	switch (len) {
@@ -299,6 +299,6 @@
  		 * missing bits first.
  		 */
-		pio_write_32(bus->conf_addr_port, host2uint32_t_le(conf_addr));
-		val = uint32_t_le2host(pio_read_32(bus->conf_data_port));
+		pio_write_32(bus->conf_addr_reg, host2uint32_t_le(conf_addr));
+		val = uint32_t_le2host(pio_read_32(bus->conf_data_reg));
 	}
 	
@@ -317,6 +317,6 @@
 	}
 
-	pio_write_32(bus->conf_addr_port, host2uint32_t_le(conf_addr));
-	pio_write_32(bus->conf_data_port, host2uint32_t_le(val));
+	pio_write_32(bus->conf_addr_reg, host2uint32_t_le(conf_addr));
+	pio_write_32(bus->conf_data_reg, host2uint32_t_le(val));
 	
 	fibril_mutex_unlock(&bus->conf_mutex);
@@ -724,17 +724,12 @@
 	    hw_resources.resources[1].res.io_range.address);
 	
-	bus->conf_io_addr =
-	    (uint32_t) hw_resources.resources[0].res.io_range.address;
-	bus->conf_io_data =
-	    (uint32_t) hw_resources.resources[1].res.io_range.address;
-	
-	if (pio_enable((void *)(uintptr_t)bus->conf_io_addr, 4,
-	    &bus->conf_addr_port)) {
+	if (pio_enable_resource(&bus->pio_win, &hw_resources.resources[0],
+	    (void **) &bus->conf_addr_reg)) {
 		ddf_msg(LVL_ERROR, "Failed to enable configuration ports.");
 		rc = EADDRNOTAVAIL;
 		goto fail;
 	}
-	if (pio_enable((void *)(uintptr_t)bus->conf_io_data, 4,
-	    &bus->conf_data_port)) {
+	if (pio_enable_resource(&bus->pio_win, &hw_resources.resources[1],
+	    (void **) &bus->conf_data_reg)) {
 		ddf_msg(LVL_ERROR, "Failed to enable configuration ports.");
 		rc = EADDRNOTAVAIL;
Index: uspace/drv/bus/pci/pciintel/pci.h
===================================================================
--- uspace/drv/bus/pci/pciintel/pci.h	(revision eeb5cc2d5850c270487563d1838d9f371d7f8e73)
+++ uspace/drv/bus/pci/pciintel/pci.h	(revision 46eb2c4eee45c63d2a2d1ef420c1917ec6c890fa)
@@ -45,8 +45,6 @@
 	/** DDF device node */
 	ddf_dev_t *dnode;
-	uint32_t conf_io_addr;
-	uint32_t conf_io_data;
-	void *conf_data_port;
-	void *conf_addr_port;
+	ioport32_t *conf_addr_reg;
+	ioport32_t *conf_data_reg;
 	pio_window_t pio_win;
 	fibril_mutex_t conf_mutex;