Changeset 46eb2c4 in mainline
- Timestamp:
- 2013-09-12T12:25:43Z (11 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- 8049b79
- Parents:
- eeb5cc2
- Location:
- uspace/drv/bus/pci/pciintel
- Files:
-
- 2 edited
Legend:
- Unmodified
- Added
- Removed
-
uspace/drv/bus/pci/pciintel/pci.c
reeb5cc2 r46eb2c4 256 256 fibril_mutex_lock(&bus->conf_mutex); 257 257 258 pio_write_32(bus->conf_addr_ port, host2uint32_t_le(conf_addr));258 pio_write_32(bus->conf_addr_reg, host2uint32_t_le(conf_addr)); 259 259 260 260 /* … … 263 263 * support shorter PIO reads offset from this register. 264 264 */ 265 val = uint32_t_le2host(pio_read_32(bus->conf_data_ port));265 val = uint32_t_le2host(pio_read_32(bus->conf_data_reg)); 266 266 267 267 switch (len) { … … 299 299 * missing bits first. 300 300 */ 301 pio_write_32(bus->conf_addr_ port, host2uint32_t_le(conf_addr));302 val = uint32_t_le2host(pio_read_32(bus->conf_data_ port));301 pio_write_32(bus->conf_addr_reg, host2uint32_t_le(conf_addr)); 302 val = uint32_t_le2host(pio_read_32(bus->conf_data_reg)); 303 303 } 304 304 … … 317 317 } 318 318 319 pio_write_32(bus->conf_addr_ port, host2uint32_t_le(conf_addr));320 pio_write_32(bus->conf_data_ port, host2uint32_t_le(val));319 pio_write_32(bus->conf_addr_reg, host2uint32_t_le(conf_addr)); 320 pio_write_32(bus->conf_data_reg, host2uint32_t_le(val)); 321 321 322 322 fibril_mutex_unlock(&bus->conf_mutex); … … 724 724 hw_resources.resources[1].res.io_range.address); 725 725 726 bus->conf_io_addr = 727 (uint32_t) hw_resources.resources[0].res.io_range.address; 728 bus->conf_io_data = 729 (uint32_t) hw_resources.resources[1].res.io_range.address; 730 731 if (pio_enable((void *)(uintptr_t)bus->conf_io_addr, 4, 732 &bus->conf_addr_port)) { 726 if (pio_enable_resource(&bus->pio_win, &hw_resources.resources[0], 727 (void **) &bus->conf_addr_reg)) { 733 728 ddf_msg(LVL_ERROR, "Failed to enable configuration ports."); 734 729 rc = EADDRNOTAVAIL; 735 730 goto fail; 736 731 } 737 if (pio_enable ((void *)(uintptr_t)bus->conf_io_data, 4,738 &bus->conf_data_port)) {732 if (pio_enable_resource(&bus->pio_win, &hw_resources.resources[1], 733 (void **) &bus->conf_data_reg)) { 739 734 ddf_msg(LVL_ERROR, "Failed to enable configuration ports."); 740 735 rc = EADDRNOTAVAIL; -
uspace/drv/bus/pci/pciintel/pci.h
reeb5cc2 r46eb2c4 45 45 /** DDF device node */ 46 46 ddf_dev_t *dnode; 47 uint32_t conf_io_addr; 48 uint32_t conf_io_data; 49 void *conf_data_port; 50 void *conf_addr_port; 47 ioport32_t *conf_addr_reg; 48 ioport32_t *conf_data_reg; 51 49 pio_window_t pio_win; 52 50 fibril_mutex_t conf_mutex;
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