Changeset 46c20c8 in mainline for kernel/arch/arm32/src


Ignore:
Timestamp:
2010-11-26T20:08:10Z (15 years ago)
Author:
Jiri Svoboda <jiri@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/fix-logger-deadlock, topic/msim-upgrade, topic/simplify-dev-export
Children:
45df59a
Parents:
fb150d78 (diff), ffdd2b9 (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the (diff) links above to see all the changes relative to each parent.
Message:

Merge mainline changes.

Location:
kernel/arch/arm32/src
Files:
1 added
18 edited

Legend:

Unmodified
Added
Removed

  • kernel/arch/arm32/src/arm32.c

    rfb150d78 r46c20c8  
    4545#include <interrupt.h>
    4646#include <arch/regutils.h>
     47#include <arch/machine_func.h>
    4748#include <userspace.h>
    4849#include <macros.h>
    49 #include <string.h>
     50#include <str.h>
    5051#include <arch/ras.h>
    51 
    52 #ifdef MACHINE_testarm
    53         #include <arch/mach/testarm/testarm.h>
    54 #endif
    55 
    56 #ifdef MACHINE_integratorcp
    57         #include <arch/mach/integratorcp/integratorcp.h>
    58 #endif
    59 
    6052
    6153/** Performs arm32-specific initialization before main_bsp() is called. */
    6254void arch_pre_main(void *entry __attribute__((unused)), bootinfo_t *bootinfo)
    6355{
    64         unsigned int i;
     56        init.cnt = min3(bootinfo->cnt, TASKMAP_MAX_RECORDS, CONFIG_INIT_TASKS);
    6557       
    66         init.cnt = bootinfo->cnt;
    67        
    68         for (i = 0; i < min3(bootinfo->cnt, TASKMAP_MAX_RECORDS, CONFIG_INIT_TASKS); ++i) {
    69                 init.tasks[i].addr = bootinfo->tasks[i].addr;
     58        size_t i;
     59        for (i = 0; i < init.cnt; i++) {
     60                init.tasks[i].addr = (uintptr_t) bootinfo->tasks[i].addr;
    7061                init.tasks[i].size = bootinfo->tasks[i].size;
    7162                str_cpy(init.tasks[i].name, CONFIG_TASK_NAME_BUFLEN,
    7263                    bootinfo->tasks[i].name);
    7364        }
     65
     66        /* Initialize machine_ops pointer. */
     67        machine_ops_init();
    7468}
    7569

  • kernel/arch/arm32/src/asm.S

    rfb150d78 r46c20c8  
    1 #
    2 # Copyright (c) 2007 Michal Kebrt
    3 # All rights reserved.
    4 #
    5 # Redistribution and use in source and binary forms, with or without
    6 # modification, are permitted provided that the following conditions
    7 # are met:
    8 #
    9 # - Redistributions of source code must retain the above copyright
    10 #   notice, this list of conditions and the following disclaimer.
    11 # - Redistributions in binary form must reproduce the above copyright
    12 #   notice, this list of conditions and the following disclaimer in the
    13 #   documentation and/or other materials provided with the distribution.
    14 # - The name of the author may not be used to endorse or promote products
    15 #   derived from this software without specific prior written permission.
    16 #
    17 # THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
    18 # IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
    19 # OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
    20 # IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
    21 # INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
    22 # NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
    23 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
    24 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
    25 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
    26 # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
    27 #
     1/*
     2 * Copyright (c) 2007 Michal Kebrt
     3 * All rights reserved.
     4 *
     5 * Redistribution and use in source and binary forms, with or without
     6 * modification, are permitted provided that the following conditions
     7 * are met:
     8 *
     9 * - Redistributions of source code must retain the above copyright
     10 *   notice, this list of conditions and the following disclaimer.
     11 * - Redistributions in binary form must reproduce the above copyright
     12 *   notice, this list of conditions and the following disclaimer in the
     13 *   documentation and/or other materials provided with the distribution.
     14 * - The name of the author may not be used to endorse or promote products
     15 *   derived from this software without specific prior written permission.
     16 *
     17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
     22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
     23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
     24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
     25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
     26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     27 */
    2828
    29        
    3029.text
    3130
    … …  
    3736.global memcpy_from_uspace_failover_address
    3837.global memcpy_to_uspace_failover_address
     38.global early_putchar
    3939
    4040memsetb:
    … …  
    4747memcpy_from_uspace:
    4848memcpy_to_uspace:
    49         add     r3, r1, #3
    50         bic     r3, r3, #3
    51         cmp     r1, r3
    52         stmdb   sp!, {r4, r5, lr}
    53         mov     r5, r0                  /* save dst */
    54         beq     4f
    55 1:
    56         cmp     r2, #0
    57         movne   ip, #0
    58         beq     3f
    59 2:
    60         ldrb    r3, [ip, r1]
    61         strb    r3, [ip, r0]
    62         add     ip, ip, #1
    63         cmp     ip, r2
    64         bne     2b
    65 3:
    66         mov     r0, r5
    67         ldmia   sp!, {r4, r5, pc}
    68 4:
    69         add     r3, r0, #3
    70         bic     r3, r3, #3
    71         cmp     r0, r3
    72         bne     1b
    73         movs    r4, r2, lsr #2
    74         moveq   lr, r4
    75         beq     6f
    76         mov     lr, #0
    77         mov     ip, lr
    78 5:
    79         ldr     r3, [ip, r1]
    80         add     lr, lr, #1
    81         cmp     lr, r4
    82         str     r3, [ip, r0]
    83         add     ip, ip, #4
    84         bne     5b
    85 6:
    86         ands    r4, r2, #3
    87         beq     3b
    88         mov     r3, lr, lsl #2
    89         add     r0, r3, r0
    90         add     ip, r3, r1
    91         mov     r2, #0
    92 7:
    93         ldrb    r3, [r2, ip]
    94         strb    r3, [r2, r0]
    95         add     r2, r2, #1
    96         cmp     r2, r4
    97         bne     7b
    98         b       3b
     49        add r3, r1, #3
     50        bic r3, r3, #3
     51        cmp r1, r3
     52        stmdb sp!, {r4, r5, lr}
     53        mov r5, r0 /* save dst */
     54        beq 4f
     55       
     56        1:
     57                cmp r2, #0
     58                movne ip, #0
     59                beq 3f
     60       
     61        2:
     62                ldrb r3, [ip, r1]
     63                strb r3, [ip, r0]
     64                add ip, ip, #1
     65                cmp ip, r2
     66                bne 2b
     67       
     68        3:
     69                mov r0, r5
     70                ldmia sp!, {r4, r5, pc}
     71       
     72        4:
     73                add r3, r0, #3
     74                bic r3, r3, #3
     75                cmp r0, r3
     76                bne 1b
     77                movs r4, r2, lsr #2
     78                moveq lr, r4
     79                beq 6f
     80                mov lr, #0
     81                mov ip, lr
     82       
     83        5:
     84                ldr r3, [ip, r1]
     85                add lr, lr, #1
     86                cmp lr, r4
     87                str r3, [ip, r0]
     88                add ip, ip, #4
     89                bne 5b
     90       
     91        6:
     92                ands r4, r2, #3
     93                beq 3b
     94                mov r3, lr, lsl #2
     95                add r0, r3, r0
     96                add ip, r3, r1
     97                mov r2, #0
     98       
     99        7:
     100                ldrb r3, [r2, ip]
     101                strb r3, [r2, r0]
     102                add r2, r2, #1
     103                cmp r2, r4
     104                bne 7b
     105                b 3b
    99106
    100107memcpy_from_uspace_failover_address:
    101108memcpy_to_uspace_failover_address:
    102         mov     r0, #0
    103         ldmia   sp!, {r4, r5, pc}
     109        mov r0, #0
     110        ldmia sp!, {r4, r5, pc}
     111
     112early_putchar:
     113        mov pc, lr

  • kernel/arch/arm32/src/cpu/cpu.c

    rfb150d78 r46c20c8  
    4343
    4444/** Implementators (vendor) names */
    45 static char *imp_data[] = {
     45static const char *imp_data[] = {
    4646        "?",                                    /* IMP_DATA_START_OFFSET */
    4747        "ARM Ltd",                              /* 0x41 */
    … …  
    6060
    6161/** Architecture names */
    62 static char *arch_data[] = {
     62static const char *arch_data[] = {
    6363        "?",       /* 0x0 */
    6464        "4",       /* 0x1 */
    … …  
    108108void cpu_print_report(cpu_t *m)
    109109{
    110         char * vendor = imp_data[0];
    111         char * architecture = arch_data[0];
     110        const char *vendor = imp_data[0];
     111        const char *architecture = arch_data[0];
    112112        cpu_arch_t * cpu_arch = &m->arch;
    113113

  • kernel/arch/arm32/src/ddi/ddi.c

    rfb150d78 r46c20c8  
    3636#include <ddi/ddi.h>
    3737#include <proc/task.h>
    38 #include <arch/types.h>
     38#include <typedefs.h>
    3939
    4040/** Enable I/O space range for task.

  • kernel/arch/arm32/src/debug/stacktrace.c

    rfb150d78 r46c20c8  
    3535#include <stacktrace.h>
    3636#include <syscall/copy.h>
    37 #include <arch/types.h>
    3837#include <typedefs.h>
    3938
    … …  
    4140#define FRAME_OFFSET_RA         -1
    4241
    43 bool kernel_frame_pointer_validate(uintptr_t fp)
     42bool kernel_stack_trace_context_validate(stack_trace_context_t *ctx)
    4443{
    45         return fp != 0;
     44        return ctx->fp != 0;
    4645}
    4746
    48 bool kernel_frame_pointer_prev(uintptr_t fp, uintptr_t *prev)
     47bool kernel_frame_pointer_prev(stack_trace_context_t *ctx, uintptr_t *prev)
    4948{
    50         uint32_t *stack = (void *) fp;
     49        uint32_t *stack = (void *) ctx->fp;
    5150
    5251        *prev = stack[FRAME_OFFSET_FP_PREV];
    … …  
    5453}
    5554
    56 bool kernel_return_address_get(uintptr_t fp, uintptr_t *ra)
     55bool kernel_return_address_get(stack_trace_context_t *ctx, uintptr_t *ra)
    5756{
    58         uint32_t *stack = (void *) fp;
     57        uint32_t *stack = (void *) ctx->fp;
    5958
    6059        *ra = stack[FRAME_OFFSET_RA];
    … …  
    6261}
    6362
    64 bool uspace_frame_pointer_validate(uintptr_t fp)
     63bool uspace_stack_trace_context_validate(stack_trace_context_t *ctx)
    6564{
    66         return fp != 0;
     65        return ctx->fp != 0;
    6766}
    6867
    69 bool uspace_frame_pointer_prev(uintptr_t fp, uintptr_t *prev)
     68bool uspace_frame_pointer_prev(stack_trace_context_t *ctx, uintptr_t *prev)
    7069{
    7170        return !copy_from_uspace((void *) prev,
    72             (uint32_t *) fp + FRAME_OFFSET_FP_PREV, sizeof(*prev));
     71            (uint32_t *) ctx->fp + FRAME_OFFSET_FP_PREV, sizeof(*prev));
    7372}
    7473
    75 bool uspace_return_address_get(uintptr_t fp, uintptr_t *ra)
     74bool uspace_return_address_get(stack_trace_context_t *ctx, uintptr_t *ra)
    7675{
    77         return !copy_from_uspace((void *) ra, (uint32_t *) fp + FRAME_OFFSET_RA,
    78             sizeof(*ra));
     76        return !copy_from_uspace((void *) ra,
     77            (uint32_t *) ctx->fp + FRAME_OFFSET_RA, sizeof(*ra));
    7978}
    8079

  • kernel/arch/arm32/src/dummy.S

    rfb150d78 r46c20c8  
    11#
    2 # Copyright (c) 2007 Michal Kebry, Pavel Jancik, Petr Stepan
     2# Copyright (c) 2007 Michal Kebrt, Pavel Jancik, Petr Stepan
    33# All rights reserved.
    44#

  • kernel/arch/arm32/src/exc_handler.S

    rfb150d78 r46c20c8  
    9696        ldmfd r3!, {r4-r7}
    9797        stmfd r13!, {r4-r7}
    98         stmfd r13!, {r13, lr}^
     98        mov r4, r13
     99        stmfd r4, {r13, lr}^
     100        nop                     /* Cannot access r13 immediately after stm(2) */
     101        sub r13, r13, #8
    99102        stmfd r13!, {r2}
     103
     104        # Stop stack traces here
     105        mov fp, #0
     106       
    100107        b 2f
    101108
    … …  
    123130        stmfd r13!, {r2}
    1241312:
    125         # Stop stack traces here
    126         mov fp, #0
    127132.endm
    128133
    … …  
    135140
    136141        # return to user mode
    137         ldmfd r13!, {r13, lr}^
     142        mov r0, r13
     143        ldmfd r0, {r13, lr}^
     144        nop                     /* Cannot access r13 immediately after ldm(2) */
     145        add r13, r13, #8
    138146        b 2f
    139147
    … …  
    150158        mov r0, #0
    151159        mov r1, r13
    152         bl ras_check 
     160        bl ras_check
    153161        LOAD_REGS_FROM_STACK
    154162
    … …  
    158166        mov r0, #5
    159167        mov r1, r13
    160         bl ras_check 
     168        bl ras_check
    161169        LOAD_REGS_FROM_STACK
    162170
    … …  
    166174        mov r0, #6
    167175        mov r1, r13
    168         bl ras_check 
     176        bl ras_check
    169177        LOAD_REGS_FROM_STACK
    170178
    … …  
    173181        mov r0, #1
    174182        mov r1, r13
    175         bl ras_check 
     183        bl ras_check
    176184        LOAD_REGS_FROM_STACK
    177185
    … …  
    181189        mov r0, #3
    182190        mov r1, r13
    183         bl ras_check 
     191        bl ras_check
    184192        LOAD_REGS_FROM_STACK
    185193
    … …  
    189197        mov r0, #4
    190198        mov r1, r13
    191         bl ras_check 
     199        bl ras_check
    192200        LOAD_REGS_FROM_STACK
    193201

  • kernel/arch/arm32/src/exception.c

    rfb150d78 r46c20c8  
    3737#include <arch/memstr.h>
    3838#include <arch/regutils.h>
     39#include <arch/machine_func.h>
    3940#include <interrupt.h>
    4041#include <arch/mm/page_fault.h>
    … …  
    4344#include <syscall/syscall.h>
    4445#include <stacktrace.h>
    45 
    46 #ifdef MACHINE_testarm
    47         #include <arch/mach/testarm/testarm.h>
    48 #endif
    49 
    50 #ifdef MACHINE_integratorcp
    51         #include <arch/mach/integratorcp/integratorcp.h>
    52 #endif
    5346
    5447/** Offset used in calculation of exception handler's relative address.
    … …  
    9184 *
    9285 * Dispatches the syscall.
     86 *
    9387 */
    94 static void swi_exception(int exc_no, istate_t *istate)
     88static void swi_exception(unsigned int exc_no, istate_t *istate)
    9589{
    9690        istate->r0 = syscall_handler(istate->r0, istate->r1, istate->r2,
    … …  
    148142 * Determines the sources of interrupt and calls their handlers.
    149143 */
    150 static void irq_exception(int exc_no, istate_t *istate)
     144static void irq_exception(unsigned int exc_no, istate_t *istate)
    151145{
    152146        machine_irq_exception(exc_no, istate);
    … …  
    165159        install_exception_handlers();
    166160       
    167         exc_register(EXC_IRQ, "interrupt", (iroutine) irq_exception);
    168         exc_register(EXC_PREFETCH_ABORT, "prefetch abort",
    169             (iroutine) prefetch_abort);
    170         exc_register(EXC_DATA_ABORT, "data abort", (iroutine) data_abort);
    171         exc_register(EXC_SWI, "software interrupt", (iroutine) swi_exception);
     161        exc_register(EXC_IRQ, "interrupt", true,
     162            (iroutine_t) irq_exception);
     163        exc_register(EXC_PREFETCH_ABORT, "prefetch abort", true,
     164            (iroutine_t) prefetch_abort);
     165        exc_register(EXC_DATA_ABORT, "data abort", true,
     166            (iroutine_t) data_abort);
     167        exc_register(EXC_SWI, "software interrupt", true,
     168            (iroutine_t) swi_exception);
    172169}
    173170
    … …  
    176173 * @param istate Structure to be printed.
    177174 */
    178 void print_istate(istate_t *istate)
     175void istate_decode(istate_t *istate)
    179176{
    180         printf("istate dump:\n");
    181        
    182         printf(" r0: %x    r1: %x    r2: %x    r3: %x\n",
     177        printf("r0 =%#0" PRIx32 "\tr1 =%#0" PRIx32 "\t"
     178            "r2 =%#0" PRIx32 "\tr3 =%#0" PRIx32 "\n",
    183179            istate->r0, istate->r1, istate->r2, istate->r3);
    184         printf(" r4: %x    r5: %x    r6: %x    r7: %x\n",
     180        printf("r4 =%#" PRIx32 "\tr5 =%#0" PRIx32 "\t"
     181            "r6 =%#0" PRIx32 "\tr7 =%#0" PRIx32 "\n",
    185182            istate->r4, istate->r5, istate->r6, istate->r7);
    186         printf(" r8: %x    r8: %x   r10: %x    fp: %x\n",
    187             istate->r8, istate->r9, istate->r10, istate->fp);
    188         printf(" r12: %x    sp: %x    lr: %x  spsr: %x\n",
    189             istate->r12, istate->sp, istate->lr, istate->spsr);
    190        
    191         printf(" pc: %x\n", istate->pc);
    192 
    193         stack_trace_istate(istate);
     183        printf("r8 =%#0" PRIx32 "\tr9 =%#0" PRIx32 "\t"
     184            "r10=%#0" PRIx32 "\tfp =%p\n",
     185            istate->r8, istate->r9, istate->r10,
     186            (void *) istate->fp);
     187        printf("r12=%#0" PRIx32 "\tsp =%p\tlr =%p\tspsr=%p\n",
     188            istate->r12, (void *) istate->sp,
     189            (void *) istate->lr, (void *) istate->spsr);
    194190}
    195191

  • kernel/arch/arm32/src/interrupt.c

    rfb150d78 r46c20c8  
    3636#include <arch/asm.h>
    3737#include <arch/regutils.h>
     38#include <arch/machine_func.h>
    3839#include <ddi/irq.h>
    3940#include <ddi/device.h>
    4041#include <interrupt.h>
    41 
    42 #ifdef MACHINE_testarm
    43         #include <arch/mach/testarm/testarm.h>
    44 #endif
    45 
    46 #ifdef MACHINE_integratorcp
    47         #include <arch/mach/integratorcp/integratorcp.h>
    48 #endif
    49 
    50 /** Initial size of a table holding interrupt handlers. */
    51 #define IRQ_COUNT 8
    5242
    5343/** Disable interrupts.
    … …  
    9787}
    9888
     89/** Check interrupts state.
     90 *
     91 * @return True if interrupts are disabled.
     92 *
     93 */
     94bool interrupts_disabled(void)
     95{
     96        return current_status_reg_read() & STATUS_REG_IRQ_DISABLED_BIT;
     97}
     98
    9999/** Initialize basic tables for exception dispatching
    100100 * and starts the timer.
    … …  
    102102void interrupt_init(void)
    103103{
    104         irq_init(IRQ_COUNT, IRQ_COUNT);
     104        size_t irq_count;
     105
     106        irq_count = machine_get_irq_count();
     107        irq_init(irq_count, irq_count);
     108
    105109        machine_timer_irq_start();
    106110}

  • kernel/arch/arm32/src/mach/integratorcp/integratorcp.c

    rfb150d78 r46c20c8  
    5656static icp_hw_map_t icp_hw_map;
    5757static irq_t icp_timer_irq;
    58 struct arm_machine_ops machine_ops = {
     58struct arm_machine_ops icp_machine_ops = {
    5959        icp_init,
    6060        icp_timer_irq_start,
    6161        icp_cpu_halt,
    62         icp_get_memory_size,
     62        icp_get_memory_extents,
    6363        icp_irq_exception,
    6464        icp_frame_init,
    6565        icp_output_init,
    66         icp_input_init
     66        icp_input_init,
     67        icp_get_irq_count
    6768};
    6869
    … …  
    214215}
    215216
    216 /** Returns the size of emulated memory.
    217  *
    218  * @return Size in bytes.
    219  */
    220 size_t icp_get_memory_size(void)
    221 {
     217/** Get extents of available memory.
     218 *
     219 * @param start         Place to store memory start address.
     220 * @param size          Place to store memory size.
     221 */
     222void icp_get_memory_extents(uintptr_t *start, uintptr_t *size)
     223{
     224        *start = 0;
     225
    222226        if (hw_map_init_called) {
    223                 return (sdram[((*(uint32_t *)icp_hw_map.sdramcr & ICP_SDRAM_MASK) >> 2)]);
     227                *size = (sdram[((*(uint32_t *)icp_hw_map.sdramcr &
     228                    ICP_SDRAM_MASK) >> 2)]);
    224229        } else {
    225                 return SDRAM_SIZE;
    226         }
    227        
     230                *size = SDRAM_SIZE;
     231        }
    228232}
    229233
    … …  
    242246 * @param istate Saved processor state.
    243247 */
    244 void icp_irq_exception(int exc_no, istate_t *istate)
     248void icp_irq_exception(unsigned int exc_no, istate_t *istate)
    245249{
    246250        uint32_t sources = icp_irqc_get_sources();
    247         int i;
     251        unsigned int i;
    248252       
    249253        for (i = 0; i < ICP_IRQC_MAX_IRQ; i++) {
    … …  
    333337}
    334338
     339size_t icp_get_irq_count(void)
     340{
     341        return ICP_IRQ_COUNT;
     342}
    335343
    336344/** @}

  • kernel/arch/arm32/src/mach/testarm/testarm.c

    rfb150d78 r46c20c8  
    5656static irq_t gxemul_timer_irq;
    5757
    58 struct arm_machine_ops machine_ops = {
     58struct arm_machine_ops gxemul_machine_ops = {
    5959        gxemul_init,
    6060        gxemul_timer_irq_start,
    6161        gxemul_cpu_halt,
    62         gxemul_get_memory_size,
     62        gxemul_get_memory_extents,
    6363        gxemul_irq_exception,
    6464        gxemul_frame_init,
    6565        gxemul_output_init,
    66         gxemul_input_init
     66        gxemul_input_init,
     67        gxemul_get_irq_count
    6768};
    6869
    … …  
    126127}
    127128
     129size_t gxemul_get_irq_count(void)
     130{
     131        return GXEMUL_IRQ_COUNT;
     132}
     133
    128134/** Starts gxemul Real Time Clock device, which asserts regular interrupts.
    129135 *
    … …  
    185191}
    186192
    187 /** Returns the size of emulated memory.
    188  *
    189  * @return Size in bytes.
    190  */
    191 uintptr_t gxemul_get_memory_size(void)
    192 {
    193         return  *((uintptr_t *) (GXEMUL_MP_ADDRESS + GXEMUL_MP_MEMSIZE_OFFSET));
    194 }
    195 
     193/** Get extents of available memory.
     194 *
     195 * @param start         Place to store memory start address.
     196 * @param size          Place to store memory size.
     197 */
     198void gxemul_get_memory_extents(uintptr_t *start, uintptr_t *size)
     199{
     200        *start = 0;
     201        *size = *((uintptr_t *) (GXEMUL_MP_ADDRESS + GXEMUL_MP_MEMSIZE_OFFSET));
     202}
    196203
    197204/** Returns the mask of active interrupts. */
    … …  
    205212 * Determines the sources of interrupt and calls their handlers.
    206213 */
    207 void gxemul_irq_exception(int exc_no, istate_t *istate)
     214void gxemul_irq_exception(unsigned int exc_no, istate_t *istate)
    208215{
    209216        uint32_t sources = gxemul_irqc_get_sources();
    210217        unsigned int i;
    211218
    212         for (i = 0; i < GXEMUL_IRQC_MAX_IRQ; i++) {
     219        for (i = 0; i < GXEMUL_IRQ_COUNT; i++) {
    213220                if (sources & (1 << i)) {
    214221                        irq_t *irq = irq_dispatch_and_lock(i);

  • kernel/arch/arm32/src/machine_func.c

    rfb150d78 r46c20c8  
    3939
    4040#include <arch/machine_func.h>
     41#include <arch/mach/gta02/gta02.h>
     42#include <arch/mach/integratorcp/integratorcp.h>
     43#include <arch/mach/testarm/testarm.h>
    4144
     45/** Pointer to machine_ops structure being used. */
     46struct arm_machine_ops *machine_ops;
     47
     48/** Initialize machine_ops pointer. */
     49void machine_ops_init(void)
     50{
     51#if defined(MACHINE_gta02)
     52        machine_ops = &gta02_machine_ops;
     53#elif defined(MACHINE_testarm)
     54        machine_ops = &gxemul_machine_ops;
     55#elif defined(MACHINE_integratorcp)
     56        machine_ops = &icp_machine_ops;
     57#else
     58#error Machine type not defined.
     59#endif
     60}
    4261
    4362/** Maps HW devices to the kernel address space using #hw_map. */
    4463void machine_init(void)
    4564{
    46         (machine_ops.machine_init)();
     65        (machine_ops->machine_init)();
    4766}
    4867
    … …  
    5170void machine_timer_irq_start(void)
    5271{
    53         (machine_ops.machine_timer_irq_start)();
     72        (machine_ops->machine_timer_irq_start)();
    5473}
    5574
    … …  
    5877void machine_cpu_halt(void)
    5978{
    60         (machine_ops.machine_cpu_halt)();
     79        (machine_ops->machine_cpu_halt)();
    6180}
    6281
    63 
    64 /** Returns size of available memory.
     82/** Get extents of available memory.
    6583 *
    66  *  @return Size of available memory.
     84 * @param start         Place to store memory start address.
     85 * @param size          Place to store memory size.
    6786 */
    68 uintptr_t machine_get_memory_size(void)
     87void machine_get_memory_extents(uintptr_t *start, uintptr_t *size)
    6988{
    70         return (machine_ops.machine_get_memory_size)();
     89        (machine_ops->machine_get_memory_extents)(start, size);
    7190}
    7291
    … …  
    7695 * @param istate Saved processor state.
    7796 */
    78 void machine_irq_exception(int exc_no, istate_t *istate)
     97void machine_irq_exception(unsigned int exc_no, istate_t *istate)
    7998{
    80         (machine_ops.machine_irq_exception)(exc_no, istate);
     99        (machine_ops->machine_irq_exception)(exc_no, istate);
    81100}
    82101
    … …  
    87106void machine_frame_init(void)
    88107{
    89         (machine_ops.machine_frame_init)();
     108        (machine_ops->machine_frame_init)();
    90109}
    91110
    … …  
    95114void machine_output_init(void)
    96115{
    97         (machine_ops.machine_output_init)();
     116        (machine_ops->machine_output_init)();
    98117}
    99118
    … …  
    103122void machine_input_init(void)
    104123{
    105         (machine_ops.machine_input_init)();
     124        (machine_ops->machine_input_init)();
    106125}
    107126
    108 /*
    109  * Generic function to use, if sepcific function doesn't define any of the above functions.
    110  */
    111 void machine_genfunc()
     127/** Get IRQ number range used by machine. */
     128size_t machine_get_irq_count(void)
    112129{
     130        return (machine_ops->machine_get_irq_count)();
    113131}
    114132

  • kernel/arch/arm32/src/mm/frame.c

    rfb150d78 r46c20c8  
    3636#include <mm/frame.h>
    3737#include <arch/mm/frame.h>
     38#include <arch/machine_func.h>
    3839#include <config.h>
    39 
    40 #ifdef MACHINE_testarm
    41         #include <arch/mach/testarm/testarm.h>
    42 #endif
    43 
    44 #ifdef MACHINE_integratorcp
    45         #include <arch/mach/integratorcp/integratorcp.h>
    46 #endif
     40#include <align.h>
    4741
    4842/** Address of the last frame in the memory. */
    … …  
    5246void frame_arch_init(void)
    5347{
    54         last_frame = machine_get_memory_size();
     48        uintptr_t mem_start, mem_size;
     49        uintptr_t first_frame;
     50        uintptr_t num_frames;
     51
     52        machine_get_memory_extents(&mem_start, &mem_size);
     53        first_frame = ALIGN_UP(mem_start, FRAME_SIZE);
     54        last_frame = ALIGN_DOWN(mem_start + mem_size, FRAME_SIZE);
     55        num_frames = (last_frame - first_frame) >> FRAME_WIDTH;
    5556       
    5657        /* All memory as one zone */
    57         zone_create(0, ADDR2PFN(last_frame),
     58        zone_create(first_frame >> FRAME_WIDTH, num_frames,
    5859            BOOT_PAGE_TABLE_START_FRAME + BOOT_PAGE_TABLE_SIZE_IN_FRAMES, 0);
    5960       

  • kernel/arch/arm32/src/mm/page.c

    rfb150d78 r46c20c8  
    2727 */
    2828
    29 /** @addtogroup arm32mm 
     29/** @addtogroup arm32mm
    3030 * @{
    3131 */
    … …  
    4141#include <arch/exception.h>
    4242#include <typedefs.h>
    43 #include <arch/types.h>
    4443#include <interrupt.h>
    4544#include <arch/mm/frame.h>
    … …  
    5453        int flags = PAGE_CACHEABLE;
    5554        page_mapping_operations = &pt_mapping_operations;
     55
     56        page_table_lock(AS_KERNEL, true);
    5657       
    5758        uintptr_t cur;
    5859        /* Kernel identity mapping */
    59         for (cur = 0; cur < last_frame; cur += FRAME_SIZE)
     60        for (cur = PHYSMEM_START_ADDR; cur < last_frame; cur += FRAME_SIZE)
    6061                page_mapping_insert(AS_KERNEL, PA2KA(cur), cur, flags);
    6162       
    … …  
    6768#error "Only high exception vector supported now"
    6869#endif
     70        cur = ALIGN_DOWN(0x50008010, FRAME_SIZE);
     71        page_mapping_insert(AS_KERNEL, PA2KA(cur), cur, flags);
     72
     73        page_table_unlock(AS_KERNEL, true);
    6974       
    7075        as_switch(NULL, AS_KERNEL);
    … …  
    8893            KA2PA(KERNEL_ADDRESS_SPACE_END_ARCH)) {
    8994                panic("Unable to map physical memory %p (%d bytes).",
    90                     physaddr, size);
     95                    (void *) physaddr, size);
    9196        }
    9297       
    9398        uintptr_t virtaddr = PA2KA(last_frame);
    9499        pfn_t i;
     100
     101        page_table_lock(AS_KERNEL, true);
    95102        for (i = 0; i < ADDR2PFN(ALIGN_UP(size, PAGE_SIZE)); i++) {
    96103                page_mapping_insert(AS_KERNEL, virtaddr + PFN2ADDR(i),
    … …  
    98105                    PAGE_NOT_CACHEABLE | PAGE_READ | PAGE_WRITE | PAGE_KERNEL);
    99106        }
     107        page_table_unlock(AS_KERNEL, true);
    100108       
    101109        last_frame = ALIGN_UP(last_frame + size, FRAME_SIZE);

  • kernel/arch/arm32/src/mm/page_fault.c

    rfb150d78 r46c20c8  
    141141        if (instr.condition == 0xf) {
    142142                panic("page_fault - instruction does not access memory "
    143                     "(instr_code: %x, badvaddr:%x).", instr, badvaddr);
     143                    "(instr_code: %#0" PRIx32 ", badvaddr:%p).",
     144                    instr_union.pc, (void *) badvaddr);
    144145                return PF_ACCESS_EXEC;
    145146        }
    … …  
    160161
    161162        panic("page_fault - instruction doesn't access memory "
    162             "(instr_code: %x, badvaddr:%x).", instr, badvaddr);
     163            "(instr_code: %#0" PRIx32 ", badvaddr:%p).",
     164            instr_union.pc, (void *) badvaddr);
    163165
    164166        return PF_ACCESS_EXEC;
    … …  
    167169/** Handles "data abort" exception (load or store at invalid address).
    168170 *
    169  * @param exc_no        Exception number.
    170  * @param istate        CPU state when exception occured.
    171  */
    172 void data_abort(int exc_no, istate_t *istate)
     171 * @param exc_no Exception number.
     172 * @param istate CPU state when exception occured.
     173 *
     174 */
     175void data_abort(unsigned int exc_no, istate_t *istate)
    173176{
    174177        fault_status_t fsr __attribute__ ((unused)) =
    … …  
    182185        if (ret == AS_PF_FAULT) {
    183186                fault_if_from_uspace(istate, "Page fault: %#x.", badvaddr);
    184                 print_istate(istate);
    185                 printf("page fault - pc: %x, va: %x, status: %x(%x), "
    186                     "access:%d\n", istate->pc, badvaddr, fsr.status, fsr,
    187                     access);
    188                
    189                 panic("Page fault.");
     187                panic_memtrap(istate, access, badvaddr, NULL);
    190188        }
    191189}
    … …  
    193191/** Handles "prefetch abort" exception (instruction couldn't be executed).
    194192 *
    195  * @param exc_no        Exception number.
    196  * @param istate        CPU state when exception occured.
    197  */
    198 void prefetch_abort(int exc_no, istate_t *istate)
     193 * @param exc_no Exception number.
     194 * @param istate CPU state when exception occured.
     195 *
     196 */
     197void prefetch_abort(unsigned int exc_no, istate_t *istate)
    199198{
    200199        int ret = as_page_fault(istate->pc, PF_ACCESS_EXEC, istate);
    201200
    202201        if (ret == AS_PF_FAULT) {
    203                 printf("prefetch_abort\n");
    204                 print_istate(istate);
    205                 panic("page fault - prefetch_abort at address: %x.",
    206                     istate->pc);
     202                fault_if_from_uspace(istate,
     203                    "Page fault - prefetch_abort: %#x.", istate->pc);
     204                panic_memtrap(istate, PF_ACCESS_EXEC, istate->pc, NULL);
    207205        }
    208206}

  • kernel/arch/arm32/src/mm/tlb.c

    rfb150d78 r46c20c8  
    3737#include <arch/mm/asid.h>
    3838#include <arch/asm.h>
    39 #include <arch/types.h>
     39#include <typedefs.h>
    4040#include <arch/mm/page.h>
    4141

  • kernel/arch/arm32/src/ras.c

    rfb150d78 r46c20c8  
    11/*
    2  * Copyright (c) 2009 Jakub Jermar 
     2 * Copyright (c) 2009 Jakub Jermar
    33 * All rights reserved.
    44 *
    … …  
    4444#include <arch.h>
    4545#include <memstr.h>
    46 #include <arch/types.h>
     46#include <typedefs.h>
    4747
    4848uintptr_t *ras_page = NULL;
    … …  
    6666}
    6767
    68 void ras_check(int n, istate_t *istate)
     68void ras_check(unsigned int n, istate_t *istate)
    6969{
    7070        uintptr_t rewrite_pc = istate->pc;

  • kernel/arch/arm32/src/userspace.c

    rfb150d78 r46c20c8  
    9797                "mov sp, %[ustate]\n"
    9898                "msr spsr_c, %[user_mode]\n"
    99                 "ldmfd sp!, {r0-r12, sp, lr}^\n"
     99                "ldmfd sp, {r0-r12, sp, lr}^\n"
     100                "nop\n"         /* Cannot access sp immediately after ldm(2) */
     101                "add sp, sp, #(15*4)\n"
    100102                "ldmfd sp!, {pc}^\n"
    101103                :: [ustate] "r" (&ustate), [user_mode] "r" (user_mode)
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