Changeset 46c20c8 in mainline for kernel/arch/amd64/include


Ignore:
Timestamp:
2010-11-26T20:08:10Z (15 years ago)
Author:
Jiri Svoboda <jiri@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
45df59a
Parents:
fb150d78 (diff), ffdd2b9 (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the (diff) links above to see all the changes relative to each parent.
Message:

Merge mainline changes.

Location:
kernel/arch/amd64/include
Files:
1 added
1 deleted
24 edited

Legend:

Unmodified
Added
Removed

  • kernel/arch/amd64/include/arch.h

    rfb150d78 r46c20c8  
    2727 */
    2828
    29 /** @addtogroup amd64   
     29/** @addtogroup amd64
    3030 * @{
    3131 */

  • kernel/arch/amd64/include/asm.h

    rfb150d78 r46c20c8  
    3737
    3838#include <config.h>
    39 #include <arch/types.h>
    4039#include <typedefs.h>
    41 
    42 extern void asm_delay_loop(uint32_t t);
    43 extern void asm_fake_loop(uint32_t t);
     40#include <arch/cpu.h>
     41#include <trace.h>
    4442
    4543/** Return base address of current stack.
    … …  
    5048 *
    5149 */
    52 static inline uintptr_t get_stack_base(void)
     50NO_TRACE static inline uintptr_t get_stack_base(void)
    5351{
    5452        uintptr_t v;
    … …  
    5755                "andq %%rsp, %[v]\n"
    5856                : [v] "=r" (v)
    59                 : "0" (~((uint64_t) STACK_SIZE-1))
     57                : "0" (~((uint64_t) STACK_SIZE - 1))
    6058        );
    6159       
    … …  
    6361}
    6462
    65 static inline void cpu_sleep(void)
    66 {
    67         asm volatile ("hlt\n");
    68 }
    69 
    70 static inline void __attribute__((noreturn)) cpu_halt(void)
     63NO_TRACE static inline void cpu_sleep(void)
     64{
     65        asm volatile (
     66                "hlt\n"
     67        );
     68}
     69
     70NO_TRACE static inline void __attribute__((noreturn)) cpu_halt(void)
    7171{
    7272        while (true) {
    … …  
    7777}
    7878
    79 
    8079/** Byte from port
    8180 *
    … …  
    8685 *
    8786 */
    88 static inline uint8_t pio_read_8(ioport8_t *port)
     87NO_TRACE static inline uint8_t pio_read_8(ioport8_t *port)
    8988{
    9089        uint8_t val;
    … …  
    107106 *
    108107 */
    109 static inline uint16_t pio_read_16(ioport16_t *port)
     108NO_TRACE static inline uint16_t pio_read_16(ioport16_t *port)
    110109{
    111110        uint16_t val;
    … …  
    128127 *
    129128 */
    130 static inline uint32_t pio_read_32(ioport32_t *port)
     129NO_TRACE static inline uint32_t pio_read_32(ioport32_t *port)
    131130{
    132131        uint32_t val;
    … …  
    149148 *
    150149 */
    151 static inline void pio_write_8(ioport8_t *port, uint8_t val)
     150NO_TRACE static inline void pio_write_8(ioport8_t *port, uint8_t val)
    152151{
    153152        asm volatile (
    154153                "outb %b[val], %w[port]\n"
    155                 :: [val] "a" (val), [port] "d" (port)
     154                :: [val] "a" (val),
     155                   [port] "d" (port)
    156156        );
    157157}
    … …  
    165165 *
    166166 */
    167 static inline void pio_write_16(ioport16_t *port, uint16_t val)
     167NO_TRACE static inline void pio_write_16(ioport16_t *port, uint16_t val)
    168168{
    169169        asm volatile (
    170170                "outw %w[val], %w[port]\n"
    171                 :: [val] "a" (val), [port] "d" (port)
     171                :: [val] "a" (val),
     172                   [port] "d" (port)
    172173        );
    173174}
    … …  
    181182 *
    182183 */
    183 static inline void pio_write_32(ioport32_t *port, uint32_t val)
     184NO_TRACE static inline void pio_write_32(ioport32_t *port, uint32_t val)
    184185{
    185186        asm volatile (
    186187                "outl %[val], %w[port]\n"
    187                 :: [val] "a" (val), [port] "d" (port)
     188                :: [val] "a" (val),
     189                   [port] "d" (port)
    188190        );
    189191}
    190192
    191193/** Swap Hidden part of GS register with visible one */
    192 static inline void swapgs(void)
    193 {
    194         asm volatile("swapgs");
     194NO_TRACE static inline void swapgs(void)
     195{
     196        asm volatile (
     197                "swapgs"
     198        );
    195199}
    196200
    … …  
    203207 *
    204208 */
    205 static inline ipl_t interrupts_enable(void) {
     209NO_TRACE static inline ipl_t interrupts_enable(void) {
    206210        ipl_t v;
    207211       
    … …  
    224228 *
    225229 */
    226 static inline ipl_t interrupts_disable(void) {
     230NO_TRACE static inline ipl_t interrupts_disable(void) {
    227231        ipl_t v;
    228232       
    … …  
    244248 *
    245249 */
    246 static inline void interrupts_restore(ipl_t ipl) {
     250NO_TRACE static inline void interrupts_restore(ipl_t ipl) {
    247251        asm volatile (
    248252                "pushq %[ipl]\n"
    … …  
    259263 *
    260264 */
    261 static inline ipl_t interrupts_read(void) {
     265NO_TRACE static inline ipl_t interrupts_read(void) {
    262266        ipl_t v;
    263267       
    … …  
    271275}
    272276
     277/** Check interrupts state.
     278 *
     279 * @return True if interrupts are disabled.
     280 *
     281 */
     282NO_TRACE static inline bool interrupts_disabled(void)
     283{
     284        ipl_t v;
     285       
     286        asm volatile (
     287                "pushfq\n"
     288                "popq %[v]\n"
     289                : [v] "=r" (v)
     290        );
     291       
     292        return ((v & RFLAGS_IF) == 0);
     293}
     294
    273295/** Write to MSR */
    274 static inline void write_msr(uint32_t msr, uint64_t value)
     296NO_TRACE static inline void write_msr(uint32_t msr, uint64_t value)
    275297{
    276298        asm volatile (
    … …  
    282304}
    283305
    284 static inline unative_t read_msr(uint32_t msr)
     306NO_TRACE static inline unative_t read_msr(uint32_t msr)
    285307{
    286308        uint32_t ax, dx;
    … …  
    295317}
    296318
    297 
    298319/** Enable local APIC
    299320 *
    … …  
    301322 *
    302323 */
    303 static inline void enable_l_apic_in_msr()
     324NO_TRACE static inline void enable_l_apic_in_msr()
    304325{
    305326        asm volatile (
    … …  
    309330                "orl $(0xfee00000),%%eax\n"
    310331                "wrmsr\n"
    311                 ::: "%eax","%ecx","%edx"
    312         );
    313 }
    314 
    315 static inline uintptr_t * get_ip()
    316 {
    317         uintptr_t *ip;
    318        
    319         asm volatile (
    320                 "mov %%rip, %[ip]"
    321                 : [ip] "=r" (ip)
    322         );
    323        
    324         return ip;
     332                ::: "%eax", "%ecx", "%edx"
     333        );
    325334}
    326335
    … …  
    330339 *
    331340 */
    332 static inline void invlpg(uintptr_t addr)
     341NO_TRACE static inline void invlpg(uintptr_t addr)
    333342{
    334343        asm volatile (
    … …  
    343352 *
    344353 */
    345 static inline void gdtr_load(ptr_16_64_t *gdtr_reg)
     354NO_TRACE static inline void gdtr_load(ptr_16_64_t *gdtr_reg)
    346355{
    347356        asm volatile (
    … …  
    356365 *
    357366 */
    358 static inline void gdtr_store(ptr_16_64_t *gdtr_reg)
     367NO_TRACE static inline void gdtr_store(ptr_16_64_t *gdtr_reg)
    359368{
    360369        asm volatile (
    … …  
    369378 *
    370379 */
    371 static inline void idtr_load(ptr_16_64_t *idtr_reg)
     380NO_TRACE static inline void idtr_load(ptr_16_64_t *idtr_reg)
    372381{
    373382        asm volatile (
    … …  
    381390 *
    382391 */
    383 static inline void tr_load(uint16_t sel)
     392NO_TRACE static inline void tr_load(uint16_t sel)
    384393{
    385394        asm volatile (
    … …  
    389398}
    390399
    391 #define GEN_READ_REG(reg) static inline unative_t read_ ##reg (void) \
     400#define GEN_READ_REG(reg) NO_TRACE static inline unative_t read_ ##reg (void) \
    392401        { \
    393402                unative_t res; \
    … …  
    399408        }
    400409
    401 #define GEN_WRITE_REG(reg) static inline void write_ ##reg (unative_t regn) \
     410#define GEN_WRITE_REG(reg) NO_TRACE static inline void write_ ##reg (unative_t regn) \
    402411        { \
    403412                asm volatile ( \
    … …  
    426435GEN_WRITE_REG(dr7)
    427436
    428 extern size_t interrupt_handler_size;
    429 extern void interrupt_handlers(void);
     437extern void asm_delay_loop(uint32_t);
     438extern void asm_fake_loop(uint32_t);
     439
     440extern uintptr_t int_0;
     441extern uintptr_t int_1;
     442extern uintptr_t int_2;
     443extern uintptr_t int_3;
     444extern uintptr_t int_4;
     445extern uintptr_t int_5;
     446extern uintptr_t int_6;
     447extern uintptr_t int_7;
     448extern uintptr_t int_8;
     449extern uintptr_t int_9;
     450extern uintptr_t int_10;
     451extern uintptr_t int_11;
     452extern uintptr_t int_12;
     453extern uintptr_t int_13;
     454extern uintptr_t int_14;
     455extern uintptr_t int_15;
     456extern uintptr_t int_16;
     457extern uintptr_t int_17;
     458extern uintptr_t int_18;
     459extern uintptr_t int_19;
     460extern uintptr_t int_20;
     461extern uintptr_t int_21;
     462extern uintptr_t int_22;
     463extern uintptr_t int_23;
     464extern uintptr_t int_24;
     465extern uintptr_t int_25;
     466extern uintptr_t int_26;
     467extern uintptr_t int_27;
     468extern uintptr_t int_28;
     469extern uintptr_t int_29;
     470extern uintptr_t int_30;
     471extern uintptr_t int_31;
     472extern uintptr_t int_32;
     473extern uintptr_t int_33;
     474extern uintptr_t int_34;
     475extern uintptr_t int_35;
     476extern uintptr_t int_36;
     477extern uintptr_t int_37;
     478extern uintptr_t int_38;
     479extern uintptr_t int_39;
     480extern uintptr_t int_40;
     481extern uintptr_t int_41;
     482extern uintptr_t int_42;
     483extern uintptr_t int_43;
     484extern uintptr_t int_44;
     485extern uintptr_t int_45;
     486extern uintptr_t int_46;
     487extern uintptr_t int_47;
     488extern uintptr_t int_48;
     489extern uintptr_t int_49;
     490extern uintptr_t int_50;
     491extern uintptr_t int_51;
     492extern uintptr_t int_52;
     493extern uintptr_t int_53;
     494extern uintptr_t int_54;
     495extern uintptr_t int_55;
     496extern uintptr_t int_56;
     497extern uintptr_t int_57;
     498extern uintptr_t int_58;
     499extern uintptr_t int_59;
     500extern uintptr_t int_60;
     501extern uintptr_t int_61;
     502extern uintptr_t int_62;
     503extern uintptr_t int_63;
    430504
    431505#endif

  • kernel/arch/amd64/include/atomic.h

    rfb150d78 r46c20c8  
    3636#define KERN_amd64_ATOMIC_H_
    3737
    38 #include <arch/types.h>
     38#include <typedefs.h>
    3939#include <arch/barrier.h>
    4040#include <preemption.h>
     41#include <trace.h>
    4142
    42 static inline void atomic_inc(atomic_t *val) {
     43NO_TRACE static inline void atomic_inc(atomic_t *val)
     44{
    4345#ifdef CONFIG_SMP
    4446        asm volatile (
    … …  
    5456}
    5557
    56 static inline void atomic_dec(atomic_t *val) {
     58NO_TRACE static inline void atomic_dec(atomic_t *val)
     59{
    5760#ifdef CONFIG_SMP
    5861        asm volatile (
    … …  
    6871}
    6972
    70 static inline long atomic_postinc(atomic_t *val)
     73NO_TRACE static inline atomic_count_t atomic_postinc(atomic_t *val)
    7174{
    72         long r = 1;
     75        atomic_count_t r = 1;
    7376       
    7477        asm volatile (
    7578                "lock xaddq %[r], %[count]\n"
    76                 : [count] "+m" (val->count), [r] "+r" (r)
     79                : [count] "+m" (val->count),
     80                  [r] "+r" (r)
    7781        );
    7882       
    … …  
    8084}
    8185
    82 static inline long atomic_postdec(atomic_t *val)
     86NO_TRACE static inline atomic_count_t atomic_postdec(atomic_t *val)
    8387{
    84         long r = -1;
     88        atomic_count_t r = -1;
    8589       
    8690        asm volatile (
    8791                "lock xaddq %[r], %[count]\n"
    88                 : [count] "+m" (val->count), [r] "+r" (r)
     92                : [count] "+m" (val->count),
     93                  [r] "+r" (r)
    8994        );
    9095       
    … …  
    95100#define atomic_predec(val)  (atomic_postdec(val) - 1)
    96101
    97 static inline uint64_t test_and_set(atomic_t *val) {
    98         uint64_t v;
     102NO_TRACE static inline atomic_count_t test_and_set(atomic_t *val)
     103{
     104        atomic_count_t v = 1;
    99105       
    100106        asm volatile (
    101                 "movq $1, %[v]\n"
    102107                "xchgq %[v], %[count]\n"
    103                 : [v] "=r" (v), [count] "+m" (val->count)
     108                : [v] "+r" (v),
     109                  [count] "+m" (val->count)
    104110        );
    105111       
    … …  
    107113}
    108114
    109 
    110115/** amd64 specific fast spinlock */
    111 static inline void atomic_lock_arch(atomic_t *val)
     116NO_TRACE static inline void atomic_lock_arch(atomic_t *val)
    112117{
    113         uint64_t tmp;
     118        atomic_count_t tmp;
    114119       
    115120        preemption_disable();
    116121        asm volatile (
    117122                "0:\n"
    118                 "pause\n"
    119                 "mov %[count], %[tmp]\n"
    120                 "testq %[tmp], %[tmp]\n"
    121                 "jnz 0b\n"       /* lightweight looping on locked spinlock */
     123                "       pause\n"
     124                "       mov %[count], %[tmp]\n"
     125                "       testq %[tmp], %[tmp]\n"
     126                "       jnz 0b\n"       /* lightweight looping on locked spinlock */
    122127               
    123                 "incq %[tmp]\n"  /* now use the atomic operation */
    124                 "xchgq %[count], %[tmp]\n"
    125                 "testq %[tmp], %[tmp]\n"
    126                 "jnz 0b\n"
    127                 : [count] "+m" (val->count), [tmp] "=&r" (tmp)
     128                "       incq %[tmp]\n"  /* now use the atomic operation */
     129                "       xchgq %[count], %[tmp]\n"
     130                "       testq %[tmp], %[tmp]\n"
     131                "       jnz 0b\n"
     132                : [count] "+m" (val->count),
     133                  [tmp] "=&r" (tmp)
    128134        );
     135       
    129136        /*
    130137         * Prevent critical section code from bleeding out this way up.

  • kernel/arch/amd64/include/boot/boot.h

    rfb150d78 r46c20c8  
    2727 */
    2828
    29 /** @addtogroup amd64   
     29/** @addtogroup amd64
    3030 * @{
    3131 */
    … …  
    3636#define KERN_amd64_BOOT_H_
    3737
    38 #define BOOT_OFFSET             0x108000
    39 #define AP_BOOT_OFFSET          0x8000
    40 #define BOOT_STACK_SIZE         0x400
     38#define BOOT_OFFSET      0x108000
     39#define AP_BOOT_OFFSET   0x008000
     40#define BOOT_STACK_SIZE  0x000400
    4141
    42 #define MULTIBOOT_HEADER_MAGIC  0x1BADB002
    43 #define MULTIBOOT_HEADER_FLAGS  0x00010003
     42#define MULTIBOOT_HEADER_MAGIC  0x1BADB002
     43#define MULTIBOOT_HEADER_FLAGS  0x00010003
    4444
    4545#ifndef __ASM__

  • kernel/arch/amd64/include/context.h

    rfb150d78 r46c20c8  
    2727 */
    2828
    29 /** @addtogroup amd64   
     29/** @addtogroup amd64
    3030 * @{
    3131 */
    … …  
    3838#ifdef KERNEL
    3939
    40 #include <arch/types.h>
     40#include <typedefs.h>
    4141
    4242/* According to ABI the stack MUST be aligned on
    … …  
    4444 * panic sooner or later
    4545 */
    46 #define SP_DELTA     16
     46#define SP_DELTA  16
    4747
    4848#define context_set(c, _pc, stack, size) \
    … …  
    5959 */
    6060typedef struct {
    61     uintptr_t sp;
    62     uintptr_t pc;
    63    
    64     uint64_t rbx;
    65     uint64_t rbp;
    66 
    67     uint64_t r12;
    68     uint64_t r13;
    69     uint64_t r14;
    70     uint64_t r15;
    71 
    72     ipl_t ipl;
     61        uintptr_t sp;
     62        uintptr_t pc;
     63       
     64        uint64_t rbx;
     65        uint64_t rbp;
     66       
     67        uint64_t r12;
     68        uint64_t r13;
     69        uint64_t r14;
     70        uint64_t r15;
     71       
     72        ipl_t ipl;
    7373} __attribute__ ((packed)) context_t;
    7474

  • kernel/arch/amd64/include/context_offset.h

    rfb150d78 r46c20c8  
    3030#define KERN_amd64_CONTEXT_OFFSET_H_
    3131
    32 #define OFFSET_SP  0x0
    33 #define OFFSET_PC  0x8
    34 #define OFFSET_RBX 0x10
    35 #define OFFSET_RBP 0x18
    36 #define OFFSET_R12 0x20
    37 #define OFFSET_R13 0x28
    38 #define OFFSET_R14 0x30
    39 #define OFFSET_R15 0x38
     32#define OFFSET_SP   0x00
     33#define OFFSET_PC   0x08
     34#define OFFSET_RBX  0x10
     35#define OFFSET_RBP  0x18
     36#define OFFSET_R12  0x20
     37#define OFFSET_R13  0x28
     38#define OFFSET_R14  0x30
     39#define OFFSET_R15  0x38
    4040
    4141#ifdef KERNEL
    42 # define OFFSET_IPL 0x40
     42        #define OFFSET_IPL 0x40
    4343#else
    44 # define OFFSET_TLS 0x40
     44        #define OFFSET_TLS 0x40
    4545#endif
    4646
    4747#ifdef __ASM__
    4848
    49 # ctx: address of the structure with saved context 
     49# ctx: address of the structure with saved context
    5050# pc: return address
    5151.macro CONTEXT_SAVE_ARCH_CORE ctx:req pc:req
    … …  
    6161.endm
    6262
    63 # ctx: address of the structure with saved context 
     63# ctx: address of the structure with saved context
    6464.macro CONTEXT_RESTORE_ARCH_CORE ctx:req pc:req
    6565        movq OFFSET_R15(\ctx), %r15
    … …  
    6868        movq OFFSET_R12(\ctx), %r12
    6969        movq OFFSET_RBP(\ctx), %rbp
    70         movq OFFSET_RBX(\ctx), %rbx     
     70        movq OFFSET_RBX(\ctx), %rbx
    7171       
    7272        movq OFFSET_SP(\ctx), %rsp   # ctx->sp -> %rsp

  • kernel/arch/amd64/include/cpu.h

    rfb150d78 r46c20c8  
    3636#define KERN_amd64_CPU_H_
    3737
    38 #define RFLAGS_CF       (1 << 0)
    39 #define RFLAGS_PF       (1 << 2)
    40 #define RFLAGS_AF       (1 << 4)
    41 #define RFLAGS_ZF       (1 << 6)
    42 #define RFLAGS_SF       (1 << 7)
    43 #define RFLAGS_TF       (1 << 8)
    44 #define RFLAGS_IF       (1 << 9)
    45 #define RFLAGS_DF       (1 << 10)
    46 #define RFLAGS_OF       (1 << 11)
    47 #define RFLAGS_RF       (1 << 16)
     38#define RFLAGS_CF  (1 << 0)
     39#define RFLAGS_PF  (1 << 2)
     40#define RFLAGS_AF  (1 << 4)
     41#define RFLAGS_ZF  (1 << 6)
     42#define RFLAGS_SF  (1 << 7)
     43#define RFLAGS_TF  (1 << 8)
     44#define RFLAGS_IF  (1 << 9)
     45#define RFLAGS_DF  (1 << 10)
     46#define RFLAGS_OF  (1 << 11)
     47#define RFLAGS_NT  (1 << 14)
     48#define RFLAGS_RF  (1 << 16)
    4849
    4950#define EFER_MSR_NUM    0xc0000080

  • kernel/arch/amd64/include/cpuid.h

    rfb150d78 r46c20c8  
    4848#ifndef __ASM__
    4949
    50 #include <arch/types.h>
     50#include <typedefs.h>
    5151
    5252typedef struct {

  • kernel/arch/amd64/include/cycle.h

    rfb150d78 r46c20c8  
    3636#define KERN_amd64_CYCLE_H_
    3737
    38 extern uint64_t get_cycle(void);
     38#include <trace.h>
     39
     40NO_TRACE static inline uint64_t get_cycle(void)
     41{
     42        uint32_t lower;
     43        uint32_t upper;
     44       
     45        asm volatile (
     46                "rdtsc\n"
     47                : "=a" (lower),
     48                  "=d" (upper)
     49        );
     50       
     51        return ((uint64_t) lower) | (((uint64_t) upper) << 32);
     52}
    3953
    4054#endif

  • kernel/arch/amd64/include/ddi/ddi.h

    rfb150d78 r46c20c8  
    3333/**
    3434 * @file
    35  * @brief       amd64 specific DDI declarations and macros.
     35 * @brief amd64 specific DDI declarations and macros.
    3636 */
    3737

  • kernel/arch/amd64/include/debugger.h

    rfb150d78 r46c20c8  
    3636#define KERN_amd64_DEBUGGER_H_
    3737
    38 #include <arch/types.h>
     38#include <typedefs.h>
    3939
    40 #define BKPOINTS_MAX 4
     40#define BKPOINTS_MAX  4
    4141
    4242/* Flags that are passed to breakpoint_add function */
    43 #define BKPOINT_INSTR        0x1
    44 #define BKPOINT_WRITE        0x2
    45 #define BKPOINT_READ_WRITE   0x4
     43#define BKPOINT_INSTR       0x1U
     44#define BKPOINT_WRITE       0x2U
     45#define BKPOINT_READ_WRITE  0x4U
    4646
    47 #define BKPOINT_CHECK_ZERO   0x8
     47#define BKPOINT_CHECK_ZERO  0x8U
    4848
    4949
    5050extern void debugger_init(void);
    51 extern int breakpoint_add(const void *where, const int flags, int curidx);
    52 extern void breakpoint_del(int slot);
     51extern int breakpoint_add(const void *, const unsigned int, int);
     52extern void breakpoint_del(int);
    5353
    5454#endif

  • kernel/arch/amd64/include/elf.h

    rfb150d78 r46c20c8  
    2727 */
    2828
    29 /** @addtogroup amd64   
     29/** @addtogroup amd64
    3030 * @{
    3131 */
    … …  
    3636#define KERN_amd64_ELF_H_
    3737
    38 #define ELF_MACHINE             EM_X86_64
    39 #define ELF_DATA_ENCODING       ELFDATA2LSB
    40 #define ELF_CLASS               ELFCLASS64
     38#define ELF_MACHINE        EM_X86_64
     39#define ELF_DATA_ENCODING  ELFDATA2LSB
     40#define ELF_CLASS          ELFCLASS64
    4141
    4242#endif

  • kernel/arch/amd64/include/faddr.h

    rfb150d78 r46c20c8  
    2727 */
    2828
    29 /** @addtogroup amd64   
     29/** @addtogroup amd64
    3030 * @{
    3131 */
    … …  
    3636#define KERN_amd64_FADDR_H_
    3737
    38 #include <arch/types.h>
     38#include <typedefs.h>
    3939
    40 #define FADDR(fptr)             ((uintptr_t) (fptr))
     40#define FADDR(fptr)  ((uintptr_t) (fptr))
    4141
    4242#endif

  • kernel/arch/amd64/include/interrupt.h

    rfb150d78 r46c20c8  
    3636#define KERN_amd64_INTERRUPT_H_
    3737
    38 #include <arch/types.h>
     38#include <typedefs.h>
     39#include <arch/istate.h>
    3940#include <arch/pm.h>
    4041
    41 #define IVT_ITEMS               IDT_ITEMS
    42 #define IVT_FIRST               0
     42#define IVT_ITEMS  IDT_ITEMS
     43#define IVT_FIRST  0
    4344
    44 #define EXC_COUNT               32
    45 #define IRQ_COUNT               16
     45#define EXC_COUNT  32
     46#define IRQ_COUNT  16
    4647
    47 #define IVT_EXCBASE             0
    48 #define IVT_IRQBASE             (IVT_EXCBASE + EXC_COUNT)
    49 #define IVT_FREEBASE            (IVT_IRQBASE + IRQ_COUNT)
     48#define IVT_EXCBASE   0
     49#define IVT_IRQBASE   (IVT_EXCBASE + EXC_COUNT)
     50#define IVT_FREEBASE  (IVT_IRQBASE + IRQ_COUNT)
    5051
    51 #define IRQ_CLK                 0
    52 #define IRQ_KBD                 1
    53 #define IRQ_PIC1                2
    54 #define IRQ_PIC_SPUR            7
    55 #define IRQ_MOUSE               12
     52#define IRQ_CLK       0
     53#define IRQ_KBD       1
     54#define IRQ_PIC1      2
     55#define IRQ_PIC_SPUR  7
     56#define IRQ_MOUSE     12
     57#define IRQ_DP8390    9
    5658
    57 /* this one must have four least significant bits set to ones */
    58 #define VECTOR_APIC_SPUR        (IVT_ITEMS - 1)
     59/* This one must have four least significant bits set to ones */
     60#define VECTOR_APIC_SPUR  (IVT_ITEMS - 1)
    5961
    6062#if (((VECTOR_APIC_SPUR + 1) % 16) || VECTOR_APIC_SPUR >= IVT_ITEMS)
    … …  
    6264#endif
    6365
    64 #define VECTOR_DEBUG                    1
    65 #define VECTOR_CLK                      (IVT_IRQBASE + IRQ_CLK)
    66 #define VECTOR_PIC_SPUR                 (IVT_IRQBASE + IRQ_PIC_SPUR)
    67 #define VECTOR_SYSCALL                  IVT_FREEBASE
    68 #define VECTOR_TLB_SHOOTDOWN_IPI        (IVT_FREEBASE + 1)
    69 #define VECTOR_DEBUG_IPI                (IVT_FREEBASE + 2)
     66#define VECTOR_DEBUG              1
     67#define VECTOR_CLK                (IVT_IRQBASE + IRQ_CLK)
     68#define VECTOR_PIC_SPUR           (IVT_IRQBASE + IRQ_PIC_SPUR)
     69#define VECTOR_SYSCALL            IVT_FREEBASE
     70#define VECTOR_TLB_SHOOTDOWN_IPI  (IVT_FREEBASE + 1)
     71#define VECTOR_DEBUG_IPI          (IVT_FREEBASE + 2)
    7072
    71 /** This is passed to interrupt handlers */
    72 typedef struct istate {
    73         uint64_t rax;
    74         uint64_t rcx;
    75         uint64_t rdx;
    76         uint64_t rsi;
    77         uint64_t rdi;
    78         uint64_t r8;
    79         uint64_t r9;
    80         uint64_t r10;
    81         uint64_t r11;
    82         uint64_t rbp;
    83         uint64_t error_word;
    84         uint64_t rip;
    85         uint64_t cs;
    86         uint64_t rflags;
    87         uint64_t stack[]; /* Additional data on stack */
    88 } istate_t;
    89 
    90 /** Return true if exception happened while in userspace */
    91 static inline int istate_from_uspace(istate_t *istate)
    92 {
    93         return !(istate->rip & 0x8000000000000000);
    94 }
    95 
    96 static inline void istate_set_retaddr(istate_t *istate, uintptr_t retaddr)
    97 {
    98         istate->rip = retaddr;
    99 }
    100 static inline unative_t istate_get_pc(istate_t *istate)
    101 {
    102         return istate->rip;
    103 }
    104 static inline unative_t istate_get_fp(istate_t *istate)
    105 {
    106         return istate->rbp;
    107 }
    108 
    109 extern void (* disable_irqs_function)(uint16_t irqmask);
    110 extern void (* enable_irqs_function)(uint16_t irqmask);
     73extern void (* disable_irqs_function)(uint16_t);
     74extern void (* enable_irqs_function)(uint16_t);
    11175extern void (* eoi_function)(void);
    11276
    113 extern void decode_istate(int n, istate_t *istate);
    11477extern void interrupt_init(void);
    115 extern void trap_virtual_enable_irqs(uint16_t irqmask);
    116 extern void trap_virtual_disable_irqs(uint16_t irqmask);
    117 /* AMD64 - specific page handler */
    118 extern void ident_page_fault(int n, istate_t *istate);
     78extern void trap_virtual_enable_irqs(uint16_t);
     79extern void trap_virtual_disable_irqs(uint16_t);
    11980
    12081#endif

  • kernel/arch/amd64/include/memstr.h

    rfb150d78 r46c20c8  
    2727 */
    2828
    29 /** @addtogroup amd64   
     29/** @addtogroup amd64
    3030 * @{
    3131 */
    … …  
    3838#define memcpy(dst, src, cnt)  __builtin_memcpy((dst), (src), (cnt))
    3939
    40 extern void memsetw(void *dst, size_t cnt, uint16_t x);
    41 extern void memsetb(void *dst, size_t cnt, uint8_t x);
    42 
    43 extern int memcmp(const void *a, const void *b, size_t cnt);
     40extern void memsetw(void *, size_t, uint16_t);
     41extern void memsetb(void *, size_t, uint8_t);
    4442
    4543#endif

  • kernel/arch/amd64/include/mm/as.h

    rfb150d78 r46c20c8  
    2727 */
    2828
    29 /** @addtogroup amd64mm 
     29/** @addtogroup amd64mm
    3030 * @{
    3131 */
    … …  
    3636#define KERN_amd64_AS_H_
    3737
    38 #define KERNEL_ADDRESS_SPACE_SHADOWED_ARCH      0
     38#define ADDRESS_SPACE_HOLE_START  UINT64_C(0x0000800000000000)
     39#define ADDRESS_SPACE_HOLE_END    UINT64_C(0xffff7fffffffffff)
    3940
    40 #define KERNEL_ADDRESS_SPACE_START_ARCH         (unsigned long) 0xffff800000000000
    41 #define KERNEL_ADDRESS_SPACE_END_ARCH           (unsigned long) 0xffffffff80000000
    42 #define USER_ADDRESS_SPACE_START_ARCH           (unsigned long) 0x0000000000000000
    43 #define USER_ADDRESS_SPACE_END_ARCH             (unsigned long) 0x00007fffffffffff
     41#define KERNEL_ADDRESS_SPACE_SHADOWED_ARCH  0
    4442
    45 #define USTACK_ADDRESS_ARCH     (USER_ADDRESS_SPACE_END_ARCH-(PAGE_SIZE-1))
     43#define KERNEL_ADDRESS_SPACE_START_ARCH  UINT64_C(0xffff800000000000)
     44#define KERNEL_ADDRESS_SPACE_END_ARCH    UINT64_C(0xffffffffffffffff)
    4645
    47 #define as_constructor_arch(as, flags)          (as != as)
    48 #define as_destructor_arch(as)                  (as != as)
    49 #define as_create_arch(as, flags)               (as != as)
     46#define USER_ADDRESS_SPACE_START_ARCH  UINT64_C(0x0000000000000000)
     47#define USER_ADDRESS_SPACE_END_ARCH    UINT64_C(0x00007fffffffffff)
     48
     49#define USTACK_ADDRESS_ARCH  (USER_ADDRESS_SPACE_END_ARCH - (PAGE_SIZE - 1))
     50
     51#define as_constructor_arch(as, flags)  (as != as)
     52#define as_destructor_arch(as)          (as != as)
     53#define as_create_arch(as, flags)       (as != as)
     54
    5055#define as_install_arch(as)
    5156#define as_deinstall_arch(as)

  • kernel/arch/amd64/include/mm/frame.h

    rfb150d78 r46c20c8  
    3636#define KERN_amd64_FRAME_H_
    3737
    38 #ifndef __ASM__
    39 #include <arch/types.h>
    40 #endif /* __ASM__ */
    41 
    4238#define FRAME_WIDTH  12  /* 4K */
    4339#define FRAME_SIZE   (1 << FRAME_WIDTH)
    4440
     41#ifdef KERNEL
    4542#ifndef __ASM__
     43
     44#include <typedefs.h>
     45
    4646extern uintptr_t last_frame;
    4747extern void frame_arch_init(void);
    4848extern void physmem_print(void);
     49
    4950#endif /* __ASM__ */
     51#endif /* KERNEL */
    5052
    5153#endif

  • kernel/arch/amd64/include/mm/page.h

    rfb150d78 r46c20c8  
    3535/** Paging on AMD64
    3636 *
    37  * The space is divided in positive numbers - userspace and
    38  * negative numbers - kernel space. The 'negative' space starting
    39  * with 0xffff800000000000 and ending with 0xffffffff80000000
    40  * (-2GB) is identically mapped physical memory. The area
    41  * (0xffffffff80000000 ... 0xffffffffffffffff is again identically
    42  * mapped first 2GB.
    43  *
    44  * ATTENTION - PA2KA(KA2PA(x)) != x if 'x' is in kernel
     37 * The space is divided in positive numbers (uspace) and
     38 * negative numbers (kernel). The 'negative' space starting
     39 * with 0xffff800000000000 and ending with 0xffffffffffffffff
     40 * is identically mapped physical memory.
     41 *
    4542 */
    4643
    … …  
    4946
    5047#include <arch/mm/frame.h>
    51 
    52 #define PAGE_WIDTH      FRAME_WIDTH
    53 #define PAGE_SIZE       FRAME_SIZE
     48#include <trace.h>
     49
     50#define PAGE_WIDTH  FRAME_WIDTH
     51#define PAGE_SIZE   FRAME_SIZE
    5452
    5553#ifdef KERNEL
    5654
    5755#ifndef __ASM__
    58 #       include <mm/mm.h>
    59 #       include <arch/types.h>
    60 #       include <arch/interrupt.h>
    61 
    62 static inline uintptr_t ka2pa(uintptr_t x)
    63 {
    64         if (x > 0xffffffff80000000)
    65                 return x - 0xffffffff80000000;
    66         else
    67                 return x - 0xffff800000000000;
    68 }
    69 
    70 #       define KA2PA(x)         ka2pa((uintptr_t) x)
    71 #       define PA2KA_CODE(x)    (((uintptr_t) (x)) + 0xffffffff80000000)
    72 #       define PA2KA(x)         (((uintptr_t) (x)) + 0xffff800000000000)
    73 #else
    74 #       define KA2PA(x)         ((x) - 0xffffffff80000000)
    75 #       define PA2KA(x)         ((x) + 0xffffffff80000000)
    76 #endif
     56
     57#define KA2PA(x)  (((uintptr_t) (x)) - UINT64_C(0xffff800000000000))
     58#define PA2KA(x)  (((uintptr_t) (x)) + UINT64_C(0xffff800000000000))
     59
     60#else /* __ASM__ */
     61
     62#define KA2PA(x)  ((x) - 0xffff800000000000)
     63#define PA2KA(x)  ((x) + 0xffff800000000000)
     64
     65#endif /* __ASM__ */
    7766
    7867/* Number of entries in each level. */
    79 #define PTL0_ENTRIES_ARCH       512
    80 #define PTL1_ENTRIES_ARCH       512
    81 #define PTL2_ENTRIES_ARCH       512
    82 #define PTL3_ENTRIES_ARCH       512
     68#define PTL0_ENTRIES_ARCH  512
     69#define PTL1_ENTRIES_ARCH  512
     70#define PTL2_ENTRIES_ARCH  512
     71#define PTL3_ENTRIES_ARCH  512
    8372
    8473/* Page table sizes for each level. */
    85 #define PTL0_SIZE_ARCH          ONE_FRAME
    86 #define PTL1_SIZE_ARCH          ONE_FRAME
    87 #define PTL2_SIZE_ARCH          ONE_FRAME
    88 #define PTL3_SIZE_ARCH          ONE_FRAME
     74#define PTL0_SIZE_ARCH  ONE_FRAME
     75#define PTL1_SIZE_ARCH  ONE_FRAME
     76#define PTL2_SIZE_ARCH  ONE_FRAME
     77#define PTL3_SIZE_ARCH  ONE_FRAME
    8978
    9079/* Macros calculating indices into page tables in each level. */
    91 #define PTL0_INDEX_ARCH(vaddr)  (((vaddr) >> 39) & 0x1ff)
    92 #define PTL1_INDEX_ARCH(vaddr)  (((vaddr) >> 30) & 0x1ff)
    93 #define PTL2_INDEX_ARCH(vaddr)  (((vaddr) >> 21) & 0x1ff)
    94 #define PTL3_INDEX_ARCH(vaddr)  (((vaddr) >> 12) & 0x1ff)
     80#define PTL0_INDEX_ARCH(vaddr)  (((vaddr) >> 39) & 0x1ffU)
     81#define PTL1_INDEX_ARCH(vaddr)  (((vaddr) >> 30) & 0x1ffU)
     82#define PTL2_INDEX_ARCH(vaddr)  (((vaddr) >> 21) & 0x1ffU)
     83#define PTL3_INDEX_ARCH(vaddr)  (((vaddr) >> 12) & 0x1ffU)
    9584
    9685/* Get PTE address accessors for each level. */
    … …  
    156145#ifndef __ASM__
    157146
     147#include <mm/mm.h>
     148#include <arch/interrupt.h>
     149#include <typedefs.h>
     150
    158151/* Page fault error codes. */
    159152
    … …  
    161154 * page.
    162155 */
    163 #define PFERR_CODE_P            (1 << 0) 
     156#define PFERR_CODE_P  (1 << 0)
    164157
    165158/** When bit on this position is 1, the page fault was caused by a write. */
    166 #define PFERR_CODE_RW           (1 << 1)
     159#define PFERR_CODE_RW  (1 << 1)
    167160
    168161/** When bit on this position is 1, the page fault was caused in user mode. */
    169 #define PFERR_CODE_US           (1 << 2)
     162#define PFERR_CODE_US  (1 << 2)
    170163
    171164/** When bit on this position is 1, a reserved bit was set in page directory. */
    172 #define PFERR_CODE_RSVD         (1 << 3)
     165#define PFERR_CODE_RSVD  (1 << 3)
    173166
    174167/** When bit on this position os 1, the page fault was caused during instruction
    175168 * fecth.
    176169 */
    177 #define PFERR_CODE_ID           (1 << 4)
     170#define PFERR_CODE_ID  (1 << 4)
    178171
    179172/** Page Table Entry. */
    180173typedef struct {
    181         unsigned present : 1;
    182         unsigned writeable : 1;
    183         unsigned uaccessible : 1;
    184         unsigned page_write_through : 1;
    185         unsigned page_cache_disable : 1;
    186         unsigned accessed : 1;
    187         unsigned dirty : 1;
    188         unsigned unused: 1;
    189         unsigned global : 1;
    190         unsigned soft_valid : 1;                /**< Valid content even if present bit is cleared. */
    191         unsigned avl : 2;
    192         unsigned addr_12_31 : 30;
    193         unsigned addr_32_51 : 21;
    194         unsigned no_execute : 1;
     174        unsigned int present : 1;
     175        unsigned int writeable : 1;
     176        unsigned int uaccessible : 1;
     177        unsigned int page_write_through : 1;
     178        unsigned int page_cache_disable : 1;
     179        unsigned int accessed : 1;
     180        unsigned int dirty : 1;
     181        unsigned int unused: 1;
     182        unsigned int global : 1;
     183        unsigned int soft_valid : 1;  /**< Valid content even if present bit is cleared. */
     184        unsigned int avl : 2;
     185        unsigned int addr_12_31 : 30;
     186        unsigned int addr_32_51 : 21;
     187        unsigned int no_execute : 1;
    195188} __attribute__ ((packed)) pte_t;
    196189
    197 static inline unsigned int get_pt_flags(pte_t *pt, size_t i)
     190NO_TRACE static inline unsigned int get_pt_flags(pte_t *pt, size_t i)
    198191{
    199192        pte_t *p = &pt[i];
    … …  
    208201}
    209202
    210 static inline void set_pt_addr(pte_t *pt, size_t i, uintptr_t a)
     203NO_TRACE static inline void set_pt_addr(pte_t *pt, size_t i, uintptr_t a)
    211204{
    212205        pte_t *p = &pt[i];
    213 
    214         p->addr_12_31 = (a >> 12) & 0xfffff;
     206       
     207        p->addr_12_31 = (a >> 12) & UINT32_C(0xfffff);
    215208        p->addr_32_51 = a >> 32;
    216209}
    217210
    218 static inline void set_pt_flags(pte_t *pt, size_t i, int flags)
     211NO_TRACE static inline void set_pt_flags(pte_t *pt, size_t i, int flags)
    219212{
    220213        pte_t *p = &pt[i];
    … …  
    234227
    235228extern void page_arch_init(void);
    236 extern void page_fault(int n, istate_t *istate);
     229extern void page_fault(unsigned int, istate_t *);
    237230
    238231#endif /* __ASM__ */

  • kernel/arch/amd64/include/mm/ptl.h

    rfb150d78 r46c20c8  
    2727 */
    2828
    29 /** @addtogroup amd64mm 
     29/** @addtogroup amd64mm
    3030 * @{
    3131 */
    … …  
    3636#define KERN_amd64_PTL_H_
    3737
    38 #define PTL_NO_EXEC       (1<<63)
    39 #define PTL_ACCESSED      (1<<5)
    40 #define PTL_CACHE_DISABLE (1<<4)
    41 #define PTL_CACHE_THROUGH (1<<3)
    42 #define PTL_USER          (1<<2)
    43 #define PTL_WRITABLE      (1<<1)
    44 #define PTL_PRESENT       1
    45 #define PTL_2MB_PAGE      (1<<7)
     38#define PTL_NO_EXEC        (1 << 63)
     39#define PTL_ACCESSED       (1 << 5)
     40#define PTL_CACHE_DISABLE  (1 << 4)
     41#define PTL_CACHE_THROUGH  (1 << 3)
     42#define PTL_USER           (1 << 2)
     43#define PTL_WRITABLE       (1 << 1)
     44#define PTL_PRESENT        1
     45#define PTL_2MB_PAGE       (1 << 7)
    4646
    4747

  • kernel/arch/amd64/include/mm/tlb.h

    rfb150d78 r46c20c8  
    2727 */
    2828
    29 /** @addtogroup amd64mm 
     29/** @addtogroup amd64mm
    3030 * @{
    3131 */

  • kernel/arch/amd64/include/pm.h

    rfb150d78 r46c20c8  
    3737
    3838#ifndef __ASM__
    39         #include <arch/types.h>
     39        #include <typedefs.h>
    4040        #include <arch/context.h>
    4141#endif
    … …  
    6565#endif /* CONFIG_FB */
    6666
    67 #define gdtselector(des)  ((des) << 3)
    68 #define idtselector(des)  ((des) << 4)
     67#define GDT_SELECTOR(des)  ((des) << 3)
    6968
    7069#define PL_KERNEL  0
    7170#define PL_USER    3
    7271
    73 #define AR_PRESENT   ( 1 << 7)
     72#define AR_PRESENT    (1 << 7)
    7473#define AR_DATA       (2 << 3)
    7574#define AR_CODE       (3 << 3)
    7675#define AR_WRITABLE   (1 << 1)
    7776#define AR_READABLE   (1 << 1)
    78 #define AR_TSS        (0x09)
    79 #define AR_INTERRUPT  (0x0e)
    80 #define AR_TRAP       (0x0f)
     77#define AR_TSS        (0x09U)
     78#define AR_INTERRUPT  (0x0eU)
     79#define AR_TRAP       (0x0fU)
    8180
    8281#define DPL_KERNEL  (PL_KERNEL << 5)
    … …  
    8483
    8584#define TSS_BASIC_SIZE  104
    86 #define TSS_IOMAP_SIZE  (16 * 1024 + 1)  /* 16K for bitmap + 1 terminating byte for convenience */
     85#define TSS_IOMAP_SIZE  (8 * 1024 + 1)  /* 8K for bitmap + 1 terminating byte for convenience */
    8786
    8887#define IO_PORTS  (64 * 1024)
    … …  
    168167
    169168extern ptr_16_64_t gdtr;
    170 extern ptr_16_32_t bootstrap_gdtr;
    171169extern ptr_16_32_t protected_ap_gdtr;
    172170

  • kernel/arch/amd64/include/proc/task.h

    rfb150d78 r46c20c8  
    3636#define KERN_amd64_TASK_H_
    3737
    38 #include <arch/types.h>
     38#include <typedefs.h>
    3939#include <adt/bitmap.h>
    4040

  • kernel/arch/amd64/include/proc/thread.h

    rfb150d78 r46c20c8  
    3737
    3838/* CAUTION: keep these in sync with low level assembly code in syscall_entry */
    39 #define SYSCALL_USTACK_RSP      0
    40 #define SYSCALL_KSTACK_RSP      1
     39#define SYSCALL_USTACK_RSP  0
     40#define SYSCALL_KSTACK_RSP  1
    4141
    4242typedef struct {
    4343        unative_t tls;
    4444        /** User and kernel RSP for syscalls. */
    45         uint64_t syscall_rsp[2];       
     45        uint64_t syscall_rsp[2];
    4646} thread_arch_t;
    4747

  • kernel/arch/amd64/include/types.h

    rfb150d78 r46c20c8  
    3636#define KERN_amd64_TYPES_H_
    3737
    38 typedef signed char int8_t;
    39 typedef signed short int16_t;
    40 typedef signed int int32_t;
    41 typedef signed long long int64_t;
    42 
    43 typedef unsigned char uint8_t;
    44 typedef unsigned short uint16_t;
    45 typedef unsigned int uint32_t;
    46 typedef unsigned long long uint64_t;
    47 
    4838typedef uint64_t size_t;
    4939
    … …  
    5545typedef uint64_t unative_t;
    5646typedef int64_t native_t;
     47typedef uint64_t atomic_count_t;
    5748
    5849typedef struct {
    5950} fncptr_t;
    6051
    61 /**< Formats for uintptr_t, size_t */
    62 #define PRIp "llx"
    63 #define PRIs "llu"
     52#define INTN_C(c)   INT64_C(c)
     53#define UINTN_C(c)  UINT64_C(c)
    6454
    65 /**< Formats for (u)int8_t, (u)int16_t, (u)int32_t, (u)int64_t and (u)native_t */
    66 #define PRId8 "d"
    67 #define PRId16 "d"
    68 #define PRId32 "d"
    69 #define PRId64 "lld"
    70 #define PRIdn "lld"
    71 
    72 #define PRIu8 "u"
    73 #define PRIu16 "u"
    74 #define PRIu32 "u"
    75 #define PRIu64 "llu"
    76 #define PRIun "llu"
    77 
    78 #define PRIx8 "x"
    79 #define PRIx16 "x"
    80 #define PRIx32 "x"
    81 #define PRIx64 "llx"
    82 #define PRIxn "llx"
     55#define PRIdn  PRId64  /**< Format for native_t. */
     56#define PRIun  PRIu64  /**< Format for unative_t. */
     57#define PRIxn  PRIx64  /**< Format for hexadecimal unative_t. */
     58#define PRIua  PRIu64  /**< Format for atomic_count_t. */
    8359
    8460#endif
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