Changeset 469e0cf in mainline
- Timestamp:
- 2012-08-31T16:48:36Z (12 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- 054fd442
- Parents:
- 9cf07b3
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
kernel/genarch/include/drivers/amdm37x_dispc/amdm37x_dispc.h
r9cf07b3 r469e0cf 49 49 typedef struct { 50 50 const ioport32_t revision; 51 #define AMDM D37X_DISPC_REVISION_MASK 0xff51 #define AMDM37X_DISPC_REVISION_MASK 0xff 52 52 53 53 PADD32(3); 54 54 ioport32_t sysconfig; 55 #define AMDM D37X_DISPC_SYSCONFIG_AUTOIDLE_FLAG (1 << 0)56 #define AMDM D37X_DISPC_SYSCONFIG_SOFTRESET_FLAG (1 << 1)57 #define AMDM D37X_DISPC_SYSCONFIG_ENWAKEUP_FLAG (1 << 2)58 #define AMDM D37X_DISPC_SYSCONFIG_SIDLEMODE_MASK 0x359 #define AMDM D37X_DISPC_SYSCONFIG_SIDLEMODE_SHIFT 360 #define AMDM D37X_DISPC_SYSCONFIG_CLOCKACTIVITY_MASK 0x361 #define AMDM D37X_DISPC_SYSCONFIG_CLOCKACTIVITY_SHIFT 862 #define AMDM D37X_DISPC_SYSCONFIG_MIDLEMODE_MASK 0x363 #define AMDM D37X_DISPC_SYSCONFIG_MIDLEMODE_SHIFT 1255 #define AMDM37X_DISPC_SYSCONFIG_AUTOIDLE_FLAG (1 << 0) 56 #define AMDM37X_DISPC_SYSCONFIG_SOFTRESET_FLAG (1 << 1) 57 #define AMDM37X_DISPC_SYSCONFIG_ENWAKEUP_FLAG (1 << 2) 58 #define AMDM37X_DISPC_SYSCONFIG_SIDLEMODE_MASK 0x3 59 #define AMDM37X_DISPC_SYSCONFIG_SIDLEMODE_SHIFT 3 60 #define AMDM37X_DISPC_SYSCONFIG_CLOCKACTIVITY_MASK 0x3 61 #define AMDM37X_DISPC_SYSCONFIG_CLOCKACTIVITY_SHIFT 8 62 #define AMDM37X_DISPC_SYSCONFIG_MIDLEMODE_MASK 0x3 63 #define AMDM37X_DISPC_SYSCONFIG_MIDLEMODE_SHIFT 12 64 64 65 65 const ioport32_t sysstatus; 66 #define AMDM D37X_DISPC_SYSSTATUS_RESETDONE_FLAG (1 << 0)66 #define AMDM37X_DISPC_SYSSTATUS_RESETDONE_FLAG (1 << 0) 67 67 68 68 ioport32_t irqstatus; 69 69 ioport32_t irqenable; 70 #define AMDM D37X_DISPC_IRQ_FRAMEDONE_FLAG (1 << 0)71 #define AMDM D37X_DISPC_IRQ_VSYNC_FLAG (1 << 1)72 #define AMDM D37X_DISPC_IRQ_EVSYNCEVEN_FLAG (1 << 2)73 #define AMDM D37X_DISPC_IRQ_EVSYNCODD_FLAG (1 << 3)74 #define AMDM D37X_DISPC_IRQ_ACBIASCOUNTSTATUS_FLAG (1 << 4)75 #define AMDM D37X_DISPC_IRQ_PROGRAMMEDLINENUMBER_FLAG (1 << 5)76 #define AMDM D37X_DISPC_IRQ_GFXFIFOUNDERFLOW_FLAG (1 << 6)77 #define AMDM D37X_DISPC_IRQ_GFXENDWINDOW_FLAG (1 << 7)78 #define AMDM D37X_DISPC_IRQ_PALETTEGAMMALOADING_FLAG (1 << 8)79 #define AMDM D37X_DISPC_IRQ_OPCERROR_FLAG (1 << 9)80 #define AMDM D37X_DISPC_IRQ_VID1FIFOUNDERFLOW_FLAG (1 << 10)81 #define AMDM D37X_DISPC_IRQ_VID1ENDWINDOW_FLAG (1 << 11)82 #define AMDM D37X_DISPC_IRQ_VID2FIFOUNDERFLOW_FLAG (1 << 12)83 #define AMDM D37X_DISPC_IRQ_VID2ENDWINDOW_FLAG (1 << 13)84 #define AMDM D37X_DISPC_IRQ_SYNCLOST_FLAG (1 << 14)85 #define AMDM D37X_DISPC_IRQ_SYNCLOSTDIGITAL_FLAG (1 << 15)86 #define AMDM D37X_DISPC_IRQ_WAKEUP_FLAG (1 << 16)70 #define AMDM37X_DISPC_IRQ_FRAMEDONE_FLAG (1 << 0) 71 #define AMDM37X_DISPC_IRQ_VSYNC_FLAG (1 << 1) 72 #define AMDM37X_DISPC_IRQ_EVSYNCEVEN_FLAG (1 << 2) 73 #define AMDM37X_DISPC_IRQ_EVSYNCODD_FLAG (1 << 3) 74 #define AMDM37X_DISPC_IRQ_ACBIASCOUNTSTATUS_FLAG (1 << 4) 75 #define AMDM37X_DISPC_IRQ_PROGRAMMEDLINENUMBER_FLAG (1 << 5) 76 #define AMDM37X_DISPC_IRQ_GFXFIFOUNDERFLOW_FLAG (1 << 6) 77 #define AMDM37X_DISPC_IRQ_GFXENDWINDOW_FLAG (1 << 7) 78 #define AMDM37X_DISPC_IRQ_PALETTEGAMMALOADING_FLAG (1 << 8) 79 #define AMDM37X_DISPC_IRQ_OPCERROR_FLAG (1 << 9) 80 #define AMDM37X_DISPC_IRQ_VID1FIFOUNDERFLOW_FLAG (1 << 10) 81 #define AMDM37X_DISPC_IRQ_VID1ENDWINDOW_FLAG (1 << 11) 82 #define AMDM37X_DISPC_IRQ_VID2FIFOUNDERFLOW_FLAG (1 << 12) 83 #define AMDM37X_DISPC_IRQ_VID2ENDWINDOW_FLAG (1 << 13) 84 #define AMDM37X_DISPC_IRQ_SYNCLOST_FLAG (1 << 14) 85 #define AMDM37X_DISPC_IRQ_SYNCLOSTDIGITAL_FLAG (1 << 15) 86 #define AMDM37X_DISPC_IRQ_WAKEUP_FLAG (1 << 16) 87 87 88 88 PADD32(8); 89 89 ioport32_t control; 90 #define AMDM D37X_DISPC_CONTROL_LCD_ENABLE_FLAG (1 << 0)91 #define AMDM D37X_DISPC_CONTROL_DIGITAL_ENABLE_FLAG (1 << 1)92 #define AMDM D37X_DISPC_CONTROL_MONOCOLOR_FLAG (1 << 2)93 #define AMDM D37X_DISPC_CONTROL_STNTFT_FLAG (1 << 3)94 #define AMDM D37X_DISPC_CONTROL_M8B_FLAG (1 << 4)95 #define AMDM D37X_DISPC_CONTROL_GOLCD_FLAG (1 << 5)96 #define AMDM D37X_DISPC_CONTROL_GODIGITAL_FLAG (1 << 6)97 #define AMDM D37X_DISPC_CONTROL_STDITHERENABLE_FLAG (1 << 7)98 #define AMDM D37X_DISPC_CONTROL_TFTDATALINES_MASK 0x399 #define AMDM D37X_DISPC_CONTROL_TFTDATALINES_SHIFT 8100 #define AMDM D37X_DISPC_CONTROL_TFTDATALINES_12B 0101 #define AMDM D37X_DISPC_CONTROL_TFTDATALINES_16B 1102 #define AMDM D37X_DISPC_CONTROL_TFTDATALINES_18B 2103 #define AMDM D37X_DISPC_CONTROL_TFTDATALINES_24B 3104 #define AMDM D37X_DISPC_CONTROL_STALLMODE_FLAG (1 << 11)105 #define AMDM D37X_DISPC_CONTROL_OVERLAYOPTIMIZATION_FLAG (1 << 12)106 #define AMDM D37X_DISPC_CONTROL_GPIN0_FLAG (1 << 13)107 #define AMDM D37X_DISPC_CONTROL_GPIN1_FLAG (1 << 14)108 #define AMDM D37X_DISPC_CONTROL_GPOUT0_FLAG (1 << 15)109 #define AMDM D37X_DISPC_CONTROL_GPOUT1_FLAG (1 << 16)110 #define AMDM D37X_DISPC_CONTROL_HT_MASK 0x7111 #define AMDM D37X_DISPC_CONTROL_HT_SHIFT 17112 #define AMDM D37X_DISPC_CONTROL_TDMENABLE_FLAG (1 << 20)113 #define AMDM D37X_DISPC_CONTROL_TDMPARALLELMODE_MASK 0x3114 #define AMDM D37X_DISPC_CONTROL_TDMPARELLELMODE_SHIFT 21115 #define AMDM D37X_DISPC_CONTROL_TDMCYCLEFORMAT_MASK 0x3116 #define AMDM D37X_DISPC_CONTROL_TDMCYCLEFORMAT_SHIFT 23117 #define AMDM D37X_DISPC_CONTROL_TDMUNUSEDBITS_MASK 0x3118 #define AMDM D37X_DISPC_CONTROL_TDMUNUSEDBITS_SHIFT 25119 #define AMDM D37X_DISPC_CONTROL_PCKFREEENABLE_FLAG (1 << 27)120 #define AMDM D37X_DISPC_CONTROL_LCDENABLESIGNAL_FLAG (1 << 28)121 #define AMDM D37X_DISPC_CONTROL_KCDENABLEPOL_FLAG (1 << 29)122 #define AMDM D37X_DISPC_CONTROL_SPATIALTEMPORALDITHERINGFRAMES_MASK 0x3123 #define AMDM D37X_DISPC_CONTROL_SPATIALTEMPORALDITHERINGFRAMES_SHIFT 3090 #define AMDM37X_DISPC_CONTROL_LCD_ENABLE_FLAG (1 << 0) 91 #define AMDM37X_DISPC_CONTROL_DIGITAL_ENABLE_FLAG (1 << 1) 92 #define AMDM37X_DISPC_CONTROL_MONOCOLOR_FLAG (1 << 2) 93 #define AMDM37X_DISPC_CONTROL_STNTFT_FLAG (1 << 3) 94 #define AMDM37X_DISPC_CONTROL_M8B_FLAG (1 << 4) 95 #define AMDM37X_DISPC_CONTROL_GOLCD_FLAG (1 << 5) 96 #define AMDM37X_DISPC_CONTROL_GODIGITAL_FLAG (1 << 6) 97 #define AMDM37X_DISPC_CONTROL_STDITHERENABLE_FLAG (1 << 7) 98 #define AMDM37X_DISPC_CONTROL_TFTDATALINES_MASK 0x3 99 #define AMDM37X_DISPC_CONTROL_TFTDATALINES_SHIFT 8 100 #define AMDM37X_DISPC_CONTROL_TFTDATALINES_12B 0 101 #define AMDM37X_DISPC_CONTROL_TFTDATALINES_16B 1 102 #define AMDM37X_DISPC_CONTROL_TFTDATALINES_18B 2 103 #define AMDM37X_DISPC_CONTROL_TFTDATALINES_24B 3 104 #define AMDM37X_DISPC_CONTROL_STALLMODE_FLAG (1 << 11) 105 #define AMDM37X_DISPC_CONTROL_OVERLAYOPTIMIZATION_FLAG (1 << 12) 106 #define AMDM37X_DISPC_CONTROL_GPIN0_FLAG (1 << 13) 107 #define AMDM37X_DISPC_CONTROL_GPIN1_FLAG (1 << 14) 108 #define AMDM37X_DISPC_CONTROL_GPOUT0_FLAG (1 << 15) 109 #define AMDM37X_DISPC_CONTROL_GPOUT1_FLAG (1 << 16) 110 #define AMDM37X_DISPC_CONTROL_HT_MASK 0x7 111 #define AMDM37X_DISPC_CONTROL_HT_SHIFT 17 112 #define AMDM37X_DISPC_CONTROL_TDMENABLE_FLAG (1 << 20) 113 #define AMDM37X_DISPC_CONTROL_TDMPARALLELMODE_MASK 0x3 114 #define AMDM37X_DISPC_CONTROL_TDMPARELLELMODE_SHIFT 21 115 #define AMDM37X_DISPC_CONTROL_TDMCYCLEFORMAT_MASK 0x3 116 #define AMDM37X_DISPC_CONTROL_TDMCYCLEFORMAT_SHIFT 23 117 #define AMDM37X_DISPC_CONTROL_TDMUNUSEDBITS_MASK 0x3 118 #define AMDM37X_DISPC_CONTROL_TDMUNUSEDBITS_SHIFT 25 119 #define AMDM37X_DISPC_CONTROL_PCKFREEENABLE_FLAG (1 << 27) 120 #define AMDM37X_DISPC_CONTROL_LCDENABLESIGNAL_FLAG (1 << 28) 121 #define AMDM37X_DISPC_CONTROL_KCDENABLEPOL_FLAG (1 << 29) 122 #define AMDM37X_DISPC_CONTROL_SPATIALTEMPORALDITHERINGFRAMES_MASK 0x3 123 #define AMDM37X_DISPC_CONTROL_SPATIALTEMPORALDITHERINGFRAMES_SHIFT 30 124 124 125 125 ioport32_t config; 126 #define AMDM D37X_DISPC_CONFIG_PIXELGATED_FLAG (1 << 0)127 #define AMDM D37X_DISPC_CONFIG_LOADMODE_MASK 0x3128 #define AMDM D37X_DISPC_CONFIG_LOADMODE_SHIFT 1129 #define AMDM D37X_DISPC_CONFIG_LOADMODE_PGDATAEVERYFRAME 0x0130 #define AMDM D37X_DISPC_CONFIG_LOADMODE_PGUSER 0x1131 #define AMDM D37X_DISPC_CONFIG_LOADMODE_DATAEVERYFRAME 0x2132 #define AMDM D37X_DISPC_CONFIG_LOADMODE_PGDFIRSTFRAME 0x3133 #define AMDM D37X_DISPC_CONFIG_PALETTEGAMMATABLE_FLAG (1 << 3)134 #define AMDM D37X_DISPC_CONFIG_PIXELDATAGATED_FLAG (1 << 4)135 #define AMDM D37X_DISPC_CONFIG_PIXELCLOCKGATED_FLAG (1 << 5)136 #define AMDM D37X_DISPC_CONFIG_HSYNCGATED_FLAG (1 << 6)137 #define AMDM D37X_DISPC_CONFIG_VSYNCGATED_FLAG (1 << 7)138 #define AMDM D37X_DISPC_CONFIG_ACBIASGATED_FLAG (1 << 8)139 #define AMDM D37X_DISPC_CONFIG_FUNCGATED_FLAG (1 << 9)140 #define AMDM D37X_DISPC_CONFIG_TCKLCDENABLE_FLAG (1 << 10)141 #define AMDM D37X_DISPC_CONFIG_TCKLCDSELECTION_FLAG (1 << 11)142 #define AMDM D37X_DISPC_CONFIG_TCKDIGENABLE_FLAG (1 << 12)143 #define AMDM D37X_DISPC_CONFIG_TCKDIGSELECTION_FLAG (1 << 13)144 #define AMDM D37X_DISPC_CONFIG_FIFOMERGE_FLAG (1 << 14)145 #define AMDM D37X_DISPC_CONFIG_CPR_FLAG (1 << 15)146 #define AMDM D37X_DISPC_CONFIG_FIFOHANDCHECK_FLAG (1 << 16)147 #define AMDM D37X_DISPC_CONFIG_FIFOFILLING_FLAG (1 << 17)148 #define AMDM D37X_DISPC_CONFIG_LCDPALPHABLENDERENABLDE_FLAG (1 << 18)149 #define AMDM D37X_DISPC_CONFIG_TVALPHABLENDERENABLE_FLAG (1 << 19)126 #define AMDM37X_DISPC_CONFIG_PIXELGATED_FLAG (1 << 0) 127 #define AMDM37X_DISPC_CONFIG_LOADMODE_MASK 0x3 128 #define AMDM37X_DISPC_CONFIG_LOADMODE_SHIFT 1 129 #define AMDM37X_DISPC_CONFIG_LOADMODE_PGDATAEVERYFRAME 0x0 130 #define AMDM37X_DISPC_CONFIG_LOADMODE_PGUSER 0x1 131 #define AMDM37X_DISPC_CONFIG_LOADMODE_DATAEVERYFRAME 0x2 132 #define AMDM37X_DISPC_CONFIG_LOADMODE_PGDFIRSTFRAME 0x3 133 #define AMDM37X_DISPC_CONFIG_PALETTEGAMMATABLE_FLAG (1 << 3) 134 #define AMDM37X_DISPC_CONFIG_PIXELDATAGATED_FLAG (1 << 4) 135 #define AMDM37X_DISPC_CONFIG_PIXELCLOCKGATED_FLAG (1 << 5) 136 #define AMDM37X_DISPC_CONFIG_HSYNCGATED_FLAG (1 << 6) 137 #define AMDM37X_DISPC_CONFIG_VSYNCGATED_FLAG (1 << 7) 138 #define AMDM37X_DISPC_CONFIG_ACBIASGATED_FLAG (1 << 8) 139 #define AMDM37X_DISPC_CONFIG_FUNCGATED_FLAG (1 << 9) 140 #define AMDM37X_DISPC_CONFIG_TCKLCDENABLE_FLAG (1 << 10) 141 #define AMDM37X_DISPC_CONFIG_TCKLCDSELECTION_FLAG (1 << 11) 142 #define AMDM37X_DISPC_CONFIG_TCKDIGENABLE_FLAG (1 << 12) 143 #define AMDM37X_DISPC_CONFIG_TCKDIGSELECTION_FLAG (1 << 13) 144 #define AMDM37X_DISPC_CONFIG_FIFOMERGE_FLAG (1 << 14) 145 #define AMDM37X_DISPC_CONFIG_CPR_FLAG (1 << 15) 146 #define AMDM37X_DISPC_CONFIG_FIFOHANDCHECK_FLAG (1 << 16) 147 #define AMDM37X_DISPC_CONFIG_FIFOFILLING_FLAG (1 << 17) 148 #define AMDM37X_DISPC_CONFIG_LCDPALPHABLENDERENABLDE_FLAG (1 << 18) 149 #define AMDM37X_DISPC_CONFIG_TVALPHABLENDERENABLE_FLAG (1 << 19) 150 150 151 151 PADD32(1); 152 152 ioport32_t default_color[2]; 153 153 ioport32_t trans_color[2]; 154 #define AMDM D37X_DISPC_COLOR_MASK 0xffffff154 #define AMDM37X_DISPC_COLOR_MASK 0xffffff 155 155 156 156 const ioport32_t line_status; 157 157 ioport32_t line_number; 158 #define AMDM D37X_DISPC_LINE_NUMBER_MASK 0x3ff158 #define AMDM37X_DISPC_LINE_NUMBER_MASK 0x3ff 159 159 160 160 ioport32_t timing_h; 161 #define AMDM D37X_DISPC_TIMING_H_HSW_MASK 0xff162 #define AMDM D37X_DISPC_TIMING_H_HSW_SHIFT 0163 #define AMDM D37X_DISPC_TIMING_H_HFP_MASK 0xfff164 #define AMDM D37X_DISPC_TIMING_H_HFP_SHIFT 8165 #define AMDM D37X_DISPC_TIMING_H_HBP_MASK 0xfff166 #define AMDM D37X_DISPC_TIMING_H_HBP_SHIFT 20161 #define AMDM37X_DISPC_TIMING_H_HSW_MASK 0xff 162 #define AMDM37X_DISPC_TIMING_H_HSW_SHIFT 0 163 #define AMDM37X_DISPC_TIMING_H_HFP_MASK 0xfff 164 #define AMDM37X_DISPC_TIMING_H_HFP_SHIFT 8 165 #define AMDM37X_DISPC_TIMING_H_HBP_MASK 0xfff 166 #define AMDM37X_DISPC_TIMING_H_HBP_SHIFT 20 167 167 168 168 ioport32_t timing_v; 169 #define AMDM D37X_DISPC_TIMING_V_VSW_MASK 0xff170 #define AMDM D37X_DISPC_TIMING_V_VSW_SHIFT 0171 #define AMDM D37X_DISPC_TIMING_V_VFP_MASK 0xfff172 #define AMDM D37X_DISPC_TIMING_V_VFP_SHIFT 8173 #define AMDM D37X_DISPC_TIMING_V_VBP_MASK 0xfff174 #define AMDM D37X_DISPC_TIMING_V_VBP_SHIFT 20169 #define AMDM37X_DISPC_TIMING_V_VSW_MASK 0xff 170 #define AMDM37X_DISPC_TIMING_V_VSW_SHIFT 0 171 #define AMDM37X_DISPC_TIMING_V_VFP_MASK 0xfff 172 #define AMDM37X_DISPC_TIMING_V_VFP_SHIFT 8 173 #define AMDM37X_DISPC_TIMING_V_VBP_MASK 0xfff 174 #define AMDM37X_DISPC_TIMING_V_VBP_SHIFT 20 175 175 176 176 ioport32_t pol_freq; 177 #define AMDM D37X_DISPC_POL_FREQ_ACB_MASK 0xff178 #define AMDM D37X_DISPC_POL_FREQ_ACB_SHIFT 0179 #define AMDM D37X_DISPC_POL_FREQ_ACBI_MASK 0xf180 #define AMDM D37X_DISPC_POL_FREQ_ACBI_SHIFT 8181 #define AMDM D37X_DISPC_POL_FREQ_IVS_FLAG (1 << 12)182 #define AMDM D37X_DISPC_POL_FREQ_IHS_FLAG (1 << 13)183 #define AMDM D37X_DISPC_POL_FREQ_IPC_FLAG (1 << 14)184 #define AMDM D37X_DISPC_POL_FREQ_IEO_FLAG (1 << 15)185 #define AMDM D37X_DISPC_POL_FREQ_RF_FLAG (1 << 16)186 #define AMDM D37X_DISPC_POL_FREQ_ONOFF_FLAG (1 << 17)177 #define AMDM37X_DISPC_POL_FREQ_ACB_MASK 0xff 178 #define AMDM37X_DISPC_POL_FREQ_ACB_SHIFT 0 179 #define AMDM37X_DISPC_POL_FREQ_ACBI_MASK 0xf 180 #define AMDM37X_DISPC_POL_FREQ_ACBI_SHIFT 8 181 #define AMDM37X_DISPC_POL_FREQ_IVS_FLAG (1 << 12) 182 #define AMDM37X_DISPC_POL_FREQ_IHS_FLAG (1 << 13) 183 #define AMDM37X_DISPC_POL_FREQ_IPC_FLAG (1 << 14) 184 #define AMDM37X_DISPC_POL_FREQ_IEO_FLAG (1 << 15) 185 #define AMDM37X_DISPC_POL_FREQ_RF_FLAG (1 << 16) 186 #define AMDM37X_DISPC_POL_FREQ_ONOFF_FLAG (1 << 17) 187 187 188 188 ioport32_t divisor; 189 #define AMDM D37X_DISPC_DIVISOR_PCD_MASK 0xff190 #define AMDM D37X_DISPC_DIVISOR_PCD_SHIFT 0191 #define AMDM D37X_DISPC_DIVISOR_LCD_MASK 0xff192 #define AMDM D37X_DISPC_DIVISOR_LCD_SHIFT 16189 #define AMDM37X_DISPC_DIVISOR_PCD_MASK 0xff 190 #define AMDM37X_DISPC_DIVISOR_PCD_SHIFT 0 191 #define AMDM37X_DISPC_DIVISOR_LCD_MASK 0xff 192 #define AMDM37X_DISPC_DIVISOR_LCD_SHIFT 16 193 193 194 194 ioport32_t global_alpha; 195 #define AMDM D37X_DISPC_GLOBAL_ALPHA_GFXGLOBALALPHA_MASK 0xff196 #define AMDM D37X_DISPC_GLOBAL_ALPHA_GFXGLOBALALPHA_SHIFT 0197 #define AMDM D37X_DISPC_GLOBAL_ALPHA_VID2GLOBALALPHA_MASK 0xff198 #define AMDM D37X_DISPC_GLOBAL_ALPHA_VID2GLOBALALPHA_SHIFT 16195 #define AMDM37X_DISPC_GLOBAL_ALPHA_GFXGLOBALALPHA_MASK 0xff 196 #define AMDM37X_DISPC_GLOBAL_ALPHA_GFXGLOBALALPHA_SHIFT 0 197 #define AMDM37X_DISPC_GLOBAL_ALPHA_VID2GLOBALALPHA_MASK 0xff 198 #define AMDM37X_DISPC_GLOBAL_ALPHA_VID2GLOBALALPHA_SHIFT 16 199 199 200 200 ioport32_t size_dig; … … 204 204 ioport32_t ba[2]; 205 205 ioport32_t position; 206 #define AMDM D37X_DISPC_GFX_POSITION_GFXPOSX_MASK 0x7ff207 #define AMDM D37X_DISPC_GFX_POSITION_GFXPOSX_SHIFT 0208 #define AMDM D37X_DISPC_GFX_POSITION_GFXPOSY_MASK 0x7ff209 #define AMDM D37X_DISPC_GFX_POSITION_GFXPOSY_SHIFT 16206 #define AMDM37X_DISPC_GFX_POSITION_GFXPOSX_MASK 0x7ff 207 #define AMDM37X_DISPC_GFX_POSITION_GFXPOSX_SHIFT 0 208 #define AMDM37X_DISPC_GFX_POSITION_GFXPOSY_MASK 0x7ff 209 #define AMDM37X_DISPC_GFX_POSITION_GFXPOSY_SHIFT 16 210 210 211 211 ioport32_t size; 212 #define AMDM D37X_DISPC_SIZE_WIDTH_MASK 0x7ff213 #define AMDM D37X_DISPC_SIZE_WIDTH_SHIFT 0214 #define AMDM D37X_DISPC_SIZE_HEIGHT_MASK 0x7ff215 #define AMDM D37X_DISPC_SIZE_HEIGHT_SHIFT 16212 #define AMDM37X_DISPC_SIZE_WIDTH_MASK 0x7ff 213 #define AMDM37X_DISPC_SIZE_WIDTH_SHIFT 0 214 #define AMDM37X_DISPC_SIZE_HEIGHT_MASK 0x7ff 215 #define AMDM37X_DISPC_SIZE_HEIGHT_SHIFT 16 216 216 217 217 PADD32(4); 218 218 ioport32_t attributes; 219 #define AMDM D37X_DISPC_GFX_ATTRIBUTES_ENABLE_FLAG (1 << 0)220 #define AMDM D37X_DISPC_GFX_ATTRIBUTES_FORMAT_MASK 0xf221 #define AMDM D37X_DISPC_GFX_ATTRIBUTES_FORMAT_SHIFT 0xf222 #define AMDM D37X_DISPC_GFX_ATTRIBUTES_FORMAT_ARGB16 0x5223 #define AMDM D37X_DISPC_GFX_ATTRIBUTES_FORMAT_RGB16 0x6224 #define AMDM D37X_DISPC_GFX_ATTRIBUTES_FORMAT_RGB24_32 0x9225 #define AMDM D37X_DISPC_GFX_ATTRIBUTES_FORMAT_RGB24 0x9226 #define AMDM D37X_DISPC_GFX_ATTRIBUTES_FORMAT_ARGB 0xc227 #define AMDM D37X_DISPC_GFX_ATTRIBUTES_FORMAT_RGBA 0xd228 #define AMDM D37X_DISPC_GFX_ATTRIBUTES_FORMAT_RGBX 0xe229 #define AMDM D37X_DISPC_GFX_ATTRIBUTES_REPLICATIONENABLE_FLAG (1 << 5)230 #define AMDM D37X_DISPC_GFX_ATTRIBUTES_GFXBURSTSIZE_MASK 0x3231 #define AMDM D37X_DISPC_GFX_ATTRIBUTES_GFXBURSTSIZE_SHIFT 6232 #define AMDM D37X_DISPC_GFX_ATTRIBUTES_GFXCHANNELOUT_FLAG (1 << 8)233 #define AMDM D37X_DISPC_GFX_ATTRIBUTES_GFXNIBBLEMODE_FLAG (1 << 9)234 #define AMDM D37X_DISPC_GFX_ATTRIBUTES_GFXENDIANNES_FLAG (1 << 10)235 #define AMDM D37X_DISPC_GFX_ATTRIBUTES_GFXFIFOPRELOAD_FLAG (1 << 11)236 #define AMDM D37X_DISPC_GFX_ATTRIBUTES_GFXROTATION_MASK 0x3237 #define AMDM D37X_DISPC_GFX_ATTRIBUTES_GFXROTATION_SHIFT 12238 #define AMDM D37X_DISPC_GFX_ATTRIBUTES_GFXARBITRATION_FLAG (1 << 14)239 #define AMDM D37X_DISPC_GFX_ATTRIBUTES_GFXSELFREFRESH_FLAG (1 << 15)240 #define AMDM D37X_DISPC_GFX_ATTRIBUTES_PREMULTIALPHA_FLAG (1 << 28)219 #define AMDM37X_DISPC_GFX_ATTRIBUTES_ENABLE_FLAG (1 << 0) 220 #define AMDM37X_DISPC_GFX_ATTRIBUTES_FORMAT_MASK 0xf 221 #define AMDM37X_DISPC_GFX_ATTRIBUTES_FORMAT_SHIFT 1 222 #define AMDM37X_DISPC_GFX_ATTRIBUTES_FORMAT_ARGB16 0x5 223 #define AMDM37X_DISPC_GFX_ATTRIBUTES_FORMAT_RGB16 0x6 224 #define AMDM37X_DISPC_GFX_ATTRIBUTES_FORMAT_RGB24_32 0x9 225 #define AMDM37X_DISPC_GFX_ATTRIBUTES_FORMAT_RGB24 0x9 226 #define AMDM37X_DISPC_GFX_ATTRIBUTES_FORMAT_ARGB 0xc 227 #define AMDM37X_DISPC_GFX_ATTRIBUTES_FORMAT_RGBA 0xd 228 #define AMDM37X_DISPC_GFX_ATTRIBUTES_FORMAT_RGBX 0xe 229 #define AMDM37X_DISPC_GFX_ATTRIBUTES_REPLICATIONENABLE_FLAG (1 << 5) 230 #define AMDM37X_DISPC_GFX_ATTRIBUTES_GFXBURSTSIZE_MASK 0x3 231 #define AMDM37X_DISPC_GFX_ATTRIBUTES_GFXBURSTSIZE_SHIFT 6 232 #define AMDM37X_DISPC_GFX_ATTRIBUTES_GFXCHANNELOUT_FLAG (1 << 8) 233 #define AMDM37X_DISPC_GFX_ATTRIBUTES_GFXNIBBLEMODE_FLAG (1 << 9) 234 #define AMDM37X_DISPC_GFX_ATTRIBUTES_GFXENDIANNES_FLAG (1 << 10) 235 #define AMDM37X_DISPC_GFX_ATTRIBUTES_GFXFIFOPRELOAD_FLAG (1 << 11) 236 #define AMDM37X_DISPC_GFX_ATTRIBUTES_GFXROTATION_MASK 0x3 237 #define AMDM37X_DISPC_GFX_ATTRIBUTES_GFXROTATION_SHIFT 12 238 #define AMDM37X_DISPC_GFX_ATTRIBUTES_GFXARBITRATION_FLAG (1 << 14) 239 #define AMDM37X_DISPC_GFX_ATTRIBUTES_GFXSELFREFRESH_FLAG (1 << 15) 240 #define AMDM37X_DISPC_GFX_ATTRIBUTES_PREMULTIALPHA_FLAG (1 << 28) 241 241 242 242 … … 290 290 { 291 291 ASSERT(regs); 292 293 printf("DISPC rev: %x\n", regs->revision); 292 #define WRITE_DUMP(name, value) \ 293 printf("Writing %s %p: %x. New: %x\n", #name, ®s->name, value, regs->name) 294 /* Init sequence for dispc is in chapter 7.6.5.1.4 p. 1810, 295 * no idea what parts of that work. */ 296 297 /* Disable all interrupts */ 298 regs->irqenable = 0; 299 300 /* Pixel format specifics*/ 301 uint32_t attrib_pixel_format = 0; 302 uint32_t control_data_lanes = 0; 303 switch (bpp) 304 { 305 case 32: 306 attrib_pixel_format = AMDM37X_DISPC_GFX_ATTRIBUTES_FORMAT_RGBX; 307 control_data_lanes = AMDM37X_DISPC_CONTROL_TFTDATALINES_24B; 308 break; 309 case 24: 310 attrib_pixel_format = AMDM37X_DISPC_GFX_ATTRIBUTES_FORMAT_RGB24; 311 control_data_lanes = AMDM37X_DISPC_CONTROL_TFTDATALINES_24B; 312 break; 313 case 16: 314 attrib_pixel_format = AMDM37X_DISPC_GFX_ATTRIBUTES_FORMAT_RGB16; 315 control_data_lanes = AMDM37X_DISPC_CONTROL_TFTDATALINES_16B; 316 break; 317 default: 318 ASSERT(false); 319 } 294 320 295 321 /* Prepare sizes */ 296 322 const uint32_t size_reg = 297 (((x - 1) & AMDM D37X_DISPC_SIZE_WIDTH_MASK)298 << AMDM D37X_DISPC_SIZE_WIDTH_SHIFT) |299 (((y - 1) & AMDM D37X_DISPC_SIZE_HEIGHT_MASK)300 << AMDM D37X_DISPC_SIZE_HEIGHT_SHIFT);323 (((x - 1) & AMDM37X_DISPC_SIZE_WIDTH_MASK) 324 << AMDM37X_DISPC_SIZE_WIDTH_SHIFT) | 325 (((y - 1) & AMDM37X_DISPC_SIZE_HEIGHT_MASK) 326 << AMDM37X_DISPC_SIZE_HEIGHT_SHIFT); 301 327 302 328 /* modes taken from u-boot */ 303 329 // TODO replace magic values with actual correct values 304 regs->timing_h = 0x1a4024c9;305 regs->timing_v = 0x02c00509;306 regs->pol_freq = 0x00007028;307 regs->divisor = 0x00010001;330 // regs->timing_h = 0x1a4024c9; 331 // regs->timing_v = 0x02c00509; 332 // regs->pol_freq = 0x00007028; 333 // regs->divisor = 0x00010001; 308 334 309 335 /* setup output */ 310 336 regs->size_lcd = size_reg; 337 WRITE_DUMP(size_lcd, size_reg); 311 338 regs->size_dig = size_reg; 339 WRITE_DUMP(size_dig, size_reg); 312 340 313 341 /* Nice blue default color */ 314 342 regs->default_color[0] = 0x0000ff; 315 343 regs->default_color[1] = 0x0000ff; 316 317 /* Assume 24bit active lcd */ 318 uint32_t control = regs->control; 319 control &= ~(AMDMD37X_DISPC_CONTROL_TFTDATALINES_MASK 320 << AMDMD37X_DISPC_CONTROL_TFTDATALINES_SHIFT); 321 control |= (AMDMD37X_DISPC_CONTROL_TFTDATALINES_24B 322 << AMDMD37X_DISPC_CONTROL_TFTDATALINES_SHIFT); 323 control |= AMDMD37X_DISPC_CONTROL_STNTFT_FLAG; 344 WRITE_DUMP(default_color[0], 0xff); 345 WRITE_DUMP(default_color[1], 0xff); 346 347 /* Setup control register */ 348 uint32_t control = 0 | 349 AMDM37X_DISPC_CONTROL_PCKFREEENABLE_FLAG | 350 (control_data_lanes << AMDM37X_DISPC_CONTROL_TFTDATALINES_SHIFT) | 351 AMDM37X_DISPC_CONTROL_GPOUT0_FLAG | 352 AMDM37X_DISPC_CONTROL_GPOUT1_FLAG; 324 353 regs->control = control; 354 WRITE_DUMP(control, control); 325 355 326 356 /* No gamma stuff only data */ 327 uint32_t config = regs->config; 328 config &= ~(AMDMD37X_DISPC_CONFIG_LOADMODE_MASK 329 << AMDMD37X_DISPC_CONFIG_LOADMODE_SHIFT); 330 config |= AMDMD37X_DISPC_CONFIG_LOADMODE_DATAEVERYFRAME 331 << AMDMD37X_DISPC_CONFIG_LOADMODE_SHIFT; 357 uint32_t config = (AMDM37X_DISPC_CONFIG_LOADMODE_DATAEVERYFRAME 358 << AMDM37X_DISPC_CONFIG_LOADMODE_SHIFT); 332 359 regs->config = config; 360 WRITE_DUMP(config, config); 333 361 334 362 … … 337 365 regs->gfx.ba[1] = pa; 338 366 regs->gfx.position = 0; 367 WRITE_DUMP(gfx.ba[0], pa); 368 WRITE_DUMP(gfx.ba[1], pa); 369 WRITE_DUMP(gfx.position, 0); 339 370 340 371 /* Setup fb size */ 341 372 regs->gfx.size = size_reg; 342 343 /* Pixel format */ 344 unsigned format = 0; 345 switch (bpp) 346 { 347 case 32: format = AMDMD37X_DISPC_GFX_ATTRIBUTES_FORMAT_RGBX; break; 348 case 24: format = AMDMD37X_DISPC_GFX_ATTRIBUTES_FORMAT_RGB24; break; 349 case 16: format = AMDMD37X_DISPC_GFX_ATTRIBUTES_FORMAT_RGB16; break; 350 default: 351 ASSERT(false); 352 } 353 354 /* Start gfx engine */ 355 uint32_t attribs = regs->gfx.attributes; 356 attribs &= ~(AMDMD37X_DISPC_GFX_ATTRIBUTES_FORMAT_MASK 357 << AMDMD37X_DISPC_GFX_ATTRIBUTES_FORMAT_SHIFT); 358 attribs |= format << AMDMD37X_DISPC_GFX_ATTRIBUTES_FORMAT_SHIFT; 359 attribs |= AMDMD37X_DISPC_GFX_ATTRIBUTES_ENABLE_FLAG; 373 WRITE_DUMP(gfx.size, size_reg); 374 375 376 /* Set pixel format */ 377 uint32_t attribs = 0 | 378 (attrib_pixel_format << AMDM37X_DISPC_GFX_ATTRIBUTES_FORMAT_SHIFT); 360 379 regs->gfx.attributes = attribs; 361 380 WRITE_DUMP(gfx.attributes, attribs); 381 382 /* 0x03ff03c0 is the default */ 383 regs->gfx.fifo_threshold = 0x03ff03c0; 384 /* This value should be stride - width, 1 means next pixel i.e. 385 * stride == width */ 386 regs->gfx.row_inc = 1; 387 /* number of bytes to next pixel in BPP multiples */ 388 regs->gfx.pixel_inc = 1; 389 /* only used if video is played over fb */ 390 regs->gfx.window_skip = 0; 391 /* Gamma and palette table */ 392 regs->gfx.table_ba = 0; 393 WRITE_DUMP(gfx.fifo_threshold, 0x03ff03c0); 394 WRITE_DUMP(gfx.row_inc, 1); 395 WRITE_DUMP(gfx.pixel_inc, 1); 396 WRITE_DUMP(gfx.window_skip, 0); 397 WRITE_DUMP(gfx.table_ba, 0); 398 399 /* enable frame buffer graphics */ 400 regs->gfx.attributes |= AMDM37X_DISPC_GFX_ATTRIBUTES_ENABLE_FLAG; 401 /* Update register values */ 402 regs->control |= AMDM37X_DISPC_CONTROL_GOLCD_FLAG; 403 regs->control |= AMDM37X_DISPC_CONTROL_GODIGITAL_FLAG; 362 404 /* Enable output */ 363 regs->control |= AMDMD37X_DISPC_CONTROL_LCD_ENABLE_FLAG; 364 // regs->control |= AMDMD37X_DISPC_CONTROL_DIGITAL_ENABLE_FLAG; 365 regs->control |= AMDMD37X_DISPC_CONTROL_GOLCD_FLAG; 366 // regs->control |= AMDMD37X_DISPC_CONTROL_GODIGITAL_FLAG; 405 regs->control |= AMDM37X_DISPC_CONTROL_LCD_ENABLE_FLAG; 406 regs->control |= AMDM37X_DISPC_CONTROL_DIGITAL_ENABLE_FLAG; 367 407 } 368 408
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