Index: arch/amd64/src/userspace.c
===================================================================
--- arch/amd64/src/userspace.c	(revision 53f98219259f3ae305745185632cbe185fb7c871)
+++ arch/amd64/src/userspace.c	(revision 45fb65c09103dff87bfb6916993a019f9309b363)
@@ -46,4 +46,7 @@
 	ipl = interrupts_disable();
 
+	/* Clear CF,PF,AF,ZF,SF,DF,OF */
+	ipl &= ~ (0xbc4);
+
 	__asm__ volatile (""
 			  "pushq %0\n"
Index: arch/mips32/include/context_offset.h
===================================================================
--- arch/mips32/include/context_offset.h	(revision 53f98219259f3ae305745185632cbe185fb7c871)
+++ arch/mips32/include/context_offset.h	(revision 45fb65c09103dff87bfb6916993a019f9309b363)
@@ -49,3 +49,4 @@
 #define EOFFSET_STATUS 0x7c
 #define EOFFSET_EPC    0x80
+#define EOFFSET_K1     0x84
 #define REGISTER_SPACE 136
Index: arch/mips32/include/exception.h
===================================================================
--- arch/mips32/include/exception.h	(revision 53f98219259f3ae305745185632cbe185fb7c871)
+++ arch/mips32/include/exception.h	(revision 45fb65c09103dff87bfb6916993a019f9309b363)
@@ -91,5 +91,5 @@
 	__u32 status; /* cp0_status */
 	__u32 epc; /* cp0_epc */
-	__u32 padding; /* padding to align stack on 8 bytes boundary */
+	__u32 k1; /* We use it as thread-local pointer */
 };
 
Index: arch/mips32/src/start.S
===================================================================
--- arch/mips32/src/start.S	(revision 53f98219259f3ae305745185632cbe185fb7c871)
+++ arch/mips32/src/start.S	(revision 45fb65c09103dff87bfb6916993a019f9309b363)
@@ -50,4 +50,5 @@
 # We will change status: Disable ERL,EXL,UM,IE
 # These changes will be automatically reversed in REGISTER_LOAD
+# SP is NOT saved as part of these registers
 .macro REGISTERS_STORE_AND_EXC_RESET r
 	sw $at,EOFFSET_AT(\r)
@@ -88,5 +89,5 @@
 	sw $gp,EOFFSET_GP(\r)
 	sw $ra,EOFFSET_RA(\r)
-	sw $sp,EOFFSET_SP(\r)
+	sw $k1,EOFFSET_K1(\r)
 
 	mfc0 $t0, $status
@@ -144,4 +145,5 @@
 	lw $gp,EOFFSET_GP(\r)
 	lw $ra,EOFFSET_RA(\r)
+	lw $k1,EOFFSET_K1(\r)
 	
 	lw $at,EOFFSET_LO(\r)
@@ -208,21 +210,22 @@
 exception_handler:
 	KERNEL_STACK_TO_K0
-	
-	mfc0 $k1, $cause
 	sub $k0, REGISTER_SPACE
-	
-	sra $k1, $k1, 0x2     # cp0_exc_cause() part 1
-	andi $k1, $k1, 0x1f   # cp0_exc_cause() part 2
-	sub $k1, 8            # 8=SYSCALL
-	
-	beqz $k1, syscall_shortcut
-	add $k1, 8            # Revert $k1 back to correct exc number
-	
-	REGISTERS_STORE_AND_EXC_RESET $k0
+	sw $sp,EOFFSET_SP($k0)
 	move $sp, $k0
+	
+	mfc0 $k0, $cause
+	
+	sra $k0, $k0, 0x2     # cp0_exc_cause() part 1
+	andi $k0, $k0, 0x1f   # cp0_exc_cause() part 2
+	sub $k0, 8            # 8=SYSCALL
+	
+	beqz $k0, syscall_shortcut
+	add $k0, 8            # Revert $k1 back to correct exc number
+	
+	REGISTERS_STORE_AND_EXC_RESET $sp
 	
 	move $a1, $sp
 	jal exc_dispatch      # exc_dispatch(excno, register_space)
-	move $a0, $k1
+	move $a0, $k0
 
 	REGISTERS_LOAD $sp
@@ -232,12 +235,9 @@
 # it seems that mips reserves some space on stack for varfuncs???
 #define SS_ARG4   16
-#define SS_SP     20
-#define SS_STATUS 24
-#define SS_EPC    28
+#define SS_SP     EOFFSET_SP
+#define SS_STATUS EOFFSET_STATUS
+#define SS_EPC    EOFFSET_EPC
 syscall_shortcut:
 	# We have a lot of space on the stack, with free use
-	sw $sp, SS_SP($k0)
-	move $sp, $k0
-
 	mfc0 $t1, $epc
 	mfc0 $t0, $status
@@ -277,4 +277,5 @@
 	sub $k0, REGISTER_SPACE
 	REGISTERS_STORE_AND_EXC_RESET $k0
+	sw $sp,EOFFSET_SP($k0)
 	add $sp, $k0, 0
 
@@ -289,6 +290,7 @@
 cache_error_handler:
 	KERNEL_STACK_TO_K0
-	sub $sp, REGISTER_SPACE
-	REGISTERS_STORE_AND_EXC_RESET $sp
+	sub $k0, REGISTER_SPACE
+	REGISTERS_STORE_AND_EXC_RESET $k0
+	sw $sp,EOFFSET_SP($k0)
 	add $sp, $k0, 0