Changeset 43114c5 in mainline for arch/mips/src

Timestamp:

2005-04-09T18:22:53Z (21 years ago)

Author:

Jakub Jermar <jakub@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

8262010

Parents:

e6ba9a3f

Message:

Introduce macros CPU, THREAD, TASK and use them to replace the→cpu, the→thread, the→task.
Later on, this will make it possible to reference *current* cpu, thread and/or task without the aid from virtual memory.

Location:

arch/mips/src

Files:

• cpu/cpu.c (modified) (1 diff)
• exception.c (modified) (2 diffs)
• mm/tlb.c (modified) (1 diff)

arch/mips/src/cpu/cpu.c

@@ -84 +84 @@
 void cpu_identify(void)
 {
-        the->cpu->arch.rev_num = cp0_prid_read() & 0xff;
-        the->cpu->arch.imp_num = (cp0_prid_read() >> 8) & 0xff;
+        CPU->arch.rev_num = cp0_prid_read() & 0xff;
+        CPU->arch.imp_num = (cp0_prid_read() >> 8) & 0xff;
 }
 

arch/mips/src/exception.c

@@ -43 +43 @@
         cp0_status_write(cp0_status_read() & ~ cp0_status_exl_exception_bit);
 
-        if (the->thread) {
-                the->thread->saved_pri = pri;
-                the->thread->saved_epc = epc;
+        if (THREAD) {
+                THREAD->saved_pri = pri;
+                THREAD->saved_epc = epc;
         }
         /* decode exception number and process the exception */
@@ -55 +55 @@
         }
         
-        if (the->thread) {
-                pri = the->thread->saved_pri;
-                epc = the->thread->saved_epc;
+        if (THREAD) {
+                pri = THREAD->saved_pri;
+                epc = THREAD->saved_epc;
         }
 

arch/mips/src/mm/tlb.c

@@ -47 +47 @@
 void tlb_invalid(void)
 {
-        panic(PANIC "%X: TLB exception at %X", cp0_badvaddr_read(), the->thread ? the->thread->saved_epc : 0);
+        panic(PANIC "%X: TLB exception at %X", cp0_badvaddr_read(), THREAD ? THREAD->saved_epc : 0);
 }