Index: kernel/genarch/Makefile.inc =================================================================== --- kernel/genarch/Makefile.inc (revision 954b645851eb59a764e118125b35f0a7f9325379) +++ kernel/genarch/Makefile.inc (revision 42f2a45636d7eec8eb42f45695923e1b57363e06) @@ -111,4 +111,9 @@ endif +ifeq ($(CONFIG_AM335X_TIMERS),y) + GENARCH_SOURCES += \ + genarch/src/drivers/am335x/timer.c +endif + ifeq ($(CONFIG_AMDM37X_UART),y) GENARCH_SOURCES += \ Index: kernel/genarch/include/drivers/am335x/timer.h =================================================================== --- kernel/genarch/include/drivers/am335x/timer.h (revision 42f2a45636d7eec8eb42f45695923e1b57363e06) +++ kernel/genarch/include/drivers/am335x/timer.h (revision 42f2a45636d7eec8eb42f45695923e1b57363e06) @@ -0,0 +1,100 @@ +/* + * Copyright (c) 2012 Maurizio Lombardi + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** @addtogroup genarch + * @{ + */ +/** + * @file + * @brief Texas Instruments AM335x timer driver. + */ + +#ifndef _AM335X_TIMER_H_ +#define _AM335X_TIMER_H_ + +#include "timer_regs.h" + +#define AM335x_DMTIMER0_BASE_ADDRESS 0x44E05000 +#define AM335x_DMTIMER0_SIZE 4096 +#define AM335x_DMTIMER0_IRQ 66 + +#define AM335x_DMTIMER2_BASE_ADDRESS 0x48040000 +#define AM335x_DMTIMER2_SIZE 4096 +#define AM335x_DMTIMER2_IRQ 68 + +#define AM335x_DMTIMER3_BASE_ADDRESS 0x48042000 +#define AM335x_DMTIMER3_SIZE 4096 +#define AM335x_DMTIMER3_IRQ 69 + +#define AM335x_DMTIMER4_BASE_ADDRESS 0x48044000 +#define AM335x_DMTIMER4_SIZE 4096 +#define AM335x_DMTIMER4_IRQ 92 + +#define AM335x_DMTIMER5_BASE_ADDRESS 0x48046000 +#define AM335x_DMTIMER5_SIZE 4096 +#define AM335x_DMTIMER5_IRQ 93 + +#define AM335x_DMTIMER6_BASE_ADDRESS 0x48048000 +#define AM335x_DMTIMER6_SIZE 4096 +#define AM335x_DMTIMER6_IRQ 94 + +#define AM335x_DMTIMER7_BASE_ADDRESS 0x4804A000 +#define AM335x_DMTIMER7_SIZE 4096 +#define AM335x_DMTIMER7_IRQ 95 + +typedef enum { + DMTIMER0 = 0, + DMTIMER1_1MS, + DMTIMER2, + DMTIMER3, + DMTIMER4, + DMTIMER5, + DMTIMER6, + DMTIMER7, + + TIMERS_MAX +} am335x_timer_id_t; + +typedef struct am335x_timer { + am335x_timer_regs_t *regs; + am335x_timer_id_t id; +} am335x_timer_t; + +extern void am335x_timer_init(am335x_timer_t *timer, am335x_timer_id_t id, + unsigned hz); +extern void am335x_timer_intr_ack(am335x_timer_t *timer); +extern void am335x_timer_reset(am335x_timer_t *timer); +extern void am335x_timer_start(am335x_timer_t *timer); +extern void am335x_timer_stop(am335x_timer_t *timer); + + +#endif + +/** + * @} + */ + Index: kernel/genarch/include/drivers/am335x/timer_regs.h =================================================================== --- kernel/genarch/include/drivers/am335x/timer_regs.h (revision 42f2a45636d7eec8eb42f45695923e1b57363e06) +++ kernel/genarch/include/drivers/am335x/timer_regs.h (revision 42f2a45636d7eec8eb42f45695923e1b57363e06) @@ -0,0 +1,154 @@ +/* + * Copyright (c) 2012 Maurizio Lombardi + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** @addtogroup genarch + * @{ + */ +/** + * @file + * @brief Texas Instruments AM335x DMTIMER memory mapped registers. + */ + +#include + +typedef struct am335x_timer_regs { + + /* This read only register contains the + * revision number of the module + */ + ioport32_t const tidr; +#define AM335x_TIMER_TIDR_MINOR_MASK 0x3F +#define AM335x_TIMER_TIDR_MINOR_SHIFT 0 +#define AM335x_TIMER_TIDR_CUSTOM_MASK 0x03 +#define AM335x_TIMER_TIDR_CUSTOM_SHIFT 6 +#define AM335x_TIMER_TIDR_MAJOR_MASK 0x07 +#define AM335x_TIMER_TIDR_MAJOR_SHIFT 8 +#define AM335x_TIMER_TIDR_RTL_MASK 0x1F +#define AM335x_TIMER_TIDR_RTL_SHIFT 11 +#define AM335x_TIMER_TIDR_FUNC_MASK 0xFFF +#define AM335x_TIMER_TIDR_FUNC_SHIFT 16 +#define AM335x_TIMER_TIDR_SCHEME_MASK 0x03 +#define AM335x_TIMER_TIDR_SCHEME_SHIFT 30 + + ioport32_t const pad1[3]; + + /* This register allows controlling various + * parameters of the OCP interface. + */ + ioport32_t tiocp_cfg; +#define AM335x_TIMER_TIOCPCFG_SOFTRESET_FLAG (1 << 0) +#define AM335x_TIMER_TIOCPCFG_EMUFREE_FLAG (1 << 1) + +#define AM335x_TIMER_TIOCPCFG_IDLEMODE_MASK 0x02 +#define AM335x_TIMER_TIOCPCFG_IDLEMODE_SHIFT 2 +# define AM335x_TIMER_TIOCCPCFG_IDLEMODE_FORCE 0x00 +# define AM335x_TIMER_TIOCCPCFG_IDLEMODE_DISABLED 0x01 +# define AM335x_TIMER_TIOCCPCFG_IDLEMODE_SMART 0x02 +# define AM335x_TIMER_TIOCCPCFG_IDLEMODE_SMART_WAKEUP 0x03 + + ioport32_t const pad2[4]; + + ioport32_t irqstatus_raw; +#define AM335x_TIMER_IRQSTATUS_RAW_MAT_FLAG (1 << 0) +#define AM335x_TIMER_IRQSTATUS_RAW_OVF_FLAG (1 << 1) +#define AM335x_TIMER_IRQSTATUS_RAW_TCAR_FLAG (1 << 2) + + ioport32_t irqstatus; +#define AM335x_TIMER_IRQSTATUS_MAT_FLAG (1 << 0) +#define AM335x_TIMER_IRQSTATUS_OVF_FLAG (1 << 1) +#define AM335x_TIMER_IRQSTATUS_TCAR_FLAG (1 << 2) + + ioport32_t irqenable_set; +#define AM335x_TIMER_IRQENABLE_SET_MAT_FLAG (1 << 0) +#define AM335x_TIMER_IRQENABLE_SET_OVF_FLAG (1 << 1) +#define AM335x_TIMER_IRQENABLE_SET_TCAR_FLAG (1 << 2) + + ioport32_t irqenable_clr; +#define AM335x_TIMER_IRQENABLE_CLR_MAT_FLAG (1 << 0) +#define AM335x_TIMER_IRQENABLE_CLR_OVF_FLAG (1 << 1) +#define AM335x_TIMER_IRQENABLE_CLR_TCAR_FLAG (1 << 2) + + /* Timer IRQ wakeup enable register */ + ioport32_t irqwakeen; +#define AM335x_TIMER_IRQWAKEEN_MAT_FLAG (1 << 0) +#define AM335x_TIMER_IRQWAKEEN_PVF_FLAG (1 << 1) +#define AM335x_TIMER_IRQWAKEEN_TCAR_FLAG (1 << 2) + + /* Timer control register */ + ioport32_t tclr; +#define AM335x_TIMER_TCLR_ST_FLAG (1 << 0) +#define AM335x_TIMER_TCLR_AR_FLAG (1 << 1) +#define AM335x_TIMER_TCLR_PTV_MASK 0x07 +#define AM335x_TIMER_TCLR_PTV_SHIFT 2 +#define AM335x_TIMER_TCLR_PRE_FLAG (1 << 5) +#define AM335x_TIMER_TCLR_CE_FLAG (1 << 6) +#define AM335x_TIMER_TCLR_SCPWM_FLAG (1 << 7) +#define AM335x_TIMER_TCLR_TCM_MASK 0x03 +#define AM335x_TIMER_TCLR_TCM_SHIFT 8 +#define AM335x_TIMER_TCLR_TGR_MASK 0x03 +#define AM335x_TIMER_TCLR_TGR_SHIFT 10 +#define AM335x_TIMER_TCLR_PT_FLAG (1 << 12) +#define AM335x_TIMER_TCLR_CAPT_MODE_FLAG (1 << 13) +#define AM335x_TIMER_TCLR_GPO_CFG_FLAG (1 << 14) + + /* Timer counter register */ + ioport32_t tcrr; + + /* Timer load register */ + ioport32_t tldr; + + /* Timer trigger register */ + ioport32_t const ttgr; + + /* Timer write posted status register */ + ioport32_t twps; +#define AM335x_TIMER_TWPS_PEND_TCLR (1 << 0) +#define AM335x_TIMER_TWPS_PEND_TCRR (1 << 1) +#define AM335x_TIMER_TWPS_PEND_TLDR (1 << 2) +#define AM335x_TIMER_TWPS_PEND_TTGR (1 << 3) +#define AM335x_TIMER_TWPS_PEND_TMAR (1 << 4) + + /* Timer match register */ + ioport32_t tmar; + + /* Timer capture register */ + ioport32_t tcar1; + + /* Timer synchronous interface control register */ + ioport32_t tsicr; +#define AM335x_TIMER_TSICR_SFT_FLAG (1 << 1) +#define AM335x_TIMER_TSICR_POSTED_FLAG (1 << 2) + + /* Timer capture register */ + ioport32_t tcar2; + +} am335x_timer_regs_t; + +/** + * @} + */ + Index: kernel/genarch/src/drivers/am335x/timer.c =================================================================== --- kernel/genarch/src/drivers/am335x/timer.c (revision 42f2a45636d7eec8eb42f45695923e1b57363e06) +++ kernel/genarch/src/drivers/am335x/timer.c (revision 42f2a45636d7eec8eb42f45695923e1b57363e06) @@ -0,0 +1,135 @@ +/* + * Copyright (c) 2012 Maurizio Lombardi + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** @addtogroup genarch + * @{ + */ +/** + * @file + * @brief Texas Instruments AM335x timer driver. + */ + +#include +#include +#include + + +typedef struct timer_regs_mmap { + uintptr_t base; + size_t size; +} timer_regs_mmap_t; + +static const timer_regs_mmap_t regs_map[TIMERS_MAX] = { + { .base = AM335x_DMTIMER0_BASE_ADDRESS, .size = AM335x_DMTIMER0_SIZE }, + {0, 0}, + { .base = AM335x_DMTIMER2_BASE_ADDRESS, .size = AM335x_DMTIMER2_SIZE }, + { .base = AM335x_DMTIMER3_BASE_ADDRESS, .size = AM335x_DMTIMER3_SIZE }, + { .base = AM335x_DMTIMER4_BASE_ADDRESS, .size = AM335x_DMTIMER4_SIZE }, + { .base = AM335x_DMTIMER5_BASE_ADDRESS, .size = AM335x_DMTIMER5_SIZE }, + { .base = AM335x_DMTIMER6_BASE_ADDRESS, .size = AM335x_DMTIMER6_SIZE }, + { .base = AM335x_DMTIMER7_BASE_ADDRESS, .size = AM335x_DMTIMER7_SIZE }, +}; + +void +am335x_timer_init(am335x_timer_t *timer, am335x_timer_id_t id, unsigned hz) +{ + uintptr_t base_addr; + size_t size; + + ASSERT(id < TIMERS_MAX); + + if (id == DMTIMER1_1MS) + return; /* Not supported yet */ + + base_addr = regs_map[id].base; + size = regs_map[id].size; + + timer->regs = (void *) km_map(base_addr, size, PAGE_NOT_CACHEABLE); + timer->id = id; + + am335x_timer_regs_t *regs = timer->regs; + + /* Stop the timer */ + am335x_timer_stop(timer); + + /* Perform a soft reset */ + am335x_timer_reset(timer); + + /* Disable the prescaler */ + regs->tclr &= ~AM335x_TIMER_TCLR_PRE_FLAG; + + /* Enable auto-reload mode */ + regs->tclr |= AM335x_TIMER_TCLR_AR_FLAG; + + /* XXX Here we assume that the timer clock source + * is running at 32 Khz but this is not always the + * case; DMTIMER[2 - 7] can use the internal system 24 Mhz + * clock source or an external clock also. + */ + unsigned const count = 0xFFFFFFFE - 32768 / hz; + regs->tcrr = count; + regs->tldr = count; +} + +void +am335x_timer_intr_ack(am335x_timer_t *timer) +{ + /* Clear pending OVF event */ + timer->regs->irqstatus |= AM335x_TIMER_IRQSTATUS_OVF_FLAG; +} + +void +am335x_timer_reset(am335x_timer_t *timer) +{ + /* Initiate soft reset */ + timer->regs->tiocp_cfg |= AM335x_TIMER_TIOCPCFG_SOFTRESET_FLAG; + /* Wait until the reset is done */ + while (timer->regs->tiocp_cfg & AM335x_TIMER_TIOCPCFG_SOFTRESET_FLAG); +} + +void +am335x_timer_stop(am335x_timer_t *timer) +{ + /* Disable the interrupt */ + timer->regs->irqenable_clr |= AM335x_TIMER_IRQENABLE_CLR_OVF_FLAG; + /* Stop the timer */ + timer->regs->tclr &= ~AM335x_TIMER_TCLR_ST_FLAG; +} + +void +am335x_timer_start(am335x_timer_t *timer) +{ + /* Enable the interrupt */ + timer->regs->irqenable_set |= AM335x_TIMER_IRQENABLE_SET_OVF_FLAG; + /* Start the clock */ + timer->regs->tclr |= AM335x_TIMER_TCLR_ST_FLAG; +} + +/** + * @} + */ +