Index: kernel/arch/abs32le/include/arch/asm.h
===================================================================
--- kernel/arch/abs32le/include/arch/asm.h	(revision c477c804d1208352d69c7b069a54d3e3b650ff96)
+++ kernel/arch/abs32le/include/arch/asm.h	(revision 401415aa8fcb6902c643bf1c028f08be8f7c2d8e)
@@ -40,9 +40,9 @@
 #include <trace.h>
 
-NO_TRACE static inline void asm_delay_loop(uint32_t usec)
-{
-}
-
-NO_TRACE static inline __attribute__((noreturn)) void cpu_halt(void)
+_NO_TRACE static inline void asm_delay_loop(uint32_t usec)
+{
+}
+
+_NO_TRACE static inline __attribute__((noreturn)) void cpu_halt(void)
 {
 	/*
@@ -57,5 +57,5 @@
 }
 
-NO_TRACE static inline void cpu_sleep(void)
+_NO_TRACE static inline void cpu_sleep(void)
 {
 	/*
@@ -67,5 +67,5 @@
 }
 
-NO_TRACE static inline void pio_write_8(ioport8_t *port, uint8_t val)
+_NO_TRACE static inline void pio_write_8(ioport8_t *port, uint8_t val)
 {
 }
@@ -79,5 +79,5 @@
  *
  */
-NO_TRACE static inline void pio_write_16(ioport16_t *port, uint16_t val)
+_NO_TRACE static inline void pio_write_16(ioport16_t *port, uint16_t val)
 {
 }
@@ -91,5 +91,5 @@
  *
  */
-NO_TRACE static inline void pio_write_32(ioport32_t *port, uint32_t val)
+_NO_TRACE static inline void pio_write_32(ioport32_t *port, uint32_t val)
 {
 }
@@ -103,5 +103,5 @@
  *
  */
-NO_TRACE static inline uint8_t pio_read_8(ioport8_t *port)
+_NO_TRACE static inline uint8_t pio_read_8(ioport8_t *port)
 {
 	return 0;
@@ -116,5 +116,5 @@
  *
  */
-NO_TRACE static inline uint16_t pio_read_16(ioport16_t *port)
+_NO_TRACE static inline uint16_t pio_read_16(ioport16_t *port)
 {
 	return 0;
@@ -129,10 +129,10 @@
  *
  */
-NO_TRACE static inline uint32_t pio_read_32(ioport32_t *port)
-{
-	return 0;
-}
-
-NO_TRACE static inline ipl_t interrupts_enable(void)
+_NO_TRACE static inline uint32_t pio_read_32(ioport32_t *port)
+{
+	return 0;
+}
+
+_NO_TRACE static inline ipl_t interrupts_enable(void)
 {
 	/*
@@ -146,5 +146,5 @@
 }
 
-NO_TRACE static inline ipl_t interrupts_disable(void)
+_NO_TRACE static inline ipl_t interrupts_disable(void)
 {
 	/*
@@ -160,5 +160,5 @@
 }
 
-NO_TRACE static inline void interrupts_restore(ipl_t ipl)
+_NO_TRACE static inline void interrupts_restore(ipl_t ipl)
 {
 	/*
@@ -168,5 +168,5 @@
 }
 
-NO_TRACE static inline ipl_t interrupts_read(void)
+_NO_TRACE static inline ipl_t interrupts_read(void)
 {
 	/*
@@ -178,5 +178,5 @@
 }
 
-NO_TRACE static inline bool interrupts_disabled(void)
+_NO_TRACE static inline bool interrupts_disabled(void)
 {
 	/*
@@ -188,5 +188,5 @@
 }
 
-NO_TRACE static inline uintptr_t get_stack_base(void)
+_NO_TRACE static inline uintptr_t get_stack_base(void)
 {
 	/*
Index: kernel/arch/abs32le/include/arch/cycle.h
===================================================================
--- kernel/arch/abs32le/include/arch/cycle.h	(revision c477c804d1208352d69c7b069a54d3e3b650ff96)
+++ kernel/arch/abs32le/include/arch/cycle.h	(revision 401415aa8fcb6902c643bf1c028f08be8f7c2d8e)
@@ -38,5 +38,5 @@
 #include <trace.h>
 
-NO_TRACE static inline uint64_t get_cycle(void)
+_NO_TRACE static inline uint64_t get_cycle(void)
 {
 	return 0;
Index: kernel/arch/abs32le/include/arch/istate.h
===================================================================
--- kernel/arch/abs32le/include/arch/istate.h	(revision c477c804d1208352d69c7b069a54d3e3b650ff96)
+++ kernel/arch/abs32le/include/arch/istate.h	(revision 401415aa8fcb6902c643bf1c028f08be8f7c2d8e)
@@ -62,5 +62,5 @@
 } istate_t;
 
-NO_TRACE static inline int istate_from_uspace(istate_t *istate)
+_NO_TRACE static inline int istate_from_uspace(istate_t *istate)
     REQUIRES_EXTENT_MUTABLE(istate)
 {
@@ -73,5 +73,5 @@
 }
 
-NO_TRACE static inline void istate_set_retaddr(istate_t *istate,
+_NO_TRACE static inline void istate_set_retaddr(istate_t *istate,
     uintptr_t retaddr)
     WRITES(&istate->ip)
@@ -82,5 +82,5 @@
 }
 
-NO_TRACE static inline uintptr_t istate_get_pc(istate_t *istate)
+_NO_TRACE static inline uintptr_t istate_get_pc(istate_t *istate)
     REQUIRES_EXTENT_MUTABLE(istate)
 {
@@ -90,5 +90,5 @@
 }
 
-NO_TRACE static inline uintptr_t istate_get_fp(istate_t *istate)
+_NO_TRACE static inline uintptr_t istate_get_fp(istate_t *istate)
     REQUIRES_EXTENT_MUTABLE(istate)
 {
Index: kernel/arch/abs32le/include/arch/mm/page.h
===================================================================
--- kernel/arch/abs32le/include/arch/mm/page.h	(revision c477c804d1208352d69c7b069a54d3e3b650ff96)
+++ kernel/arch/abs32le/include/arch/mm/page.h	(revision 401415aa8fcb6902c643bf1c028f08be8f7c2d8e)
@@ -147,5 +147,5 @@
 } __attribute__((packed)) pte_t;
 
-NO_TRACE static inline unsigned int get_pt_flags(pte_t *pt, size_t i)
+_NO_TRACE static inline unsigned int get_pt_flags(pte_t *pt, size_t i)
     REQUIRES_ARRAY_MUTABLE(pt, PTL0_ENTRIES_ARCH)
 {
@@ -161,5 +161,5 @@
 }
 
-NO_TRACE static inline void set_pt_flags(pte_t *pt, size_t i, int flags)
+_NO_TRACE static inline void set_pt_flags(pte_t *pt, size_t i, int flags)
     WRITES(ARRAY_RANGE(pt, PTL0_ENTRIES_ARCH))
     REQUIRES_ARRAY_MUTABLE(pt, PTL0_ENTRIES_ARCH)
@@ -180,5 +180,5 @@
 }
 
-NO_TRACE static inline void set_pt_present(pte_t *pt, size_t i)
+_NO_TRACE static inline void set_pt_present(pte_t *pt, size_t i)
     WRITES(ARRAY_RANGE(pt, PTL0_ENTRIES_ARCH))
     REQUIRES_ARRAY_MUTABLE(pt, PTL0_ENTRIES_ARCH)
Index: kernel/arch/amd64/include/arch/asm.h
===================================================================
--- kernel/arch/amd64/include/arch/asm.h	(revision c477c804d1208352d69c7b069a54d3e3b650ff96)
+++ kernel/arch/amd64/include/arch/asm.h	(revision 401415aa8fcb6902c643bf1c028f08be8f7c2d8e)
@@ -50,5 +50,5 @@
  *
  */
-NO_TRACE static inline uintptr_t get_stack_base(void)
+_NO_TRACE static inline uintptr_t get_stack_base(void)
 {
 	uintptr_t v;
@@ -63,5 +63,5 @@
 }
 
-NO_TRACE static inline void cpu_sleep(void)
+_NO_TRACE static inline void cpu_sleep(void)
 {
 	asm volatile (
@@ -70,5 +70,5 @@
 }
 
-NO_TRACE static inline void __attribute__((noreturn)) cpu_halt(void)
+_NO_TRACE static inline void __attribute__((noreturn)) cpu_halt(void)
 {
 	while (true) {
@@ -87,5 +87,5 @@
  *
  */
-NO_TRACE static inline uint8_t pio_read_8(ioport8_t *port)
+_NO_TRACE static inline uint8_t pio_read_8(ioport8_t *port)
 {
 	if (port < (ioport8_t *) IO_SPACE_BOUNDARY) {
@@ -111,5 +111,5 @@
  *
  */
-NO_TRACE static inline uint16_t pio_read_16(ioport16_t *port)
+_NO_TRACE static inline uint16_t pio_read_16(ioport16_t *port)
 {
 	if (port < (ioport16_t *) IO_SPACE_BOUNDARY) {
@@ -135,5 +135,5 @@
  *
  */
-NO_TRACE static inline uint32_t pio_read_32(ioport32_t *port)
+_NO_TRACE static inline uint32_t pio_read_32(ioport32_t *port)
 {
 	if (port < (ioport32_t *) IO_SPACE_BOUNDARY) {
@@ -159,5 +159,5 @@
  *
  */
-NO_TRACE static inline void pio_write_8(ioport8_t *port, uint8_t val)
+_NO_TRACE static inline void pio_write_8(ioport8_t *port, uint8_t val)
 {
 	if (port < (ioport8_t *) IO_SPACE_BOUNDARY) {
@@ -178,5 +178,5 @@
  *
  */
-NO_TRACE static inline void pio_write_16(ioport16_t *port, uint16_t val)
+_NO_TRACE static inline void pio_write_16(ioport16_t *port, uint16_t val)
 {
 	if (port < (ioport16_t *) IO_SPACE_BOUNDARY) {
@@ -197,5 +197,5 @@
  *
  */
-NO_TRACE static inline void pio_write_32(ioport32_t *port, uint32_t val)
+_NO_TRACE static inline void pio_write_32(ioport32_t *port, uint32_t val)
 {
 	if (port < (ioport32_t *) IO_SPACE_BOUNDARY) {
@@ -208,5 +208,5 @@
 }
 
-NO_TRACE static inline uint64_t read_rflags(void)
+_NO_TRACE static inline uint64_t read_rflags(void)
 {
 	uint64_t rflags;
@@ -221,5 +221,5 @@
 }
 
-NO_TRACE static inline void write_rflags(uint64_t rflags)
+_NO_TRACE static inline void write_rflags(uint64_t rflags)
 {
 	asm volatile (
@@ -237,5 +237,5 @@
  *
  */
-NO_TRACE static inline ipl_t interrupts_read(void)
+_NO_TRACE static inline ipl_t interrupts_read(void)
 {
 	return (ipl_t) read_rflags();
@@ -249,5 +249,5 @@
  *
  */
-NO_TRACE static inline ipl_t interrupts_enable(void)
+_NO_TRACE static inline ipl_t interrupts_enable(void)
 {
 	ipl_t ipl = interrupts_read();
@@ -265,5 +265,5 @@
  *
  */
-NO_TRACE static inline ipl_t interrupts_disable(void)
+_NO_TRACE static inline ipl_t interrupts_disable(void)
 {
 	ipl_t ipl = interrupts_read();
@@ -281,5 +281,5 @@
  *
  */
-NO_TRACE static inline void interrupts_restore(ipl_t ipl)
+_NO_TRACE static inline void interrupts_restore(ipl_t ipl)
 {
 	write_rflags((uint64_t) ipl);
@@ -291,5 +291,5 @@
  *
  */
-NO_TRACE static inline bool interrupts_disabled(void)
+_NO_TRACE static inline bool interrupts_disabled(void)
 {
 	return ((read_rflags() & RFLAGS_IF) == 0);
@@ -297,5 +297,5 @@
 
 /** Write to MSR */
-NO_TRACE static inline void write_msr(uint32_t msr, uint64_t value)
+_NO_TRACE static inline void write_msr(uint32_t msr, uint64_t value)
 {
 	asm volatile (
@@ -307,5 +307,5 @@
 }
 
-NO_TRACE static inline sysarg_t read_msr(uint32_t msr)
+_NO_TRACE static inline sysarg_t read_msr(uint32_t msr)
 {
 	uint32_t ax, dx;
@@ -325,5 +325,5 @@
  *
  */
-NO_TRACE static inline void invlpg(uintptr_t addr)
+_NO_TRACE static inline void invlpg(uintptr_t addr)
 {
 	asm volatile (
@@ -338,5 +338,5 @@
  *
  */
-NO_TRACE static inline void gdtr_load(ptr_16_64_t *gdtr_reg)
+_NO_TRACE static inline void gdtr_load(ptr_16_64_t *gdtr_reg)
 {
 	asm volatile (
@@ -351,5 +351,5 @@
  *
  */
-NO_TRACE static inline void gdtr_store(ptr_16_64_t *gdtr_reg)
+_NO_TRACE static inline void gdtr_store(ptr_16_64_t *gdtr_reg)
 {
 	asm volatile (
@@ -364,5 +364,5 @@
  *
  */
-NO_TRACE static inline void idtr_load(ptr_16_64_t *idtr_reg)
+_NO_TRACE static inline void idtr_load(ptr_16_64_t *idtr_reg)
 {
 	asm volatile (
@@ -376,5 +376,5 @@
  *
  */
-NO_TRACE static inline void tr_load(uint16_t sel)
+_NO_TRACE static inline void tr_load(uint16_t sel)
 {
 	asm volatile (
@@ -384,5 +384,5 @@
 }
 
-#define GEN_READ_REG(reg) NO_TRACE static inline sysarg_t read_ ##reg (void) \
+#define GEN_READ_REG(reg) _NO_TRACE static inline sysarg_t read_ ##reg (void) \
 	{ \
 		sysarg_t res; \
@@ -394,5 +394,5 @@
 	}
 
-#define GEN_WRITE_REG(reg) NO_TRACE static inline void write_ ##reg (sysarg_t regn) \
+#define GEN_WRITE_REG(reg) _NO_TRACE static inline void write_ ##reg (sysarg_t regn) \
 	{ \
 		asm volatile ( \
Index: kernel/arch/amd64/include/arch/cycle.h
===================================================================
--- kernel/arch/amd64/include/arch/cycle.h	(revision c477c804d1208352d69c7b069a54d3e3b650ff96)
+++ kernel/arch/amd64/include/arch/cycle.h	(revision 401415aa8fcb6902c643bf1c028f08be8f7c2d8e)
@@ -38,5 +38,5 @@
 #include <trace.h>
 
-NO_TRACE static inline uint64_t get_cycle(void)
+_NO_TRACE static inline uint64_t get_cycle(void)
 {
 	uint32_t lower;
Index: kernel/arch/amd64/include/arch/istate.h
===================================================================
--- kernel/arch/amd64/include/arch/istate.h	(revision c477c804d1208352d69c7b069a54d3e3b650ff96)
+++ kernel/arch/amd64/include/arch/istate.h	(revision 401415aa8fcb6902c643bf1c028f08be8f7c2d8e)
@@ -47,10 +47,10 @@
 
 /** Return true if exception happened while in userspace */
-NO_TRACE static inline int istate_from_uspace(istate_t *istate)
+_NO_TRACE static inline int istate_from_uspace(istate_t *istate)
 {
 	return (istate->cs & RPL_USER) == RPL_USER;
 }
 
-NO_TRACE static inline void istate_set_retaddr(istate_t *istate,
+_NO_TRACE static inline void istate_set_retaddr(istate_t *istate,
     uintptr_t retaddr)
 {
@@ -58,10 +58,10 @@
 }
 
-NO_TRACE static inline uintptr_t istate_get_pc(istate_t *istate)
+_NO_TRACE static inline uintptr_t istate_get_pc(istate_t *istate)
 {
 	return istate->rip;
 }
 
-NO_TRACE static inline uintptr_t istate_get_fp(istate_t *istate)
+_NO_TRACE static inline uintptr_t istate_get_fp(istate_t *istate)
 {
 	return istate->rbp;
Index: kernel/arch/amd64/include/arch/mm/page.h
===================================================================
--- kernel/arch/amd64/include/arch/mm/page.h	(revision c477c804d1208352d69c7b069a54d3e3b650ff96)
+++ kernel/arch/amd64/include/arch/mm/page.h	(revision 401415aa8fcb6902c643bf1c028f08be8f7c2d8e)
@@ -207,5 +207,5 @@
 } __attribute__((packed)) pte_t;
 
-NO_TRACE static inline unsigned int get_pt_flags(pte_t *pt, size_t i)
+_NO_TRACE static inline unsigned int get_pt_flags(pte_t *pt, size_t i)
 {
 	pte_t *p = &pt[i];
@@ -220,5 +220,5 @@
 }
 
-NO_TRACE static inline void set_pt_addr(pte_t *pt, size_t i, uintptr_t a)
+_NO_TRACE static inline void set_pt_addr(pte_t *pt, size_t i, uintptr_t a)
 {
 	pte_t *p = &pt[i];
@@ -228,5 +228,5 @@
 }
 
-NO_TRACE static inline void set_pt_flags(pte_t *pt, size_t i, int flags)
+_NO_TRACE static inline void set_pt_flags(pte_t *pt, size_t i, int flags)
 {
 	pte_t *p = &pt[i];
@@ -245,5 +245,5 @@
 }
 
-NO_TRACE static inline void set_pt_present(pte_t *pt, size_t i)
+_NO_TRACE static inline void set_pt_present(pte_t *pt, size_t i)
 {
 	pte_t *p = &pt[i];
Index: kernel/arch/arm32/include/arch/asm.h
===================================================================
--- kernel/arch/arm32/include/arch/asm.h	(revision c477c804d1208352d69c7b069a54d3e3b650ff96)
+++ kernel/arch/arm32/include/arch/asm.h	(revision 401415aa8fcb6902c643bf1c028f08be8f7c2d8e)
@@ -56,5 +56,5 @@
  * only for armv6+.
  */
-NO_TRACE static inline void cpu_sleep(void)
+_NO_TRACE static inline void cpu_sleep(void)
 {
 #ifdef PROCESSOR_ARCH_armv7_a
@@ -65,30 +65,30 @@
 }
 
-NO_TRACE static inline void pio_write_8(ioport8_t *port, uint8_t v)
+_NO_TRACE static inline void pio_write_8(ioport8_t *port, uint8_t v)
 {
 	*port = v;
 }
 
-NO_TRACE static inline void pio_write_16(ioport16_t *port, uint16_t v)
+_NO_TRACE static inline void pio_write_16(ioport16_t *port, uint16_t v)
 {
 	*port = v;
 }
 
-NO_TRACE static inline void pio_write_32(ioport32_t *port, uint32_t v)
+_NO_TRACE static inline void pio_write_32(ioport32_t *port, uint32_t v)
 {
 	*port = v;
 }
 
-NO_TRACE static inline uint8_t pio_read_8(ioport8_t *port)
+_NO_TRACE static inline uint8_t pio_read_8(ioport8_t *port)
 {
 	return *port;
 }
 
-NO_TRACE static inline uint16_t pio_read_16(ioport16_t *port)
+_NO_TRACE static inline uint16_t pio_read_16(ioport16_t *port)
 {
 	return *port;
 }
 
-NO_TRACE static inline uint32_t pio_read_32(ioport32_t *port)
+_NO_TRACE static inline uint32_t pio_read_32(ioport32_t *port)
 {
 	return *port;
@@ -102,5 +102,5 @@
  *
  */
-NO_TRACE static inline uintptr_t get_stack_base(void)
+_NO_TRACE static inline uintptr_t get_stack_base(void)
 {
 	uintptr_t v;
Index: kernel/arch/arm32/include/arch/cycle.h
===================================================================
--- kernel/arch/arm32/include/arch/cycle.h	(revision c477c804d1208352d69c7b069a54d3e3b650ff96)
+++ kernel/arch/arm32/include/arch/cycle.h	(revision 401415aa8fcb6902c643bf1c028f08be8f7c2d8e)
@@ -47,5 +47,5 @@
  *
  */
-NO_TRACE static inline uint64_t get_cycle(void)
+_NO_TRACE static inline uint64_t get_cycle(void)
 {
 #ifdef PROCESSOR_ARCH_armv7_a
Index: kernel/arch/arm32/include/arch/istate.h
===================================================================
--- kernel/arch/arm32/include/arch/istate.h	(revision c477c804d1208352d69c7b069a54d3e3b650ff96)
+++ kernel/arch/arm32/include/arch/istate.h	(revision 401415aa8fcb6902c643bf1c028f08be8f7c2d8e)
@@ -55,5 +55,5 @@
  *
  */
-NO_TRACE static inline void istate_set_retaddr(istate_t *istate,
+_NO_TRACE static inline void istate_set_retaddr(istate_t *istate,
     uintptr_t retaddr)
 {
@@ -62,5 +62,5 @@
 
 /** Return true if exception happened while in userspace. */
-NO_TRACE static inline int istate_from_uspace(istate_t *istate)
+_NO_TRACE static inline int istate_from_uspace(istate_t *istate)
 {
 	return (istate->spsr & STATUS_REG_MODE_MASK) == USER_MODE;
@@ -68,10 +68,10 @@
 
 /** Return Program Counter member of given istate structure. */
-NO_TRACE static inline uintptr_t istate_get_pc(istate_t *istate)
+_NO_TRACE static inline uintptr_t istate_get_pc(istate_t *istate)
 {
 	return istate->pc;
 }
 
-NO_TRACE static inline uintptr_t istate_get_fp(istate_t *istate)
+_NO_TRACE static inline uintptr_t istate_get_fp(istate_t *istate)
 {
 	return istate->fp;
Index: kernel/arch/arm32/include/arch/mm/page.h
===================================================================
--- kernel/arch/arm32/include/arch/mm/page.h	(revision c477c804d1208352d69c7b069a54d3e3b650ff96)
+++ kernel/arch/arm32/include/arch/mm/page.h	(revision 401415aa8fcb6902c643bf1c028f08be8f7c2d8e)
@@ -151,5 +151,5 @@
  * set_pt_level1_flags (kernel/arch/arm32/include/arch/mm/page_armv6.h)
  */
-NO_TRACE static inline void set_ptl0_addr(pte_t *pt)
+_NO_TRACE static inline void set_ptl0_addr(pte_t *pt)
 {
 	uint32_t val = (uint32_t)pt & TTBR_ADDR_MASK;
@@ -161,5 +161,5 @@
 }
 
-NO_TRACE static inline void set_ptl1_addr(pte_t *pt, size_t i, uintptr_t address)
+_NO_TRACE static inline void set_ptl1_addr(pte_t *pt, size_t i, uintptr_t address)
 {
 	pt[i].l0.coarse_table_addr = address >> 10;
@@ -167,5 +167,5 @@
 }
 
-NO_TRACE static inline void set_ptl3_addr(pte_t *pt, size_t i, uintptr_t address)
+_NO_TRACE static inline void set_ptl3_addr(pte_t *pt, size_t i, uintptr_t address)
 {
 	pt[i].l1.frame_base_addr = address >> 12;
Index: kernel/arch/arm32/include/arch/mm/page_armv4.h
===================================================================
--- kernel/arch/arm32/include/arch/mm/page_armv4.h	(revision c477c804d1208352d69c7b069a54d3e3b650ff96)
+++ kernel/arch/arm32/include/arch/mm/page_armv4.h	(revision 401415aa8fcb6902c643bf1c028f08be8f7c2d8e)
@@ -137,5 +137,5 @@
  *
  */
-NO_TRACE static inline int get_pt_level0_flags(pte_t *pt, size_t i)
+_NO_TRACE static inline int get_pt_level0_flags(pte_t *pt, size_t i)
 {
 	pte_level0_t *p = &pt[i].l0;
@@ -153,5 +153,5 @@
  *
  */
-NO_TRACE static inline int get_pt_level1_flags(pte_t *pt, size_t i)
+_NO_TRACE static inline int get_pt_level1_flags(pte_t *pt, size_t i)
 {
 	pte_level1_t *p = &pt[i].l1;
@@ -178,5 +178,5 @@
  *
  */
-NO_TRACE static inline void set_pt_level0_flags(pte_t *pt, size_t i, int flags)
+_NO_TRACE static inline void set_pt_level0_flags(pte_t *pt, size_t i, int flags)
 {
 	pte_level0_t *p = &pt[i].l0;
@@ -206,5 +206,5 @@
  *
  */
-NO_TRACE static inline void set_pt_level1_flags(pte_t *pt, size_t i, int flags)
+_NO_TRACE static inline void set_pt_level1_flags(pte_t *pt, size_t i, int flags)
 {
 	pte_level1_t *p = &pt[i].l1;
@@ -236,5 +236,5 @@
 }
 
-NO_TRACE static inline void set_pt_level0_present(pte_t *pt, size_t i)
+_NO_TRACE static inline void set_pt_level0_present(pte_t *pt, size_t i)
 {
 	pte_level0_t *p = &pt[i].l0;
@@ -245,5 +245,5 @@
 }
 
-NO_TRACE static inline void set_pt_level1_present(pte_t *pt, size_t i)
+_NO_TRACE static inline void set_pt_level1_present(pte_t *pt, size_t i)
 {
 	pte_level1_t *p = &pt[i].l1;
Index: kernel/arch/arm32/include/arch/mm/page_armv6.h
===================================================================
--- kernel/arch/arm32/include/arch/mm/page_armv6.h	(revision c477c804d1208352d69c7b069a54d3e3b650ff96)
+++ kernel/arch/arm32/include/arch/mm/page_armv6.h	(revision 401415aa8fcb6902c643bf1c028f08be8f7c2d8e)
@@ -164,5 +164,5 @@
  *
  */
-NO_TRACE static inline int get_pt_level0_flags(pte_t *pt, size_t i)
+_NO_TRACE static inline int get_pt_level0_flags(pte_t *pt, size_t i)
 {
 	const pte_level0_t *p = &pt[i].l0;
@@ -180,5 +180,5 @@
  *
  */
-NO_TRACE static inline int get_pt_level1_flags(pte_t *pt, size_t i)
+_NO_TRACE static inline int get_pt_level1_flags(pte_t *pt, size_t i)
 {
 	const pte_level1_t *p = &pt[i].l1;
@@ -206,5 +206,5 @@
  *
  */
-NO_TRACE static inline void set_pt_level0_flags(pte_t *pt, size_t i, int flags)
+_NO_TRACE static inline void set_pt_level0_flags(pte_t *pt, size_t i, int flags)
 {
 	pte_level0_t *p = &pt[i].l0;
@@ -239,5 +239,5 @@
  *
  */
-NO_TRACE static inline void set_pt_level1_flags(pte_t *pt, size_t i, int flags)
+_NO_TRACE static inline void set_pt_level1_flags(pte_t *pt, size_t i, int flags)
 {
 	pte_level1_t *p = &pt[i].l1;
@@ -297,5 +297,5 @@
 }
 
-NO_TRACE static inline void set_pt_level0_present(pte_t *pt, size_t i)
+_NO_TRACE static inline void set_pt_level0_present(pte_t *pt, size_t i)
 {
 	pte_level0_t *p = &pt[i].l0;
@@ -307,5 +307,5 @@
 }
 
-NO_TRACE static inline void set_pt_level1_present(pte_t *pt, size_t i)
+_NO_TRACE static inline void set_pt_level1_present(pte_t *pt, size_t i)
 {
 	pte_level1_t *p = &pt[i].l1;
Index: kernel/arch/ia32/include/arch/asm.h
===================================================================
--- kernel/arch/ia32/include/arch/asm.h	(revision c477c804d1208352d69c7b069a54d3e3b650ff96)
+++ kernel/arch/ia32/include/arch/asm.h	(revision 401415aa8fcb6902c643bf1c028f08be8f7c2d8e)
@@ -48,5 +48,5 @@
  *
  */
-NO_TRACE static inline __attribute__((noreturn)) void cpu_halt(void)
+_NO_TRACE static inline __attribute__((noreturn)) void cpu_halt(void)
 {
 	while (true) {
@@ -57,5 +57,5 @@
 }
 
-NO_TRACE static inline void cpu_sleep(void)
+_NO_TRACE static inline void cpu_sleep(void)
 {
 	asm volatile (
@@ -64,5 +64,5 @@
 }
 
-#define GEN_READ_REG(reg) NO_TRACE static inline sysarg_t read_ ##reg (void) \
+#define GEN_READ_REG(reg) _NO_TRACE static inline sysarg_t read_ ##reg (void) \
 	{ \
 		sysarg_t res; \
@@ -74,5 +74,5 @@
 	}
 
-#define GEN_WRITE_REG(reg) NO_TRACE static inline void write_ ##reg (sysarg_t regn) \
+#define GEN_WRITE_REG(reg) _NO_TRACE static inline void write_ ##reg (sysarg_t regn) \
 	{ \
 		asm volatile ( \
@@ -113,5 +113,5 @@
  *
  */
-NO_TRACE static inline void pio_write_8(ioport8_t *port, uint8_t val)
+_NO_TRACE static inline void pio_write_8(ioport8_t *port, uint8_t val)
 {
 	if (port < (ioport8_t *) IO_SPACE_BOUNDARY) {
@@ -132,5 +132,5 @@
  *
  */
-NO_TRACE static inline void pio_write_16(ioport16_t *port, uint16_t val)
+_NO_TRACE static inline void pio_write_16(ioport16_t *port, uint16_t val)
 {
 	if (port < (ioport16_t *) IO_SPACE_BOUNDARY) {
@@ -151,5 +151,5 @@
  *
  */
-NO_TRACE static inline void pio_write_32(ioport32_t *port, uint32_t val)
+_NO_TRACE static inline void pio_write_32(ioport32_t *port, uint32_t val)
 {
 	if (port < (ioport32_t *) IO_SPACE_BOUNDARY) {
@@ -170,5 +170,5 @@
  *
  */
-NO_TRACE static inline uint8_t pio_read_8(ioport8_t *port)
+_NO_TRACE static inline uint8_t pio_read_8(ioport8_t *port)
 {
 	if (((void *)port) < IO_SPACE_BOUNDARY) {
@@ -194,5 +194,5 @@
  *
  */
-NO_TRACE static inline uint16_t pio_read_16(ioport16_t *port)
+_NO_TRACE static inline uint16_t pio_read_16(ioport16_t *port)
 {
 	if (((void *)port) < IO_SPACE_BOUNDARY) {
@@ -218,5 +218,5 @@
  *
  */
-NO_TRACE static inline uint32_t pio_read_32(ioport32_t *port)
+_NO_TRACE static inline uint32_t pio_read_32(ioport32_t *port)
 {
 	if (((void *)port) < IO_SPACE_BOUNDARY) {
@@ -234,5 +234,5 @@
 }
 
-NO_TRACE static inline uint32_t read_eflags(void)
+_NO_TRACE static inline uint32_t read_eflags(void)
 {
 	uint32_t eflags;
@@ -247,5 +247,5 @@
 }
 
-NO_TRACE static inline void write_eflags(uint32_t eflags)
+_NO_TRACE static inline void write_eflags(uint32_t eflags)
 {
 	asm volatile (
@@ -261,5 +261,5 @@
  *
  */
-NO_TRACE static inline ipl_t interrupts_read(void)
+_NO_TRACE static inline ipl_t interrupts_read(void)
 {
 	return (ipl_t) read_eflags();
@@ -273,5 +273,5 @@
  *
  */
-NO_TRACE static inline ipl_t interrupts_enable(void)
+_NO_TRACE static inline ipl_t interrupts_enable(void)
 {
 	ipl_t ipl = interrupts_read();
@@ -289,5 +289,5 @@
  *
  */
-NO_TRACE static inline ipl_t interrupts_disable(void)
+_NO_TRACE static inline ipl_t interrupts_disable(void)
 {
 	ipl_t ipl = interrupts_read();
@@ -305,5 +305,5 @@
  *
  */
-NO_TRACE static inline void interrupts_restore(ipl_t ipl)
+_NO_TRACE static inline void interrupts_restore(ipl_t ipl)
 {
 	write_eflags((uint32_t) ipl);
@@ -315,5 +315,5 @@
  *
  */
-NO_TRACE static inline bool interrupts_disabled(void)
+_NO_TRACE static inline bool interrupts_disabled(void)
 {
 	return ((read_eflags() & EFLAGS_IF) == 0);
@@ -323,5 +323,5 @@
 
 /** Write to MSR */
-NO_TRACE static inline void write_msr(uint32_t msr, uint64_t value)
+_NO_TRACE static inline void write_msr(uint32_t msr, uint64_t value)
 {
 	asm volatile (
@@ -333,5 +333,5 @@
 }
 
-NO_TRACE static inline uint64_t read_msr(uint32_t msr)
+_NO_TRACE static inline uint64_t read_msr(uint32_t msr)
 {
 	uint32_t ax, dx;
@@ -356,5 +356,5 @@
  *
  */
-NO_TRACE static inline uintptr_t get_stack_base(void)
+_NO_TRACE static inline uintptr_t get_stack_base(void)
 {
 	uintptr_t v;
@@ -374,5 +374,5 @@
  *
  */
-NO_TRACE static inline void invlpg(uintptr_t addr)
+_NO_TRACE static inline void invlpg(uintptr_t addr)
 {
 	asm volatile (
@@ -387,5 +387,5 @@
  *
  */
-NO_TRACE static inline void gdtr_load(ptr_16_32_t *gdtr_reg)
+_NO_TRACE static inline void gdtr_load(ptr_16_32_t *gdtr_reg)
 {
 	asm volatile (
@@ -400,5 +400,5 @@
  *
  */
-NO_TRACE static inline void gdtr_store(ptr_16_32_t *gdtr_reg)
+_NO_TRACE static inline void gdtr_store(ptr_16_32_t *gdtr_reg)
 {
 	asm volatile (
@@ -413,5 +413,5 @@
  *
  */
-NO_TRACE static inline void idtr_load(ptr_16_32_t *idtr_reg)
+_NO_TRACE static inline void idtr_load(ptr_16_32_t *idtr_reg)
 {
 	asm volatile (
@@ -426,5 +426,5 @@
  *
  */
-NO_TRACE static inline void tr_load(uint16_t sel)
+_NO_TRACE static inline void tr_load(uint16_t sel)
 {
 	asm volatile (
@@ -439,5 +439,5 @@
  *
  */
-NO_TRACE static inline void gs_load(uint16_t sel)
+_NO_TRACE static inline void gs_load(uint16_t sel)
 {
 	asm volatile (
Index: kernel/arch/ia32/include/arch/cycle.h
===================================================================
--- kernel/arch/ia32/include/arch/cycle.h	(revision c477c804d1208352d69c7b069a54d3e3b650ff96)
+++ kernel/arch/ia32/include/arch/cycle.h	(revision 401415aa8fcb6902c643bf1c028f08be8f7c2d8e)
@@ -38,5 +38,5 @@
 #include <trace.h>
 
-NO_TRACE static inline uint64_t get_cycle(void)
+_NO_TRACE static inline uint64_t get_cycle(void)
 {
 #ifdef PROCESSOR_i486
Index: kernel/arch/ia32/include/arch/istate.h
===================================================================
--- kernel/arch/ia32/include/arch/istate.h	(revision c477c804d1208352d69c7b069a54d3e3b650ff96)
+++ kernel/arch/ia32/include/arch/istate.h	(revision 401415aa8fcb6902c643bf1c028f08be8f7c2d8e)
@@ -47,10 +47,10 @@
 
 /** Return true if exception happened while in userspace */
-NO_TRACE static inline int istate_from_uspace(istate_t *istate)
+_NO_TRACE static inline int istate_from_uspace(istate_t *istate)
 {
 	return (istate->cs & RPL_USER) == RPL_USER;
 }
 
-NO_TRACE static inline void istate_set_retaddr(istate_t *istate,
+_NO_TRACE static inline void istate_set_retaddr(istate_t *istate,
     uintptr_t retaddr)
 {
@@ -58,10 +58,10 @@
 }
 
-NO_TRACE static inline uintptr_t istate_get_pc(istate_t *istate)
+_NO_TRACE static inline uintptr_t istate_get_pc(istate_t *istate)
 {
 	return istate->eip;
 }
 
-NO_TRACE static inline uintptr_t istate_get_fp(istate_t *istate)
+_NO_TRACE static inline uintptr_t istate_get_fp(istate_t *istate)
 {
 	return istate->ebp;
Index: kernel/arch/ia32/include/arch/mm/page.h
===================================================================
--- kernel/arch/ia32/include/arch/mm/page.h	(revision c477c804d1208352d69c7b069a54d3e3b650ff96)
+++ kernel/arch/ia32/include/arch/mm/page.h	(revision 401415aa8fcb6902c643bf1c028f08be8f7c2d8e)
@@ -180,5 +180,5 @@
 } __attribute__((packed)) pte_t;
 
-NO_TRACE static inline unsigned int get_pt_flags(pte_t *pt, size_t i)
+_NO_TRACE static inline unsigned int get_pt_flags(pte_t *pt, size_t i)
 {
 	pte_t *p = &pt[i];
@@ -193,5 +193,5 @@
 }
 
-NO_TRACE static inline void set_pt_flags(pte_t *pt, size_t i, int flags)
+_NO_TRACE static inline void set_pt_flags(pte_t *pt, size_t i, int flags)
 {
 	pte_t *p = &pt[i];
@@ -210,5 +210,5 @@
 }
 
-NO_TRACE static inline void set_pt_present(pte_t *pt, size_t i)
+_NO_TRACE static inline void set_pt_present(pte_t *pt, size_t i)
 {
 	pte_t *p = &pt[i];
Index: kernel/arch/ia64/include/arch/asm.h
===================================================================
--- kernel/arch/ia64/include/arch/asm.h	(revision c477c804d1208352d69c7b069a54d3e3b650ff96)
+++ kernel/arch/ia64/include/arch/asm.h	(revision 401415aa8fcb6902c643bf1c028f08be8f7c2d8e)
@@ -45,5 +45,5 @@
 
 /** Map the I/O port address to a legacy I/O address. */
-NO_TRACE static inline uintptr_t p2a(volatile void *p)
+_NO_TRACE static inline uintptr_t p2a(volatile void *p)
 {
 	uintptr_t prt = (uintptr_t) p;
@@ -52,5 +52,5 @@
 }
 
-NO_TRACE static inline void pio_write_8(ioport8_t *port, uint8_t v)
+_NO_TRACE static inline void pio_write_8(ioport8_t *port, uint8_t v)
 {
 	if (port < (ioport8_t *) IO_SPACE_BOUNDARY)
@@ -66,5 +66,5 @@
 }
 
-NO_TRACE static inline void pio_write_16(ioport16_t *port, uint16_t v)
+_NO_TRACE static inline void pio_write_16(ioport16_t *port, uint16_t v)
 {
 	if (port < (ioport16_t *) IO_SPACE_BOUNDARY)
@@ -80,5 +80,5 @@
 }
 
-NO_TRACE static inline void pio_write_32(ioport32_t *port, uint32_t v)
+_NO_TRACE static inline void pio_write_32(ioport32_t *port, uint32_t v)
 {
 	if (port < (ioport32_t *) IO_SPACE_BOUNDARY)
@@ -94,5 +94,5 @@
 }
 
-NO_TRACE static inline uint8_t pio_read_8(ioport8_t *port)
+_NO_TRACE static inline uint8_t pio_read_8(ioport8_t *port)
 {
 	uint8_t v;
@@ -116,5 +116,5 @@
 }
 
-NO_TRACE static inline uint16_t pio_read_16(ioport16_t *port)
+_NO_TRACE static inline uint16_t pio_read_16(ioport16_t *port)
 {
 	uint16_t v;
@@ -138,5 +138,5 @@
 }
 
-NO_TRACE static inline uint32_t pio_read_32(ioport32_t *port)
+_NO_TRACE static inline uint32_t pio_read_32(ioport32_t *port)
 {
 	uint32_t v;
@@ -166,5 +166,5 @@
  * The memory stack must start on page boundary.
  */
-NO_TRACE static inline uintptr_t get_stack_base(void)
+_NO_TRACE static inline uintptr_t get_stack_base(void)
 {
 	uint64_t value;
@@ -183,5 +183,5 @@
  *
  */
-NO_TRACE static inline uint64_t psr_read(void)
+_NO_TRACE static inline uint64_t psr_read(void)
 {
 	uint64_t v;
@@ -200,5 +200,5 @@
  *
  */
-NO_TRACE static inline uint64_t iva_read(void)
+_NO_TRACE static inline uint64_t iva_read(void)
 {
 	uint64_t v;
@@ -217,5 +217,5 @@
  *
  */
-NO_TRACE static inline void iva_write(uint64_t v)
+_NO_TRACE static inline void iva_write(uint64_t v)
 {
 	asm volatile (
@@ -231,5 +231,5 @@
  *
  */
-NO_TRACE static inline uint64_t ivr_read(void)
+_NO_TRACE static inline uint64_t ivr_read(void)
 {
 	uint64_t v;
@@ -243,5 +243,5 @@
 }
 
-NO_TRACE static inline uint64_t cr64_read(void)
+_NO_TRACE static inline uint64_t cr64_read(void)
 {
 	uint64_t v;
@@ -260,5 +260,5 @@
  *
  */
-NO_TRACE static inline void itc_write(uint64_t v)
+_NO_TRACE static inline void itc_write(uint64_t v)
 {
 	asm volatile (
@@ -273,5 +273,5 @@
  *
  */
-NO_TRACE static inline uint64_t itc_read(void)
+_NO_TRACE static inline uint64_t itc_read(void)
 {
 	uint64_t v;
@@ -290,5 +290,5 @@
  *
  */
-NO_TRACE static inline void itm_write(uint64_t v)
+_NO_TRACE static inline void itm_write(uint64_t v)
 {
 	asm volatile (
@@ -303,5 +303,5 @@
  *
  */
-NO_TRACE static inline uint64_t itm_read(void)
+_NO_TRACE static inline uint64_t itm_read(void)
 {
 	uint64_t v;
@@ -320,5 +320,5 @@
  *
  */
-NO_TRACE static inline uint64_t itv_read(void)
+_NO_TRACE static inline uint64_t itv_read(void)
 {
 	uint64_t v;
@@ -337,5 +337,5 @@
  *
  */
-NO_TRACE static inline void itv_write(uint64_t v)
+_NO_TRACE static inline void itv_write(uint64_t v)
 {
 	asm volatile (
@@ -350,5 +350,5 @@
  *
  */
-NO_TRACE static inline void eoi_write(uint64_t v)
+_NO_TRACE static inline void eoi_write(uint64_t v)
 {
 	asm volatile (
@@ -363,5 +363,5 @@
  *
  */
-NO_TRACE static inline uint64_t tpr_read(void)
+_NO_TRACE static inline uint64_t tpr_read(void)
 {
 	uint64_t v;
@@ -380,5 +380,5 @@
  *
  */
-NO_TRACE static inline void tpr_write(uint64_t v)
+_NO_TRACE static inline void tpr_write(uint64_t v)
 {
 	asm volatile (
@@ -396,5 +396,5 @@
  *
  */
-NO_TRACE static ipl_t interrupts_disable(void)
+_NO_TRACE static ipl_t interrupts_disable(void)
 {
 	uint64_t v;
@@ -418,5 +418,5 @@
  *
  */
-NO_TRACE static ipl_t interrupts_enable(void)
+_NO_TRACE static ipl_t interrupts_enable(void)
 {
 	uint64_t v;
@@ -441,5 +441,5 @@
  *
  */
-NO_TRACE static inline void interrupts_restore(ipl_t ipl)
+_NO_TRACE static inline void interrupts_restore(ipl_t ipl)
 {
 	if (ipl & PSR_I_MASK)
@@ -454,5 +454,5 @@
  *
  */
-NO_TRACE static inline ipl_t interrupts_read(void)
+_NO_TRACE static inline ipl_t interrupts_read(void)
 {
 	return (ipl_t) psr_read();
@@ -464,5 +464,5 @@
  *
  */
-NO_TRACE static inline bool interrupts_disabled(void)
+_NO_TRACE static inline bool interrupts_disabled(void)
 {
 	return !(psr_read() & PSR_I_MASK);
@@ -470,5 +470,5 @@
 
 /** Disable protection key checking. */
-NO_TRACE static inline void pk_disable(void)
+_NO_TRACE static inline void pk_disable(void)
 {
 	asm volatile (
Index: kernel/arch/ia64/include/arch/cpu.h
===================================================================
--- kernel/arch/ia64/include/arch/cpu.h	(revision c477c804d1208352d69c7b069a54d3e3b650ff96)
+++ kernel/arch/ia64/include/arch/cpu.h	(revision 401415aa8fcb6902c643bf1c028f08be8f7c2d8e)
@@ -64,5 +64,5 @@
  *
  */
-NO_TRACE static inline uint64_t cpuid_read(int n)
+_NO_TRACE static inline uint64_t cpuid_read(int n)
 {
 	uint64_t v;
@@ -77,5 +77,5 @@
 }
 
-NO_TRACE static inline int ia64_get_cpu_id(void)
+_NO_TRACE static inline int ia64_get_cpu_id(void)
 {
 	uint64_t cr64 = cr64_read();
@@ -83,5 +83,5 @@
 }
 
-NO_TRACE static inline int ia64_get_cpu_eid(void)
+_NO_TRACE static inline int ia64_get_cpu_eid(void)
 {
 	uint64_t cr64 = cr64_read();
@@ -89,5 +89,5 @@
 }
 
-NO_TRACE static inline void ipi_send_ipi(int id, int eid, int intno)
+_NO_TRACE static inline void ipi_send_ipi(int id, int eid, int intno)
 {
 	(bootinfo->sapic)[2 * (id * 256 + eid)] = intno;
Index: kernel/arch/ia64/include/arch/cycle.h
===================================================================
--- kernel/arch/ia64/include/arch/cycle.h	(revision c477c804d1208352d69c7b069a54d3e3b650ff96)
+++ kernel/arch/ia64/include/arch/cycle.h	(revision 401415aa8fcb6902c643bf1c028f08be8f7c2d8e)
@@ -38,5 +38,5 @@
 #include <trace.h>
 
-NO_TRACE static inline uint64_t get_cycle(void)
+_NO_TRACE static inline uint64_t get_cycle(void)
 {
 	return 0;
Index: kernel/arch/ia64/include/arch/istate.h
===================================================================
--- kernel/arch/ia64/include/arch/istate.h	(revision c477c804d1208352d69c7b069a54d3e3b650ff96)
+++ kernel/arch/ia64/include/arch/istate.h	(revision 401415aa8fcb6902c643bf1c028f08be8f7c2d8e)
@@ -50,5 +50,5 @@
 #endif /* KERNEL */
 
-NO_TRACE static inline void istate_set_retaddr(istate_t *istate,
+_NO_TRACE static inline void istate_set_retaddr(istate_t *istate,
     uintptr_t retaddr)
 {
@@ -57,10 +57,10 @@
 }
 
-NO_TRACE static inline uintptr_t istate_get_pc(istate_t *istate)
+_NO_TRACE static inline uintptr_t istate_get_pc(istate_t *istate)
 {
 	return istate->cr_iip;
 }
 
-NO_TRACE static inline uintptr_t istate_get_fp(istate_t *istate)
+_NO_TRACE static inline uintptr_t istate_get_fp(istate_t *istate)
 {
 	/* FIXME */
@@ -69,5 +69,5 @@
 }
 
-NO_TRACE static inline int istate_from_uspace(istate_t *istate)
+_NO_TRACE static inline int istate_from_uspace(istate_t *istate)
 {
 	return (istate->cr_iip) < 0xe000000000000000ULL;
Index: kernel/arch/ia64/include/arch/mm/page.h
===================================================================
--- kernel/arch/ia64/include/arch/mm/page.h	(revision c477c804d1208352d69c7b069a54d3e3b650ff96)
+++ kernel/arch/ia64/include/arch/mm/page.h	(revision 401415aa8fcb6902c643bf1c028f08be8f7c2d8e)
@@ -191,5 +191,5 @@
  * @return Address of the head of VHPT collision chain.
  */
-NO_TRACE static inline uint64_t thash(uint64_t va)
+_NO_TRACE static inline uint64_t thash(uint64_t va)
 {
 	uint64_t ret;
@@ -213,5 +213,5 @@
  * @return The unique tag for VPN and RID in the collision chain returned by thash().
  */
-NO_TRACE static inline uint64_t ttag(uint64_t va)
+_NO_TRACE static inline uint64_t ttag(uint64_t va)
 {
 	uint64_t ret;
@@ -232,5 +232,5 @@
  * @return Current contents of rr[i].
  */
-NO_TRACE static inline uint64_t rr_read(size_t i)
+_NO_TRACE static inline uint64_t rr_read(size_t i)
 {
 	uint64_t ret;
@@ -252,5 +252,5 @@
  * @param v Value to be written to rr[i].
  */
-NO_TRACE static inline void rr_write(size_t i, uint64_t v)
+_NO_TRACE static inline void rr_write(size_t i, uint64_t v)
 {
 	assert(i < REGION_REGISTERS);
@@ -267,5 +267,5 @@
  * @return Current value stored in PTA.
  */
-NO_TRACE static inline uint64_t pta_read(void)
+_NO_TRACE static inline uint64_t pta_read(void)
 {
 	uint64_t ret;
@@ -283,5 +283,5 @@
  * @param v New value to be stored in PTA.
  */
-NO_TRACE static inline void pta_write(uint64_t v)
+_NO_TRACE static inline void pta_write(uint64_t v)
 {
 	asm volatile (
Index: kernel/arch/mips32/include/arch/asm.h
===================================================================
--- kernel/arch/mips32/include/arch/asm.h	(revision c477c804d1208352d69c7b069a54d3e3b650ff96)
+++ kernel/arch/mips32/include/arch/asm.h	(revision 401415aa8fcb6902c643bf1c028f08be8f7c2d8e)
@@ -40,5 +40,5 @@
 #include <trace.h>
 
-NO_TRACE static inline void cpu_sleep(void)
+_NO_TRACE static inline void cpu_sleep(void)
 {
 	asm volatile ("wait");
@@ -52,5 +52,5 @@
  *
  */
-NO_TRACE static inline uintptr_t get_stack_base(void)
+_NO_TRACE static inline uintptr_t get_stack_base(void)
 {
 	uintptr_t base;
@@ -65,30 +65,30 @@
 }
 
-NO_TRACE static inline void pio_write_8(ioport8_t *port, uint8_t v)
+_NO_TRACE static inline void pio_write_8(ioport8_t *port, uint8_t v)
 {
 	*port = v;
 }
 
-NO_TRACE static inline void pio_write_16(ioport16_t *port, uint16_t v)
+_NO_TRACE static inline void pio_write_16(ioport16_t *port, uint16_t v)
 {
 	*port = v;
 }
 
-NO_TRACE static inline void pio_write_32(ioport32_t *port, uint32_t v)
+_NO_TRACE static inline void pio_write_32(ioport32_t *port, uint32_t v)
 {
 	*port = v;
 }
 
-NO_TRACE static inline uint8_t pio_read_8(ioport8_t *port)
+_NO_TRACE static inline uint8_t pio_read_8(ioport8_t *port)
 {
 	return *port;
 }
 
-NO_TRACE static inline uint16_t pio_read_16(ioport16_t *port)
+_NO_TRACE static inline uint16_t pio_read_16(ioport16_t *port)
 {
 	return *port;
 }
 
-NO_TRACE static inline uint32_t pio_read_32(ioport32_t *port)
+_NO_TRACE static inline uint32_t pio_read_32(ioport32_t *port)
 {
 	return *port;
Index: kernel/arch/mips32/include/arch/cycle.h
===================================================================
--- kernel/arch/mips32/include/arch/cycle.h	(revision c477c804d1208352d69c7b069a54d3e3b650ff96)
+++ kernel/arch/mips32/include/arch/cycle.h	(revision 401415aa8fcb6902c643bf1c028f08be8f7c2d8e)
@@ -40,5 +40,5 @@
 #include <trace.h>
 
-NO_TRACE static inline uint64_t get_cycle(void)
+_NO_TRACE static inline uint64_t get_cycle(void)
 {
 	return ((uint64_t) count_hi << 32) + ((uint64_t) cp0_count_read());
Index: kernel/arch/mips32/include/arch/istate.h
===================================================================
--- kernel/arch/mips32/include/arch/istate.h	(revision c477c804d1208352d69c7b069a54d3e3b650ff96)
+++ kernel/arch/mips32/include/arch/istate.h	(revision 401415aa8fcb6902c643bf1c028f08be8f7c2d8e)
@@ -50,5 +50,5 @@
 #endif /* KERNEL */
 
-NO_TRACE static inline void istate_set_retaddr(istate_t *istate,
+_NO_TRACE static inline void istate_set_retaddr(istate_t *istate,
     uintptr_t retaddr)
 {
@@ -57,15 +57,15 @@
 
 /** Return true if exception happened while in userspace */
-NO_TRACE static inline int istate_from_uspace(istate_t *istate)
+_NO_TRACE static inline int istate_from_uspace(istate_t *istate)
 {
 	return istate->status & cp0_status_um_bit;
 }
 
-NO_TRACE static inline uintptr_t istate_get_pc(istate_t *istate)
+_NO_TRACE static inline uintptr_t istate_get_pc(istate_t *istate)
 {
 	return istate->epc;
 }
 
-NO_TRACE static inline uintptr_t istate_get_fp(istate_t *istate)
+_NO_TRACE static inline uintptr_t istate_get_fp(istate_t *istate)
 {
 	return istate->sp;
Index: kernel/arch/mips32/include/arch/mm/page.h
===================================================================
--- kernel/arch/mips32/include/arch/mm/page.h	(revision c477c804d1208352d69c7b069a54d3e3b650ff96)
+++ kernel/arch/mips32/include/arch/mm/page.h	(revision 401415aa8fcb6902c643bf1c028f08be8f7c2d8e)
@@ -161,5 +161,5 @@
 } pte_t;
 
-NO_TRACE static inline unsigned int get_pt_flags(pte_t *pt, size_t i)
+_NO_TRACE static inline unsigned int get_pt_flags(pte_t *pt, size_t i)
 {
 	pte_t *p = &pt[i];
@@ -174,5 +174,5 @@
 }
 
-NO_TRACE static inline void set_pt_flags(pte_t *pt, size_t i, int flags)
+_NO_TRACE static inline void set_pt_flags(pte_t *pt, size_t i, int flags)
 {
 	pte_t *p = &pt[i];
@@ -189,5 +189,5 @@
 }
 
-NO_TRACE static inline void set_pt_present(pte_t *pt, size_t i)
+_NO_TRACE static inline void set_pt_present(pte_t *pt, size_t i)
 {
 	pte_t *p = &pt[i];
Index: kernel/arch/mips32/include/arch/mm/tlb.h
===================================================================
--- kernel/arch/mips32/include/arch/mm/tlb.h	(revision c477c804d1208352d69c7b069a54d3e3b650ff96)
+++ kernel/arch/mips32/include/arch/mm/tlb.h	(revision 401415aa8fcb6902c643bf1c028f08be8f7c2d8e)
@@ -135,5 +135,5 @@
  * Probe TLB for Matching Entry.
  */
-NO_TRACE static inline void tlbp(void)
+_NO_TRACE static inline void tlbp(void)
 {
 	asm volatile ("tlbp\n\t");
@@ -144,5 +144,5 @@
  * Read Indexed TLB Entry.
  */
-NO_TRACE static inline void tlbr(void)
+_NO_TRACE static inline void tlbr(void)
 {
 	asm volatile ("tlbr\n\t");
@@ -153,5 +153,5 @@
  * Write Indexed TLB Entry.
  */
-NO_TRACE static inline void tlbwi(void)
+_NO_TRACE static inline void tlbwi(void)
 {
 	asm volatile ("tlbwi\n\t");
@@ -162,5 +162,5 @@
  * Write Random TLB Entry.
  */
-NO_TRACE static inline void tlbwr(void)
+_NO_TRACE static inline void tlbwr(void)
 {
 	asm volatile ("tlbwr\n\t");
Index: kernel/arch/ppc32/include/arch/asm.h
===================================================================
--- kernel/arch/ppc32/include/arch/asm.h	(revision c477c804d1208352d69c7b069a54d3e3b650ff96)
+++ kernel/arch/ppc32/include/arch/asm.h	(revision 401415aa8fcb6902c643bf1c028f08be8f7c2d8e)
@@ -42,5 +42,5 @@
 #include <trace.h>
 
-NO_TRACE static inline uint32_t msr_read(void)
+_NO_TRACE static inline uint32_t msr_read(void)
 {
 	uint32_t msr;
@@ -54,5 +54,5 @@
 }
 
-NO_TRACE static inline void msr_write(uint32_t msr)
+_NO_TRACE static inline void msr_write(uint32_t msr)
 {
 	asm volatile (
@@ -63,5 +63,5 @@
 }
 
-NO_TRACE static inline void sr_set(uint32_t flags, asid_t asid, uint32_t sr)
+_NO_TRACE static inline void sr_set(uint32_t flags, asid_t asid, uint32_t sr)
 {
 	asm volatile (
@@ -74,5 +74,5 @@
 }
 
-NO_TRACE static inline uint32_t sr_get(uint32_t vaddr)
+_NO_TRACE static inline uint32_t sr_get(uint32_t vaddr)
 {
 	uint32_t vsid;
@@ -87,5 +87,5 @@
 }
 
-NO_TRACE static inline uint32_t sdr1_get(void)
+_NO_TRACE static inline uint32_t sdr1_get(void)
 {
 	uint32_t sdr1;
@@ -107,5 +107,5 @@
  *
  */
-NO_TRACE static inline ipl_t interrupts_enable(void)
+_NO_TRACE static inline ipl_t interrupts_enable(void)
 {
 	ipl_t ipl = msr_read();
@@ -122,5 +122,5 @@
  *
  */
-NO_TRACE static inline ipl_t interrupts_disable(void)
+_NO_TRACE static inline ipl_t interrupts_disable(void)
 {
 	ipl_t ipl = msr_read();
@@ -136,5 +136,5 @@
  *
  */
-NO_TRACE static inline void interrupts_restore(ipl_t ipl)
+_NO_TRACE static inline void interrupts_restore(ipl_t ipl)
 {
 	msr_write((msr_read() & (~MSR_EE)) | (ipl & MSR_EE));
@@ -148,5 +148,5 @@
  *
  */
-NO_TRACE static inline ipl_t interrupts_read(void)
+_NO_TRACE static inline ipl_t interrupts_read(void)
 {
 	return msr_read();
@@ -158,5 +158,5 @@
  *
  */
-NO_TRACE static inline bool interrupts_disabled(void)
+_NO_TRACE static inline bool interrupts_disabled(void)
 {
 	return ((msr_read() & MSR_EE) == 0);
@@ -170,5 +170,5 @@
  *
  */
-NO_TRACE static inline uintptr_t get_stack_base(void)
+_NO_TRACE static inline uintptr_t get_stack_base(void)
 {
 	uintptr_t base;
@@ -183,34 +183,34 @@
 }
 
-NO_TRACE static inline void cpu_sleep(void)
-{
-}
-
-NO_TRACE static inline void pio_write_8(ioport8_t *port, uint8_t v)
+_NO_TRACE static inline void cpu_sleep(void)
+{
+}
+
+_NO_TRACE static inline void pio_write_8(ioport8_t *port, uint8_t v)
 {
 	*port = v;
 }
 
-NO_TRACE static inline void pio_write_16(ioport16_t *port, uint16_t v)
+_NO_TRACE static inline void pio_write_16(ioport16_t *port, uint16_t v)
 {
 	*port = v;
 }
 
-NO_TRACE static inline void pio_write_32(ioport32_t *port, uint32_t v)
+_NO_TRACE static inline void pio_write_32(ioport32_t *port, uint32_t v)
 {
 	*port = v;
 }
 
-NO_TRACE static inline uint8_t pio_read_8(ioport8_t *port)
+_NO_TRACE static inline uint8_t pio_read_8(ioport8_t *port)
 {
 	return *port;
 }
 
-NO_TRACE static inline uint16_t pio_read_16(ioport16_t *port)
+_NO_TRACE static inline uint16_t pio_read_16(ioport16_t *port)
 {
 	return *port;
 }
 
-NO_TRACE static inline uint32_t pio_read_32(ioport32_t *port)
+_NO_TRACE static inline uint32_t pio_read_32(ioport32_t *port)
 {
 	return *port;
Index: kernel/arch/ppc32/include/arch/cpu.h
===================================================================
--- kernel/arch/ppc32/include/arch/cpu.h	(revision c477c804d1208352d69c7b069a54d3e3b650ff96)
+++ kernel/arch/ppc32/include/arch/cpu.h	(revision 401415aa8fcb6902c643bf1c028f08be8f7c2d8e)
@@ -44,5 +44,5 @@
 } __attribute__((packed)) cpu_arch_t;
 
-NO_TRACE static inline void cpu_version(cpu_arch_t *info)
+_NO_TRACE static inline void cpu_version(cpu_arch_t *info)
 {
 	asm volatile (
Index: kernel/arch/ppc32/include/arch/cycle.h
===================================================================
--- kernel/arch/ppc32/include/arch/cycle.h	(revision c477c804d1208352d69c7b069a54d3e3b650ff96)
+++ kernel/arch/ppc32/include/arch/cycle.h	(revision 401415aa8fcb6902c643bf1c028f08be8f7c2d8e)
@@ -38,5 +38,5 @@
 #include <trace.h>
 
-NO_TRACE static inline uint64_t get_cycle(void)
+_NO_TRACE static inline uint64_t get_cycle(void)
 {
 	uint32_t lower;
Index: kernel/arch/ppc32/include/arch/istate.h
===================================================================
--- kernel/arch/ppc32/include/arch/istate.h	(revision c477c804d1208352d69c7b069a54d3e3b650ff96)
+++ kernel/arch/ppc32/include/arch/istate.h	(revision 401415aa8fcb6902c643bf1c028f08be8f7c2d8e)
@@ -50,5 +50,5 @@
 #endif /* KERNEL */
 
-NO_TRACE static inline void istate_set_retaddr(istate_t *istate,
+_NO_TRACE static inline void istate_set_retaddr(istate_t *istate,
     uintptr_t retaddr)
 {
@@ -61,15 +61,15 @@
  *
  */
-NO_TRACE static inline int istate_from_uspace(istate_t *istate)
+_NO_TRACE static inline int istate_from_uspace(istate_t *istate)
 {
 	return (istate->srr1 & MSR_PR) != 0;
 }
 
-NO_TRACE static inline sysarg_t istate_get_pc(istate_t *istate)
+_NO_TRACE static inline sysarg_t istate_get_pc(istate_t *istate)
 {
 	return istate->pc;
 }
 
-NO_TRACE static inline sysarg_t istate_get_fp(istate_t *istate)
+_NO_TRACE static inline sysarg_t istate_get_fp(istate_t *istate)
 {
 	return istate->sp;
Index: kernel/arch/ppc32/include/arch/mm/frame.h
===================================================================
--- kernel/arch/ppc32/include/arch/mm/frame.h	(revision c477c804d1208352d69c7b069a54d3e3b650ff96)
+++ kernel/arch/ppc32/include/arch/mm/frame.h	(revision 401415aa8fcb6902c643bf1c028f08be8f7c2d8e)
@@ -46,5 +46,5 @@
 #include <trace.h>
 
-NO_TRACE static inline uint32_t physmem_top(void)
+_NO_TRACE static inline uint32_t physmem_top(void)
 {
 	uint32_t physmem;
Index: kernel/arch/ppc32/include/arch/mm/page.h
===================================================================
--- kernel/arch/ppc32/include/arch/mm/page.h	(revision c477c804d1208352d69c7b069a54d3e3b650ff96)
+++ kernel/arch/ppc32/include/arch/mm/page.h	(revision 401415aa8fcb6902c643bf1c028f08be8f7c2d8e)
@@ -162,5 +162,5 @@
 } pte_t;
 
-NO_TRACE static inline unsigned int get_pt_flags(pte_t *pt, size_t i)
+_NO_TRACE static inline unsigned int get_pt_flags(pte_t *pt, size_t i)
 {
 	pte_t *entry = &pt[i];
@@ -175,5 +175,5 @@
 }
 
-NO_TRACE static inline void set_pt_flags(pte_t *pt, size_t i, int flags)
+_NO_TRACE static inline void set_pt_flags(pte_t *pt, size_t i, int flags)
 {
 	pte_t *entry = &pt[i];
@@ -185,5 +185,5 @@
 }
 
-NO_TRACE static inline void set_pt_present(pte_t *pt, size_t i)
+_NO_TRACE static inline void set_pt_present(pte_t *pt, size_t i)
 {
 	pte_t *entry = &pt[i];
Index: kernel/arch/riscv64/include/arch/asm.h
===================================================================
--- kernel/arch/riscv64/include/arch/asm.h	(revision c477c804d1208352d69c7b069a54d3e3b650ff96)
+++ kernel/arch/riscv64/include/arch/asm.h	(revision 401415aa8fcb6902c643bf1c028f08be8f7c2d8e)
@@ -42,5 +42,5 @@
 #include <trace.h>
 
-NO_TRACE static inline ipl_t interrupts_enable(void)
+_NO_TRACE static inline ipl_t interrupts_enable(void)
 {
 	ipl_t ipl;
@@ -54,5 +54,5 @@
 }
 
-NO_TRACE static inline ipl_t interrupts_disable(void)
+_NO_TRACE static inline ipl_t interrupts_disable(void)
 {
 	ipl_t ipl;
@@ -66,5 +66,5 @@
 }
 
-NO_TRACE static inline void interrupts_restore(ipl_t ipl)
+_NO_TRACE static inline void interrupts_restore(ipl_t ipl)
 {
 	if ((ipl & SSTATUS_SIE_MASK) == SSTATUS_SIE_MASK)
@@ -74,5 +74,5 @@
 }
 
-NO_TRACE static inline ipl_t interrupts_read(void)
+_NO_TRACE static inline ipl_t interrupts_read(void)
 {
 	ipl_t ipl;
@@ -86,10 +86,10 @@
 }
 
-NO_TRACE static inline bool interrupts_disabled(void)
+_NO_TRACE static inline bool interrupts_disabled(void)
 {
 	return ((interrupts_read() & SSTATUS_SIE_MASK) == 0);
 }
 
-NO_TRACE static inline uintptr_t get_stack_base(void)
+_NO_TRACE static inline uintptr_t get_stack_base(void)
 {
 	uintptr_t base;
@@ -104,34 +104,34 @@
 }
 
-NO_TRACE static inline void cpu_sleep(void)
+_NO_TRACE static inline void cpu_sleep(void)
 {
 }
 
-NO_TRACE static inline void pio_write_8(ioport8_t *port, uint8_t v)
+_NO_TRACE static inline void pio_write_8(ioport8_t *port, uint8_t v)
 {
 	*port = v;
 }
 
-NO_TRACE static inline void pio_write_16(ioport16_t *port, uint16_t v)
+_NO_TRACE static inline void pio_write_16(ioport16_t *port, uint16_t v)
 {
 	*port = v;
 }
 
-NO_TRACE static inline void pio_write_32(ioport32_t *port, uint32_t v)
+_NO_TRACE static inline void pio_write_32(ioport32_t *port, uint32_t v)
 {
 	*port = v;
 }
 
-NO_TRACE static inline uint8_t pio_read_8(ioport8_t *port)
+_NO_TRACE static inline uint8_t pio_read_8(ioport8_t *port)
 {
 	return *port;
 }
 
-NO_TRACE static inline uint16_t pio_read_16(ioport16_t *port)
+_NO_TRACE static inline uint16_t pio_read_16(ioport16_t *port)
 {
 	return *port;
 }
 
-NO_TRACE static inline uint32_t pio_read_32(ioport32_t *port)
+_NO_TRACE static inline uint32_t pio_read_32(ioport32_t *port)
 {
 	return *port;
Index: kernel/arch/riscv64/include/arch/cycle.h
===================================================================
--- kernel/arch/riscv64/include/arch/cycle.h	(revision c477c804d1208352d69c7b069a54d3e3b650ff96)
+++ kernel/arch/riscv64/include/arch/cycle.h	(revision 401415aa8fcb6902c643bf1c028f08be8f7c2d8e)
@@ -38,5 +38,5 @@
 #include <trace.h>
 
-NO_TRACE static inline uint64_t get_cycle(void)
+_NO_TRACE static inline uint64_t get_cycle(void)
 {
 	uint64_t cycle;
Index: kernel/arch/riscv64/include/arch/istate.h
===================================================================
--- kernel/arch/riscv64/include/arch/istate.h	(revision c477c804d1208352d69c7b069a54d3e3b650ff96)
+++ kernel/arch/riscv64/include/arch/istate.h	(revision 401415aa8fcb6902c643bf1c028f08be8f7c2d8e)
@@ -44,5 +44,5 @@
 #endif
 
-NO_TRACE static inline int istate_from_uspace(istate_t *istate)
+_NO_TRACE static inline int istate_from_uspace(istate_t *istate)
 {
 	// FIXME
@@ -50,5 +50,5 @@
 }
 
-NO_TRACE static inline void istate_set_retaddr(istate_t *istate,
+_NO_TRACE static inline void istate_set_retaddr(istate_t *istate,
     uintptr_t retaddr)
 {
@@ -56,5 +56,5 @@
 }
 
-NO_TRACE static inline uintptr_t istate_get_pc(istate_t *istate)
+_NO_TRACE static inline uintptr_t istate_get_pc(istate_t *istate)
 {
 	// FIXME
@@ -62,5 +62,5 @@
 }
 
-NO_TRACE static inline uintptr_t istate_get_fp(istate_t *istate)
+_NO_TRACE static inline uintptr_t istate_get_fp(istate_t *istate)
 {
 	// FIXME
Index: kernel/arch/riscv64/include/arch/mm/page.h
===================================================================
--- kernel/arch/riscv64/include/arch/mm/page.h	(revision c477c804d1208352d69c7b069a54d3e3b650ff96)
+++ kernel/arch/riscv64/include/arch/mm/page.h	(revision 401415aa8fcb6902c643bf1c028f08be8f7c2d8e)
@@ -179,5 +179,5 @@
 } pte_t;
 
-NO_TRACE static inline unsigned int get_pt_flags(pte_t *pt, size_t i)
+_NO_TRACE static inline unsigned int get_pt_flags(pte_t *pt, size_t i)
 {
 	pte_t *entry = &pt[i];
@@ -191,5 +191,5 @@
 }
 
-NO_TRACE static inline void set_pt_flags(pte_t *pt, size_t i, int flags)
+_NO_TRACE static inline void set_pt_flags(pte_t *pt, size_t i, int flags)
 {
 	pte_t *entry = &pt[i];
@@ -205,5 +205,5 @@
 }
 
-NO_TRACE static inline void set_pt_present(pte_t *pt, size_t i)
+_NO_TRACE static inline void set_pt_present(pte_t *pt, size_t i)
 {
 	pte_t *entry = &pt[i];
Index: kernel/arch/sparc64/include/arch/asm.h
===================================================================
--- kernel/arch/sparc64/include/arch/asm.h	(revision c477c804d1208352d69c7b069a54d3e3b650ff96)
+++ kernel/arch/sparc64/include/arch/asm.h	(revision 401415aa8fcb6902c643bf1c028f08be8f7c2d8e)
@@ -44,5 +44,5 @@
 #include <trace.h>
 
-NO_TRACE static inline void pio_write_8(ioport8_t *port, uint8_t v)
+_NO_TRACE static inline void pio_write_8(ioport8_t *port, uint8_t v)
 {
 	*port = v;
@@ -50,5 +50,5 @@
 }
 
-NO_TRACE static inline void pio_write_16(ioport16_t *port, uint16_t v)
+_NO_TRACE static inline void pio_write_16(ioport16_t *port, uint16_t v)
 {
 	*port = v;
@@ -56,5 +56,5 @@
 }
 
-NO_TRACE static inline void pio_write_32(ioport32_t *port, uint32_t v)
+_NO_TRACE static inline void pio_write_32(ioport32_t *port, uint32_t v)
 {
 	*port = v;
@@ -62,5 +62,5 @@
 }
 
-NO_TRACE static inline uint8_t pio_read_8(ioport8_t *port)
+_NO_TRACE static inline uint8_t pio_read_8(ioport8_t *port)
 {
 	uint8_t rv = *port;
@@ -69,5 +69,5 @@
 }
 
-NO_TRACE static inline uint16_t pio_read_16(ioport16_t *port)
+_NO_TRACE static inline uint16_t pio_read_16(ioport16_t *port)
 {
 	uint16_t rv = *port;
@@ -76,5 +76,5 @@
 }
 
-NO_TRACE static inline uint32_t pio_read_32(ioport32_t *port)
+_NO_TRACE static inline uint32_t pio_read_32(ioport32_t *port)
 {
 	uint32_t rv = *port;
@@ -88,5 +88,5 @@
  *
  */
-NO_TRACE static inline uint64_t pstate_read(void)
+_NO_TRACE static inline uint64_t pstate_read(void)
 {
 	uint64_t v;
@@ -105,5 +105,5 @@
  *
  */
-NO_TRACE static inline void pstate_write(uint64_t v)
+_NO_TRACE static inline void pstate_write(uint64_t v)
 {
 	asm volatile (
@@ -119,5 +119,5 @@
  *
  */
-NO_TRACE static inline uint64_t tick_compare_read(void)
+_NO_TRACE static inline uint64_t tick_compare_read(void)
 {
 	uint64_t v;
@@ -136,5 +136,5 @@
  *
  */
-NO_TRACE static inline void tick_compare_write(uint64_t v)
+_NO_TRACE static inline void tick_compare_write(uint64_t v)
 {
 	asm volatile (
@@ -150,5 +150,5 @@
  *
  */
-NO_TRACE static inline uint64_t stick_compare_read(void)
+_NO_TRACE static inline uint64_t stick_compare_read(void)
 {
 	uint64_t v;
@@ -167,5 +167,5 @@
  *
  */
-NO_TRACE static inline void stick_compare_write(uint64_t v)
+_NO_TRACE static inline void stick_compare_write(uint64_t v)
 {
 	asm volatile (
@@ -181,5 +181,5 @@
  *
  */
-NO_TRACE static inline uint64_t tick_read(void)
+_NO_TRACE static inline uint64_t tick_read(void)
 {
 	uint64_t v;
@@ -198,5 +198,5 @@
  *
  */
-NO_TRACE static inline void tick_write(uint64_t v)
+_NO_TRACE static inline void tick_write(uint64_t v)
 {
 	asm volatile (
@@ -212,5 +212,5 @@
  *
  */
-NO_TRACE static inline uint64_t fprs_read(void)
+_NO_TRACE static inline uint64_t fprs_read(void)
 {
 	uint64_t v;
@@ -229,5 +229,5 @@
  *
  */
-NO_TRACE static inline void fprs_write(uint64_t v)
+_NO_TRACE static inline void fprs_write(uint64_t v)
 {
 	asm volatile (
@@ -243,5 +243,5 @@
  *
  */
-NO_TRACE static inline uint64_t softint_read(void)
+_NO_TRACE static inline uint64_t softint_read(void)
 {
 	uint64_t v;
@@ -260,5 +260,5 @@
  *
  */
-NO_TRACE static inline void softint_write(uint64_t v)
+_NO_TRACE static inline void softint_write(uint64_t v)
 {
 	asm volatile (
@@ -276,5 +276,5 @@
  *
  */
-NO_TRACE static inline void clear_softint_write(uint64_t v)
+_NO_TRACE static inline void clear_softint_write(uint64_t v)
 {
 	asm volatile (
@@ -292,5 +292,5 @@
  *
  */
-NO_TRACE static inline void set_softint_write(uint64_t v)
+_NO_TRACE static inline void set_softint_write(uint64_t v)
 {
 	asm volatile (
@@ -309,5 +309,5 @@
  *
  */
-NO_TRACE static inline ipl_t interrupts_enable(void)
+_NO_TRACE static inline ipl_t interrupts_enable(void)
 {
 	pstate_reg_t pstate;
@@ -329,5 +329,5 @@
  *
  */
-NO_TRACE static inline ipl_t interrupts_disable(void)
+_NO_TRACE static inline ipl_t interrupts_disable(void)
 {
 	pstate_reg_t pstate;
@@ -348,5 +348,5 @@
  *
  */
-NO_TRACE static inline void interrupts_restore(ipl_t ipl)
+_NO_TRACE static inline void interrupts_restore(ipl_t ipl)
 {
 	pstate_reg_t pstate;
@@ -364,5 +364,5 @@
  *
  */
-NO_TRACE static inline ipl_t interrupts_read(void)
+_NO_TRACE static inline ipl_t interrupts_read(void)
 {
 	return (ipl_t) pstate_read();
@@ -374,5 +374,5 @@
  *
  */
-NO_TRACE static inline bool interrupts_disabled(void)
+_NO_TRACE static inline bool interrupts_disabled(void)
 {
 	pstate_reg_t pstate;
@@ -389,5 +389,5 @@
  *
  */
-NO_TRACE static inline uintptr_t get_stack_base(void)
+_NO_TRACE static inline uintptr_t get_stack_base(void)
 {
 	uintptr_t unbiased_sp;
@@ -407,5 +407,5 @@
  *
  */
-NO_TRACE static inline uint64_t ver_read(void)
+_NO_TRACE static inline uint64_t ver_read(void)
 {
 	uint64_t v;
@@ -424,5 +424,5 @@
  *
  */
-NO_TRACE static inline uint64_t tpc_read(void)
+_NO_TRACE static inline uint64_t tpc_read(void)
 {
 	uint64_t v;
@@ -441,5 +441,5 @@
  *
  */
-NO_TRACE static inline uint64_t tl_read(void)
+_NO_TRACE static inline uint64_t tl_read(void)
 {
 	uint64_t v;
@@ -458,5 +458,5 @@
  *
  */
-NO_TRACE static inline uint64_t tba_read(void)
+_NO_TRACE static inline uint64_t tba_read(void)
 {
 	uint64_t v;
@@ -475,5 +475,5 @@
  *
  */
-NO_TRACE static inline void tba_write(uint64_t v)
+_NO_TRACE static inline void tba_write(uint64_t v)
 {
 	asm volatile (
@@ -493,5 +493,5 @@
  *
  */
-NO_TRACE static inline uint64_t asi_u64_read(asi_t asi, uintptr_t va)
+_NO_TRACE static inline uint64_t asi_u64_read(asi_t asi, uintptr_t va)
 {
 	uint64_t v;
@@ -514,5 +514,5 @@
  *
  */
-NO_TRACE static inline void asi_u64_write(asi_t asi, uintptr_t va, uint64_t v)
+_NO_TRACE static inline void asi_u64_write(asi_t asi, uintptr_t va, uint64_t v)
 {
 	asm volatile (
@@ -526,5 +526,5 @@
 
 /** Flush all valid register windows to memory. */
-NO_TRACE static inline void flushw(void)
+_NO_TRACE static inline void flushw(void)
 {
 	asm volatile ("flushw\n");
@@ -532,5 +532,5 @@
 
 /** Switch to nucleus by setting TL to 1. */
-NO_TRACE static inline void nucleus_enter(void)
+_NO_TRACE static inline void nucleus_enter(void)
 {
 	asm volatile ("wrpr %g0, 1, %tl\n");
@@ -538,5 +538,5 @@
 
 /** Switch from nucleus by setting TL to 0. */
-NO_TRACE static inline void nucleus_leave(void)
+_NO_TRACE static inline void nucleus_leave(void)
 {
 	asm volatile ("wrpr %g0, %g0, %tl\n");
Index: kernel/arch/sparc64/include/arch/barrier.h
===================================================================
--- kernel/arch/sparc64/include/arch/barrier.h	(revision c477c804d1208352d69c7b069a54d3e3b650ff96)
+++ kernel/arch/sparc64/include/arch/barrier.h	(revision 401415aa8fcb6902c643bf1c028f08be8f7c2d8e)
@@ -39,5 +39,5 @@
 
 /** Flush Instruction pipeline. */
-NO_TRACE static inline void flush_pipeline(void)
+_NO_TRACE static inline void flush_pipeline(void)
 {
 	unsigned long pc;
@@ -62,5 +62,5 @@
 
 /** Memory Barrier instruction. */
-NO_TRACE static inline void membar(void)
+_NO_TRACE static inline void membar(void)
 {
 	asm volatile (
Index: kernel/arch/sparc64/include/arch/cycle.h
===================================================================
--- kernel/arch/sparc64/include/arch/cycle.h	(revision c477c804d1208352d69c7b069a54d3e3b650ff96)
+++ kernel/arch/sparc64/include/arch/cycle.h	(revision 401415aa8fcb6902c643bf1c028f08be8f7c2d8e)
@@ -39,5 +39,5 @@
 #include <trace.h>
 
-NO_TRACE static inline uint64_t get_cycle(void)
+_NO_TRACE static inline uint64_t get_cycle(void)
 {
 	return tick_read();
Index: kernel/arch/sparc64/include/arch/istate.h
===================================================================
--- kernel/arch/sparc64/include/arch/istate.h	(revision c477c804d1208352d69c7b069a54d3e3b650ff96)
+++ kernel/arch/sparc64/include/arch/istate.h	(revision 401415aa8fcb6902c643bf1c028f08be8f7c2d8e)
@@ -51,5 +51,5 @@
 #endif /* KERNEL */
 
-NO_TRACE static inline void istate_set_retaddr(istate_t *istate,
+_NO_TRACE static inline void istate_set_retaddr(istate_t *istate,
     uintptr_t retaddr)
 {
@@ -57,15 +57,15 @@
 }
 
-NO_TRACE static inline int istate_from_uspace(istate_t *istate)
+_NO_TRACE static inline int istate_from_uspace(istate_t *istate)
 {
 	return !(istate->tstate & TSTATE_PRIV_BIT);
 }
 
-NO_TRACE static inline uintptr_t istate_get_pc(istate_t *istate)
+_NO_TRACE static inline uintptr_t istate_get_pc(istate_t *istate)
 {
 	return istate->tpc;
 }
 
-NO_TRACE static inline uintptr_t istate_get_fp(istate_t *istate)
+_NO_TRACE static inline uintptr_t istate_get_fp(istate_t *istate)
 {
 	/* TODO */
Index: kernel/arch/sparc64/include/arch/mm/sun4u/tlb.h
===================================================================
--- kernel/arch/sparc64/include/arch/mm/sun4u/tlb.h	(revision c477c804d1208352d69c7b069a54d3e3b650ff96)
+++ kernel/arch/sparc64/include/arch/mm/sun4u/tlb.h	(revision 401415aa8fcb6902c643bf1c028f08be8f7c2d8e)
@@ -243,5 +243,5 @@
  * Determine the number of entries in the DMMU's small TLB.
  */
-NO_TRACE static inline uint16_t tlb_dsmall_size(void)
+_NO_TRACE static inline uint16_t tlb_dsmall_size(void)
 {
 	return 16;
@@ -251,5 +251,5 @@
  * Determine the number of entries in each DMMU's big TLB.
  */
-NO_TRACE static inline uint16_t tlb_dbig_size(void)
+_NO_TRACE static inline uint16_t tlb_dbig_size(void)
 {
 	return 512;
@@ -259,5 +259,5 @@
  * Determine the number of entries in the IMMU's small TLB.
  */
-NO_TRACE static inline uint16_t tlb_ismall_size(void)
+_NO_TRACE static inline uint16_t tlb_ismall_size(void)
 {
 	return 16;
@@ -267,5 +267,5 @@
  * Determine the number of entries in the IMMU's big TLB.
  */
-NO_TRACE static inline uint16_t tlb_ibig_size(void)
+_NO_TRACE static inline uint16_t tlb_ibig_size(void)
 {
 	if (((ver_reg_t) ver_read()).impl == IMPL_ULTRASPARCIV_PLUS)
@@ -281,5 +281,5 @@
  * @return		Current value of Primary Context Register.
  */
-NO_TRACE static inline uint64_t mmu_primary_context_read(void)
+_NO_TRACE static inline uint64_t mmu_primary_context_read(void)
 {
 	return asi_u64_read(ASI_DMMU, VA_PRIMARY_CONTEXT_REG);
@@ -290,5 +290,5 @@
  * @param v		New value of Primary Context Register.
  */
-NO_TRACE static inline void mmu_primary_context_write(uint64_t v)
+_NO_TRACE static inline void mmu_primary_context_write(uint64_t v)
 {
 	asi_u64_write(ASI_DMMU, VA_PRIMARY_CONTEXT_REG, v);
@@ -300,5 +300,5 @@
  * @return		Current value of Secondary Context Register.
  */
-NO_TRACE static inline uint64_t mmu_secondary_context_read(void)
+_NO_TRACE static inline uint64_t mmu_secondary_context_read(void)
 {
 	return asi_u64_read(ASI_DMMU, VA_SECONDARY_CONTEXT_REG);
@@ -309,5 +309,5 @@
  * @param v		New value of Primary Context Register.
  */
-NO_TRACE static inline void mmu_secondary_context_write(uint64_t v)
+_NO_TRACE static inline void mmu_secondary_context_write(uint64_t v)
 {
 	asi_u64_write(ASI_DMMU, VA_SECONDARY_CONTEXT_REG, v);
@@ -324,5 +324,5 @@
  * 			Register.
  */
-NO_TRACE static inline uint64_t itlb_data_access_read(size_t entry)
+_NO_TRACE static inline uint64_t itlb_data_access_read(size_t entry)
 {
 	itlb_data_access_addr_t reg;
@@ -338,5 +338,5 @@
  * @param value		Value to be written.
  */
-NO_TRACE static inline void itlb_data_access_write(size_t entry, uint64_t value)
+_NO_TRACE static inline void itlb_data_access_write(size_t entry, uint64_t value)
 {
 	itlb_data_access_addr_t reg;
@@ -355,5 +355,5 @@
  * 			Register.
  */
-NO_TRACE static inline uint64_t dtlb_data_access_read(size_t entry)
+_NO_TRACE static inline uint64_t dtlb_data_access_read(size_t entry)
 {
 	dtlb_data_access_addr_t reg;
@@ -369,5 +369,5 @@
  * @param value		Value to be written.
  */
-NO_TRACE static inline void dtlb_data_access_write(size_t entry, uint64_t value)
+_NO_TRACE static inline void dtlb_data_access_write(size_t entry, uint64_t value)
 {
 	dtlb_data_access_addr_t reg;
@@ -385,5 +385,5 @@
  * @return		Current value of specified IMMU TLB Tag Read Register.
  */
-NO_TRACE static inline uint64_t itlb_tag_read_read(size_t entry)
+_NO_TRACE static inline uint64_t itlb_tag_read_read(size_t entry)
 {
 	itlb_tag_read_addr_t tag;
@@ -400,5 +400,5 @@
  * @return		Current value of specified DMMU TLB Tag Read Register.
  */
-NO_TRACE static inline uint64_t dtlb_tag_read_read(size_t entry)
+_NO_TRACE static inline uint64_t dtlb_tag_read_read(size_t entry)
 {
 	dtlb_tag_read_addr_t tag;
@@ -419,5 +419,5 @@
  * 			Register.
  */
-NO_TRACE static inline uint64_t itlb_data_access_read(int tlb, size_t entry)
+_NO_TRACE static inline uint64_t itlb_data_access_read(int tlb, size_t entry)
 {
 	itlb_data_access_addr_t reg;
@@ -434,5 +434,5 @@
  * @param value		Value to be written.
  */
-NO_TRACE static inline void itlb_data_access_write(int tlb, size_t entry,
+_NO_TRACE static inline void itlb_data_access_write(int tlb, size_t entry,
     uint64_t value)
 {
@@ -454,5 +454,5 @@
  * 			Register.
  */
-NO_TRACE static inline uint64_t dtlb_data_access_read(int tlb, size_t entry)
+_NO_TRACE static inline uint64_t dtlb_data_access_read(int tlb, size_t entry)
 {
 	dtlb_data_access_addr_t reg;
@@ -470,5 +470,5 @@
  * @param value		Value to be written.
  */
-NO_TRACE static inline void dtlb_data_access_write(int tlb, size_t entry,
+_NO_TRACE static inline void dtlb_data_access_write(int tlb, size_t entry,
     uint64_t value)
 {
@@ -489,5 +489,5 @@
  * @return		Current value of specified IMMU TLB Tag Read Register.
  */
-NO_TRACE static inline uint64_t itlb_tag_read_read(int tlb, size_t entry)
+_NO_TRACE static inline uint64_t itlb_tag_read_read(int tlb, size_t entry)
 {
 	itlb_tag_read_addr_t tag;
@@ -506,5 +506,5 @@
  * @return		Current value of specified DMMU TLB Tag Read Register.
  */
-NO_TRACE static inline uint64_t dtlb_tag_read_read(int tlb, size_t entry)
+_NO_TRACE static inline uint64_t dtlb_tag_read_read(int tlb, size_t entry)
 {
 	dtlb_tag_read_addr_t tag;
@@ -522,5 +522,5 @@
  * @param v		Value to be written.
  */
-NO_TRACE static inline void itlb_tag_access_write(uint64_t v)
+_NO_TRACE static inline void itlb_tag_access_write(uint64_t v)
 {
 	asi_u64_write(ASI_IMMU, VA_IMMU_TAG_ACCESS, v);
@@ -532,5 +532,5 @@
  * @return		Current value of IMMU TLB Tag Access Register.
  */
-NO_TRACE static inline uint64_t itlb_tag_access_read(void)
+_NO_TRACE static inline uint64_t itlb_tag_access_read(void)
 {
 	return asi_u64_read(ASI_IMMU, VA_IMMU_TAG_ACCESS);
@@ -541,5 +541,5 @@
  * @param v		Value to be written.
  */
-NO_TRACE static inline void dtlb_tag_access_write(uint64_t v)
+_NO_TRACE static inline void dtlb_tag_access_write(uint64_t v)
 {
 	asi_u64_write(ASI_DMMU, VA_DMMU_TAG_ACCESS, v);
@@ -551,5 +551,5 @@
  * @return 		Current value of DMMU TLB Tag Access Register.
  */
-NO_TRACE static inline uint64_t dtlb_tag_access_read(void)
+_NO_TRACE static inline uint64_t dtlb_tag_access_read(void)
 {
 	return asi_u64_read(ASI_DMMU, VA_DMMU_TAG_ACCESS);
@@ -560,5 +560,5 @@
  * @param v		Value to be written.
  */
-NO_TRACE static inline void itlb_data_in_write(uint64_t v)
+_NO_TRACE static inline void itlb_data_in_write(uint64_t v)
 {
 	asi_u64_write(ASI_ITLB_DATA_IN_REG, 0, v);
@@ -570,5 +570,5 @@
  * @param v		Value to be written.
  */
-NO_TRACE static inline void dtlb_data_in_write(uint64_t v)
+_NO_TRACE static inline void dtlb_data_in_write(uint64_t v)
 {
 	asi_u64_write(ASI_DTLB_DATA_IN_REG, 0, v);
@@ -580,5 +580,5 @@
  * @return		Current content of I-SFSR register.
  */
-NO_TRACE static inline uint64_t itlb_sfsr_read(void)
+_NO_TRACE static inline uint64_t itlb_sfsr_read(void)
 {
 	return asi_u64_read(ASI_IMMU, VA_IMMU_SFSR);
@@ -589,5 +589,5 @@
  * @param v		New value of I-SFSR register.
  */
-NO_TRACE static inline void itlb_sfsr_write(uint64_t v)
+_NO_TRACE static inline void itlb_sfsr_write(uint64_t v)
 {
 	asi_u64_write(ASI_IMMU, VA_IMMU_SFSR, v);
@@ -599,5 +599,5 @@
  * @return		Current content of D-SFSR register.
  */
-NO_TRACE static inline uint64_t dtlb_sfsr_read(void)
+_NO_TRACE static inline uint64_t dtlb_sfsr_read(void)
 {
 	return asi_u64_read(ASI_DMMU, VA_DMMU_SFSR);
@@ -608,5 +608,5 @@
  * @param v		New value of D-SFSR register.
  */
-NO_TRACE static inline void dtlb_sfsr_write(uint64_t v)
+_NO_TRACE static inline void dtlb_sfsr_write(uint64_t v)
 {
 	asi_u64_write(ASI_DMMU, VA_DMMU_SFSR, v);
@@ -618,5 +618,5 @@
  * @return		Current content of D-SFAR register.
  */
-NO_TRACE static inline uint64_t dtlb_sfar_read(void)
+_NO_TRACE static inline uint64_t dtlb_sfar_read(void)
 {
 	return asi_u64_read(ASI_DMMU, VA_DMMU_SFAR);
@@ -631,5 +631,5 @@
  * @param page		Address which is on the page to be demapped.
  */
-NO_TRACE static inline void itlb_demap(int type, int context_encoding, uintptr_t page)
+_NO_TRACE static inline void itlb_demap(int type, int context_encoding, uintptr_t page)
 {
 	tlb_demap_addr_t da;
@@ -657,5 +657,5 @@
  * @param page		Address which is on the page to be demapped.
  */
-NO_TRACE static inline void dtlb_demap(int type, int context_encoding, uintptr_t page)
+_NO_TRACE static inline void dtlb_demap(int type, int context_encoding, uintptr_t page)
 {
 	tlb_demap_addr_t da;
Index: kernel/arch/sparc64/include/arch/mm/sun4v/tlb.h
===================================================================
--- kernel/arch/sparc64/include/arch/mm/sun4v/tlb.h	(revision c477c804d1208352d69c7b069a54d3e3b650ff96)
+++ kernel/arch/sparc64/include/arch/mm/sun4v/tlb.h	(revision 401415aa8fcb6902c643bf1c028f08be8f7c2d8e)
@@ -88,5 +88,5 @@
  * @return	Current value of Primary Context Register.
  */
-NO_TRACE static inline uint64_t mmu_primary_context_read(void)
+_NO_TRACE static inline uint64_t mmu_primary_context_read(void)
 {
 	return asi_u64_read(ASI_PRIMARY_CONTEXT_REG, VA_PRIMARY_CONTEXT_REG);
@@ -97,5 +97,5 @@
  * @param v	New value of Primary Context Register.
  */
-NO_TRACE static inline void mmu_primary_context_write(uint64_t v)
+_NO_TRACE static inline void mmu_primary_context_write(uint64_t v)
 {
 	asi_u64_write(ASI_PRIMARY_CONTEXT_REG, VA_PRIMARY_CONTEXT_REG, v);
@@ -106,5 +106,5 @@
  * @return	Current value of Secondary Context Register.
  */
-NO_TRACE static inline uint64_t mmu_secondary_context_read(void)
+_NO_TRACE static inline uint64_t mmu_secondary_context_read(void)
 {
 	return asi_u64_read(ASI_SECONDARY_CONTEXT_REG, VA_SECONDARY_CONTEXT_REG);
@@ -115,5 +115,5 @@
  * @param v	New value of Secondary Context Register.
  */
-NO_TRACE static inline void mmu_secondary_context_write(uint64_t v)
+_NO_TRACE static inline void mmu_secondary_context_write(uint64_t v)
 {
 	asi_u64_write(ASI_SECONDARY_CONTEXT_REG, VA_SECONDARY_CONTEXT_REG, v);
@@ -126,5 +126,5 @@
  * @param mmu_flag	MMU_FLAG_DTLB, MMU_FLAG_ITLB or a combination of both
  */
-NO_TRACE static inline void mmu_demap_ctx(int context, int mmu_flag)
+_NO_TRACE static inline void mmu_demap_ctx(int context, int mmu_flag)
 {
 	__hypercall_fast4(MMU_DEMAP_CTX, 0, 0, context, mmu_flag);
@@ -138,5 +138,5 @@
  * @param mmu_flag	MMU_FLAG_DTLB, MMU_FLAG_ITLB or a combination of both
  */
-NO_TRACE static inline void mmu_demap_page(uintptr_t vaddr, int context, int mmu_flag)
+_NO_TRACE static inline void mmu_demap_page(uintptr_t vaddr, int context, int mmu_flag)
 {
 	__hypercall_fast5(MMU_DEMAP_PAGE, 0, 0, vaddr, context, mmu_flag);
Index: kernel/arch/sparc64/include/arch/sun4u/asm.h
===================================================================
--- kernel/arch/sparc64/include/arch/sun4u/asm.h	(revision c477c804d1208352d69c7b069a54d3e3b650ff96)
+++ kernel/arch/sparc64/include/arch/sun4u/asm.h	(revision 401415aa8fcb6902c643bf1c028f08be8f7c2d8e)
@@ -43,5 +43,5 @@
  *
  */
-NO_TRACE static inline uint64_t ver_read(void)
+_NO_TRACE static inline uint64_t ver_read(void)
 {
 	uint64_t v;
Index: kernel/arch/sparc64/include/arch/sun4u/cpu.h
===================================================================
--- kernel/arch/sparc64/include/arch/sun4u/cpu.h	(revision c477c804d1208352d69c7b069a54d3e3b650ff96)
+++ kernel/arch/sparc64/include/arch/sun4u/cpu.h	(revision 401415aa8fcb6902c643bf1c028f08be8f7c2d8e)
@@ -76,5 +76,5 @@
  *
  */
-NO_TRACE static inline uint32_t read_mid(void)
+_NO_TRACE static inline uint32_t read_mid(void)
 {
 	uint64_t icbus_config = asi_u64_read(ASI_ICBUS_CONFIG, 0);