Changeset 3e828ea in mainline for kernel/genarch
- Timestamp:
- 2019-09-23T12:49:29Z (6 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- 9be2358
- Parents:
- 9259d20 (diff), 1a4ec93f (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the(diff)links above to see all the changes relative to each parent. - git-author:
- Jiri Svoboda <jiri@…> (2019-09-22 12:49:07)
- git-committer:
- Jiri Svoboda <jiri@…> (2019-09-23 12:49:29)
- Location:
- kernel/genarch
- Files:
-
- 4 added
- 1 deleted
- 8 edited
-
Makefile.inc (deleted)
-
include/genarch/drivers/gicv2/gicv2.h (added)
-
include/genarch/drivers/i8259/i8259.h (modified) (2 diffs)
-
include/genarch/drivers/pl011/pl011.h (modified) (2 diffs)
-
include/genarch/drivers/via-cuda/cuda.h (modified) (1 diff)
-
include/genarch/pic/pic_ops.h (added)
-
meson.build (added)
-
src/drivers/gicv2/gicv2.c (added)
-
src/drivers/i8259/i8259.c (modified) (7 diffs)
-
src/drivers/ns16550/ns16550.c (modified) (5 diffs)
-
src/drivers/pl011/pl011.c (modified) (3 diffs)
-
src/mm/as_pt.c (modified) (2 diffs)
-
src/multiboot/multiboot2.c (modified) (1 diff)
Legend:
- Unmodified
- Added
- Removed
-
kernel/genarch/include/genarch/drivers/i8259/i8259.h
r9259d20 r3e828ea 38 38 #include <typedefs.h> 39 39 #include <arch/interrupt.h> 40 41 /* ICW1 bits */ 42 #define PIC_ICW1 (1 << 4) 43 #define PIC_ICW1_NEEDICW4 (1 << 0) 44 45 /* OCW4 bits */ 46 #define PIC_OCW4 (0 << 3) 47 #define PIC_OCW4_NSEOI (1 << 5) 40 #include <genarch/pic/pic_ops.h> 41 #include <stdbool.h> 48 42 49 43 typedef struct { … … 52 46 } __attribute__((packed)) i8259_t; 53 47 54 extern void i8259_init(i8259_t *, i8259_t *, inr_t, unsigned int, unsigned int); 55 extern void pic_enable_irqs(uint16_t); 56 extern void pic_disable_irqs(uint16_t); 57 extern void pic_eoi(void); 48 extern pic_ops_t i8259_pic_ops; 49 50 extern void i8259_init(i8259_t *, i8259_t *, unsigned int); 51 extern void i8259_enable_irqs(uint16_t); 52 extern void i8259_disable_irqs(uint16_t); 53 extern void i8259_eoi(unsigned int); 54 extern bool i8259_is_spurious(unsigned int); 55 extern void i8259_handle_spurious(unsigned int); 58 56 59 57 #endif -
kernel/genarch/include/genarch/drivers/pl011/pl011.h
r9259d20 r3e828ea 38 38 #define KERN_PL011_H_ 39 39 40 #include <ddi/ddi.h> 40 41 #include <ddi/irq.h> 41 42 #include <console/chardev.h> … … 150 151 outdev_t outdev; 151 152 irq_t irq; 153 parea_t parea; 152 154 } pl011_uart_t; 153 155 -
kernel/genarch/include/genarch/drivers/via-cuda/cuda.h
r9259d20 r3e828ea 42 42 43 43 typedef struct { 44 uint8_t b;44 ioport8_t b; 45 45 uint8_t pad0[0x1ff]; 46 46 47 uint8_t a;47 ioport8_t a; 48 48 uint8_t pad1[0x1ff]; 49 49 50 uint8_t dirb;50 ioport8_t dirb; 51 51 uint8_t pad2[0x1ff]; 52 52 53 uint8_t dira;53 ioport8_t dira; 54 54 uint8_t pad3[0x1ff]; 55 55 56 uint8_t t1cl;56 ioport8_t t1cl; 57 57 uint8_t pad4[0x1ff]; 58 58 59 uint8_t t1ch;59 ioport8_t t1ch; 60 60 uint8_t pad5[0x1ff]; 61 61 62 uint8_t t1ll;62 ioport8_t t1ll; 63 63 uint8_t pad6[0x1ff]; 64 64 65 uint8_t t1lh;65 ioport8_t t1lh; 66 66 uint8_t pad7[0x1ff]; 67 67 68 uint8_t t2cl;68 ioport8_t t2cl; 69 69 uint8_t pad8[0x1ff]; 70 70 71 uint8_t t2ch;71 ioport8_t t2ch; 72 72 uint8_t pad9[0x1ff]; 73 73 74 uint8_t sr;74 ioport8_t sr; 75 75 uint8_t pad10[0x1ff]; 76 76 77 uint8_t acr;77 ioport8_t acr; 78 78 uint8_t pad11[0x1ff]; 79 79 80 uint8_t pcr;80 ioport8_t pcr; 81 81 uint8_t pad12[0x1ff]; 82 82 83 uint8_t ifr;83 ioport8_t ifr; 84 84 uint8_t pad13[0x1ff]; 85 85 86 uint8_t ier;86 ioport8_t ier; 87 87 uint8_t pad14[0x1ff]; 88 88 89 uint8_t anh;89 ioport8_t anh; 90 90 uint8_t pad15[0x1ff]; 91 91 } cuda_t; -
kernel/genarch/src/drivers/i8259/i8259.c
r9259d20 r3e828ea 32 32 /** 33 33 * @file 34 * @brief PICdriver.34 * @brief i8259 driver. 35 35 * 36 36 * Programmable Interrupt Controller for UP systems based on i8259 chip. … … 43 43 #include <interrupt.h> 44 44 45 static void pic_spurious(unsigned int n, istate_t *istate); 45 /* ICW1 bits */ 46 #define I8259_ICW1 (1 << 4) 47 #define I8259_ICW1_NEEDICW4 (1 << 0) 48 49 /* OCW3 bits */ 50 #define I8259_OCW3 (1 << 3) 51 #define I8259_OCW3_READ_ISR (3 << 0) 52 53 /* OCW4 bits */ 54 #define I8259_OCW4 (0 << 3) 55 #define I8259_OCW4_NSEOI (1 << 5) 56 57 #define I8259_IRQ_COUNT 8 58 59 #define I8259_IRQ_SLAVE 2 60 61 static const char *i8259_get_name(void); 62 63 pic_ops_t i8259_pic_ops = { 64 .get_name = i8259_get_name, 65 .enable_irqs = i8259_enable_irqs, 66 .disable_irqs = i8259_disable_irqs, 67 .eoi = i8259_eoi, 68 .is_spurious = i8259_is_spurious, 69 .handle_spurious = i8259_handle_spurious 70 }; 46 71 47 72 // XXX: need to change pic_* API to get rid of these … … 49 74 static i8259_t *saved_pic1; 50 75 51 void i8259_init(i8259_t *pic0, i8259_t *pic1, inr_t pic1_irq, 52 unsigned int irq0_int, unsigned int irq8_int) 76 void i8259_init(i8259_t *pic0, i8259_t *pic1, unsigned int irq0_vec) 53 77 { 54 78 saved_pic0 = pic0; … … 56 80 57 81 /* ICW1: this is ICW1, ICW4 to follow */ 58 pio_write_8(&pic0->port1, PIC_ICW1 | PIC_ICW1_NEEDICW4);82 pio_write_8(&pic0->port1, I8259_ICW1 | I8259_ICW1_NEEDICW4); 59 83 60 /* ICW2: IRQ 0 maps to INT irq0_int*/61 pio_write_8(&pic0->port2, irq0_ int);84 /* ICW2: IRQ 0 maps to interrupt vector address irq0_vec */ 85 pio_write_8(&pic0->port2, irq0_vec); 62 86 63 /* ICW3: pic1 using IRQ I RQ_PIC1*/64 pio_write_8(&pic0->port2, 1 << pic1_irq);87 /* ICW3: pic1 using IRQ I8259_IRQ_SLAVE */ 88 pio_write_8(&pic0->port2, 1 << I8259_IRQ_SLAVE); 65 89 66 90 /* ICW4: i8086 mode */ … … 68 92 69 93 /* ICW1: ICW1, ICW4 to follow */ 70 pio_write_8(&pic1->port1, PIC_ICW1 | PIC_ICW1_NEEDICW4);94 pio_write_8(&pic1->port1, I8259_ICW1 | I8259_ICW1_NEEDICW4); 71 95 72 /* ICW2: IRQ 8 maps to INT irq8_int*/73 pio_write_8(&pic1->port2, irq 8_int);96 /* ICW2: IRQ 8 maps to interrupt vector address irq0_vec + 8 */ 97 pio_write_8(&pic1->port2, irq0_vec + I8259_IRQ_COUNT); 74 98 75 /* ICW3: pic1 is known as I RQ_PIC1*/76 pio_write_8(&pic1->port2, pic1_irq);99 /* ICW3: pic1 is known as I8259_IRQ_SLAVE */ 100 pio_write_8(&pic1->port2, I8259_IRQ_SLAVE); 77 101 78 102 /* ICW4: i8086 mode */ 79 103 pio_write_8(&pic1->port2, 1); 80 104 81 /* 82 * Register interrupt handler for the PIC spurious interrupt. 83 * 84 * XXX: This is currently broken. Both IRQ 7 and IRQ 15 can be spurious 85 * or can be actual interrupts. This needs to be detected when 86 * the interrupt happens by inspecting ISR. 87 */ 88 exc_register(irq0_int + 7, "pic_spurious", false, 89 (iroutine_t) pic_spurious); 90 91 pic_disable_irqs(0xffff); /* disable all irq's */ 92 pic_enable_irqs(1 << pic1_irq); /* but enable pic1_irq */ 105 /* disable all irq's */ 106 i8259_disable_irqs(0xffff); 107 /* but enable I8259_IRQ_SLAVE */ 108 i8259_enable_irqs(1 << I8259_IRQ_SLAVE); 93 109 } 94 110 95 void pic_enable_irqs(uint16_t irqmask) 111 const char *i8259_get_name(void) 112 { 113 return "i8259"; 114 } 115 116 void i8259_enable_irqs(uint16_t irqmask) 96 117 { 97 118 uint8_t x; … … 102 123 (uint8_t) (x & (~(irqmask & 0xff)))); 103 124 } 104 if (irqmask >> 8) {125 if (irqmask >> I8259_IRQ_COUNT) { 105 126 x = pio_read_8(&saved_pic1->port2); 106 127 pio_write_8(&saved_pic1->port2, 107 (uint8_t) (x & (~(irqmask >> 8))));128 (uint8_t) (x & (~(irqmask >> I8259_IRQ_COUNT)))); 108 129 } 109 130 } 110 131 111 void pic_disable_irqs(uint16_t irqmask)132 void i8259_disable_irqs(uint16_t irqmask) 112 133 { 113 134 uint8_t x; … … 118 139 (uint8_t) (x | (irqmask & 0xff))); 119 140 } 120 if (irqmask >> 8) {141 if (irqmask >> I8259_IRQ_COUNT) { 121 142 x = pio_read_8(&saved_pic1->port2); 122 pio_write_8(&saved_pic1->port2, (uint8_t) (x | (irqmask >> 8))); 143 pio_write_8(&saved_pic1->port2, 144 (uint8_t) (x | (irqmask >> I8259_IRQ_COUNT))); 123 145 } 124 146 } 125 147 126 void pic_eoi(void)148 void i8259_eoi(unsigned int irq) 127 149 { 128 pio_write_8(&saved_pic0->port1, PIC_OCW4 | PIC_OCW4_NSEOI); 129 pio_write_8(&saved_pic1->port1, PIC_OCW4 | PIC_OCW4_NSEOI); 150 if (irq >= I8259_IRQ_COUNT) 151 pio_write_8(&saved_pic1->port1, I8259_OCW4 | I8259_OCW4_NSEOI); 152 pio_write_8(&saved_pic0->port1, I8259_OCW4 | I8259_OCW4_NSEOI); 130 153 } 131 154 132 void pic_spurious(unsigned int n __attribute__((unused)), istate_t *istate __attribute__((unused)))155 bool i8259_is_spurious(unsigned int irq) 133 156 { 134 #ifdef CONFIG_DEBUG 135 log(LF_ARCH, LVL_DEBUG, "cpu%u: PIC spurious interrupt", CPU->id); 136 #endif 157 pio_write_8(&saved_pic0->port1, I8259_OCW3 | I8259_OCW3_READ_ISR); 158 pio_write_8(&saved_pic1->port1, I8259_OCW3 | I8259_OCW3_READ_ISR); 159 uint8_t isr_lo = pio_read_8(&saved_pic0->port1); 160 uint8_t isr_hi = pio_read_8(&saved_pic1->port1); 161 return !(((isr_hi << I8259_IRQ_COUNT) | isr_lo) & (1 << irq)); 162 } 163 164 void i8259_handle_spurious(unsigned int irq) 165 { 166 /* For spurious IRQs from pic1, we need to isssue an EOI to pic0 */ 167 if (irq >= I8259_IRQ_COUNT) 168 pio_write_8(&saved_pic0->port1, I8259_OCW4 | I8259_OCW4_NSEOI); 137 169 } 138 170 -
kernel/genarch/src/drivers/ns16550/ns16550.c
r9259d20 r3e828ea 39 39 #include <genarch/drivers/ns16550/ns16550.h> 40 40 #include <ddi/irq.h> 41 #include <ddi/ddi.h> 41 42 #include <arch/asm.h> 42 43 #include <console/chardev.h> 43 44 #include <stdlib.h> 45 #include <align.h> 44 46 #include <str.h> 45 47 … … 115 117 116 118 if ((!instance->parea.mapped) || (console_override)) { 119 if (ch == '\n') 120 ns16550_sendb(instance, '\r'); 121 117 122 if (ascii_check(ch)) 118 123 ns16550_sendb(instance, (uint8_t) ch); … … 143 148 * 144 149 */ 145 ns16550_instance_t *ns16550_init(ioport8_t *dev, unsigned reg_shift, inr_t inr, 146 cir_t cir, void *cir_arg, outdev_t **output) 147 { 148 ns16550_instance_t *instance = 149 malloc(sizeof(ns16550_instance_t)); 150 ns16550_instance_t *ns16550_init(ioport8_t *dev_phys, unsigned reg_shift, 151 inr_t inr, cir_t cir, void *cir_arg, outdev_t **output) 152 { 153 size_t size = 6 * (1U << reg_shift); 154 ioport8_t *dev = pio_map((void *) dev_phys, size); 155 156 ns16550_instance_t *instance = malloc(sizeof(ns16550_instance_t)); 150 157 if (instance) { 151 158 instance->ns16550 = dev; … … 158 165 if (!instance->output) { 159 166 free(instance); 167 pio_unmap((void *) dev_phys, (void *) dev, 168 size); 160 169 return NULL; 161 170 } … … 176 185 177 186 ddi_parea_init(&instance->parea); 178 instance->parea.pbase = (uintptr_t) dev; 179 instance->parea.frames = 1; 187 instance->parea.pbase = ALIGN_DOWN((uintptr_t) dev_phys, 188 PAGE_SIZE); 189 instance->parea.frames = ALIGN_UP(size, PAGE_SIZE); 180 190 instance->parea.unpriv = false; 181 191 instance->parea.mapped = false; -
kernel/genarch/src/drivers/pl011/pl011.c
r9259d20 r3e828ea 60 60 pl011_uart_t *uart = dev->data; 61 61 62 if (!ascii_check(ch)) { 62 /* If the userspace owns the console, do not output anything. */ 63 if (uart->parea.mapped && !console_override) 64 return; 65 66 if (!ascii_check(ch)) 63 67 pl011_uart_sendb(uart, U_SPECIAL); 64 }else {68 else { 65 69 if (ch == '\n') 66 70 pl011_uart_sendb(uart, (uint8_t) '\r'); … … 100 104 assert(uart); 101 105 uart->regs = (void *)km_map(addr, sizeof(pl011_uart_regs_t), 102 KM_NATURAL_ALIGNMENT, PAGE_ NOT_CACHEABLE);106 KM_NATURAL_ALIGNMENT, PAGE_WRITE | PAGE_NOT_CACHEABLE); 103 107 assert(uart->regs); 104 108 … … 131 135 uart->irq.instance = uart; 132 136 137 ddi_parea_init(&uart->parea); 138 uart->parea.pbase = addr; 139 uart->parea.frames = 1; 140 uart->parea.unpriv = false; 141 uart->parea.mapped = false; 142 ddi_parea_register(&uart->parea); 143 133 144 return true; 134 145 } -
kernel/genarch/src/mm/as_pt.c
r9259d20 r3e828ea 76 76 PA2KA(frame_alloc(PTL0_FRAMES, FRAME_LOWMEM, PTL0_SIZE - 1)); 77 77 78 if (flags & FLAG_AS_KERNEL)79 memsetb(dst_ptl0, PTL0_SIZE, 0); 80 else{78 memsetb(dst_ptl0, PTL0_SIZE, 0); 79 80 if (!KERNEL_SEPARATE_PTL0 && !(flags & FLAG_AS_KERNEL)) { 81 81 /* 82 82 * Copy the kernel address space portion to new PTL0. … … 93 93 &dst_ptl0[PTL0_INDEX(KERNEL_ADDRESS_SPACE_START)]; 94 94 95 memsetb(dst_ptl0, PTL0_SIZE, 0);96 95 memcpy((void *) dst, (void *) src, 97 96 PTL0_SIZE - (src - (uintptr_t) src_ptl0)); -
kernel/genarch/src/multiboot/multiboot2.c
r9259d20 r3e828ea 65 65 multiboot2_memmap_entry_t *entry = (multiboot2_memmap_entry_t *) 66 66 ((uintptr_t) memmap + sizeof(*memmap)); 67 uint32_t pos = sizeof(*memmap);67 uint32_t pos = offsetof(multiboot2_tag_t, memmap) + sizeof(*memmap); 68 68 69 69 while ((pos < length) && (e820counter < MEMMAP_E820_MAX_RECORDS)) {
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