Index: kernel/arch/amd64/src/fpu_context.c
===================================================================
--- kernel/arch/amd64/src/fpu_context.c	(revision ce60be1a85249a003137d846c99ab01a330a0439)
+++ kernel/arch/amd64/src/fpu_context.c	(revision 3e6a98c595287c43d200d28d97f57755342be117)
@@ -57,4 +57,6 @@
 {
 	/* TODO: Zero all SSE, MMX etc. registers */
+	/* Default value of SCR register is 0x1f80,
+	 * it masks all FPU exceptions*/
 	asm volatile (
 		"fninit\n"
Index: kernel/arch/ia32/src/fpu_context.c
===================================================================
--- kernel/arch/ia32/src/fpu_context.c	(revision ce60be1a85249a003137d846c99ab01a330a0439)
+++ kernel/arch/ia32/src/fpu_context.c	(revision 3e6a98c595287c43d200d28d97f57755342be117)
@@ -37,4 +37,31 @@
 #include <arch.h>
 #include <cpu.h>
+
+
+/** x87 FPU scr values (P3+ MMX2) */
+enum {
+	X87_FLUSH_ZERO_FLAG = (1 << 15),
+	X87_ROUND_CONTROL_MASK = (0x3 << 13),
+	x87_ROUND_TO_NEAREST_EVEN = (0x0 << 13),
+	X87_ROUND_DOWN_TO_NEG_INF = (0x1 << 13),
+	X87_ROUND_UP_TO_POS_INF = (0x2 << 13),
+	X87_ROUND_TO_ZERO = (0x3 << 13),
+	X87_PRECISION_MASK = (1 << 12),
+	X87_UNDERFLOW_MASK = (1 << 11),
+	X87_OVERFLOW_MASK = (1 << 10),
+	X87_ZERO_DIV_MASK = (1 << 9),
+	X87_DENORMAL_OP_MASK = (1 << 8),
+	X87_INVALID_OP_MASK = (1 << 7),
+	X87_DENOM_ZERO_FLAG = (1 << 6),
+	X87_PRECISION_EXC_FLAG = (1 << 5),
+	X87_UNDERFLOW_EXC_FLAG = (1 << 4),
+	X87_OVERFLOW_EXC_FLAG = (1 << 3),
+	X87_ZERO_DIV_EXC_FLAG = (1 << 2),
+	X87_DENORMAL_EXC_FLAG = (1 << 1),
+	X87_INVALID_OP_EXC_FLAG = (1 << 0),
+
+	X87_ALL_MASK = X87_PRECISION_MASK | X87_UNDERFLOW_MASK | X87_OVERFLOW_MASK | X87_ZERO_DIV_MASK | X87_DENORMAL_OP_MASK | X87_INVALID_OP_MASK,
+};
+
 
 typedef void (*fpu_context_function)(fpu_context_t *fctx);
@@ -98,4 +125,5 @@
 }
 
+/** Initialize x87 FPU. Mask all exceptions. */
 void fpu_init()
 {
@@ -111,5 +139,5 @@
 		"ldmxcsr %[help0]\n"
 		: [help0] "+m" (help0), [help1] "+r" (help1)
-		: [magic] "i" (0x1f80)
+		: [magic] "i" (X87_ALL_MASK)
 	);
 }