Changeset 3c79afe in mainline


Ignore:
Timestamp:
2009-03-12T17:54:24Z (16 years ago)
Author:
Martin Decky <martin@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
3a1c048
Parents:
a0e1b48
Message:

update for the new scheme of wiring device drivers to keyboard/serial modules

Location:
kernel/genarch
Files:
6 edited

Legend:

Unmodified
Added
Removed

  • kernel/genarch/include/drivers/i8042/i8042.h

    ra0e1b48 r3c79afe  
    2727 */
    2828
    29 /** @addtogroup genarch 
     29/** @addtogroup genarch
    3030 * @{
    3131 */
    … …  
    4141#include <typedefs.h>
    4242
    43 struct i8042 {
     43typedef struct {
    4444        ioport8_t data;
    4545        uint8_t pad[3];
    4646        ioport8_t status;
    47 } __attribute__ ((packed));
    48 typedef struct i8042 i8042_t;
     47} __attribute__ ((packed)) i8042_t;
    4948
    50 typedef struct i8042_instance {
     49typedef struct {
    5150        devno_t devno;
    5251        irq_t irq;
    5352        i8042_t *i8042;
    54         chardev_t *devout;
     53        indev_t kbrdin;
    5554} i8042_instance_t;
    5655
    57 extern bool i8042_init(i8042_t *, devno_t, inr_t, chardev_t *);
     56extern indev_t *i8042_init(i8042_t *, devno_t, inr_t);
    5857
    5958#endif

  • kernel/genarch/include/drivers/ns16550/ns16550.h

    ra0e1b48 r3c79afe  
    2727 */
    2828
    29 /** @addtogroup genarch 
     29/** @addtogroup genarch
    3030 * @{
    3131 */
    3232/**
    3333 * @file
    34  * @brief       Headers for NS 16550 serial controller.
     34 * @brief Headers for NS 16550 serial controller.
    3535 */
    3636
    … …  
    4242#include <console/chardev.h>
    4343
    44 #define IER_ERBFI       0x01    /** Enable Receive Buffer Full Interrupt. */
     44#define IER_ERBFI  0x01  /** Enable Receive Buffer Full Interrupt. */
    4545
    46 #define LCR_DLAB        0x80    /** Divisor Latch Access bit. */
     46#define LCR_DLAB   0x80  /** Divisor Latch Access bit. */
    4747
    48 #define MCR_OUT2        0x08    /** OUT2. */
     48#define MCR_OUT2   0x08  /** OUT2. */
    4949
    5050/** NS16550 registers. */
    51 struct ns16550 {
    52         ioport8_t rbr;  /**< Receiver Buffer Register. */
    53         ioport8_t ier;  /**< Interrupt Enable Register. */
     51typedef struct {
     52        ioport8_t rbr;      /**< Receiver Buffer Register. */
     53        ioport8_t ier;      /**< Interrupt Enable Register. */
    5454        union {
    55                 ioport8_t iir;  /**< Interrupt Ident Register (read). */
    56                 ioport8_t fcr;  /**< FIFO control register (write). */
     55                ioport8_t iir;  /**< Interrupt Ident Register (read). */
     56                ioport8_t fcr;  /**< FIFO control register (write). */
    5757        } __attribute__ ((packed));
    58         ioport8_t lcr;  /**< Line Control register. */
    59         ioport8_t mcr;  /**< Modem Control Register. */
    60         ioport8_t lsr;  /**< Line Status Register. */
    61 } __attribute__ ((packed));
    62 typedef struct ns16550 ns16550_t;
     58        ioport8_t lcr;      /**< Line Control register. */
     59        ioport8_t mcr;      /**< Modem Control Register. */
     60        ioport8_t lsr;      /**< Line Status Register. */
     61} __attribute__ ((packed)) ns16550_t;
    6362
    6463/** Structure representing the ns16550 device. */
    65 typedef struct ns16550_instance {
     64typedef struct {
    6665        devno_t devno;
    6766        ns16550_t *ns16550;
    6867        irq_t irq;
    69         chardev_t *devout;
     68        indev_t kbrdin;
    7069} ns16550_instance_t;
    7170
    72 extern bool ns16550_init(ns16550_t *, devno_t, inr_t, cir_t, void *,
    73     chardev_t *);
    74 extern irq_ownership_t ns16550_claim(irq_t *);
    75 extern void ns16550_irq_handler(irq_t *);
     71extern indev_t *ns16550_init(ns16550_t *, devno_t, inr_t, cir_t, void *)
    7672
    7773#endif

  • kernel/genarch/include/drivers/z8530/z8530.h

    ra0e1b48 r3c79afe  
    2727 */
    2828
    29 /** @addtogroup genarch 
     29/** @addtogroup genarch
    3030 * @{
    3131 */
    3232/**
    3333 * @file
    34  * @brief       Headers for Zilog 8530 serial controller.
     34 * @brief Headers for Zilog 8530 serial controller.
    3535 */
    3636
    … …  
    4242#include <console/chardev.h>
    4343
    44 #define WR0     0
    45 #define WR1     1
    46 #define WR2     2
    47 #define WR3     3
    48 #define WR4     4
    49 #define WR5     5
    50 #define WR6     6
    51 #define WR7     7
    52 #define WR8     8
    53 #define WR9     9
    54 #define WR10    10
    55 #define WR11    11
    56 #define WR12    12
    57 #define WR13    13
    58 #define WR14    14
    59 #define WR15    15
     44#define WR0   0
     45#define WR1   1
     46#define WR2   2
     47#define WR3   3
     48#define WR4   4
     49#define WR5   5
     50#define WR6   6
     51#define WR7   7
     52#define WR8   8
     53#define WR9   9
     54#define WR10  10
     55#define WR11  11
     56#define WR12  12
     57#define WR13  13
     58#define WR14  14
     59#define WR15  15
    6060
    61 #define RR0     0
    62 #define RR1     1
    63 #define RR2     2
    64 #define RR3     3
    65 #define RR8     8
    66 #define RR10    10
    67 #define RR12    12
    68 #define RR13    13
    69 #define RR14    14
    70 #define RR15    15
     61#define RR0   0
     62#define RR1   1
     63#define RR2   2
     64#define RR3   3
     65#define RR8   8
     66#define RR10  10
     67#define RR12  12
     68#define RR13  13
     69#define RR14  14
     70#define RR15  15
    7171
    7272/** Reset pending TX interrupt. */
    73 #define WR0_TX_IP_RST   (0x5 << 3)
    74 #define WR0_ERR_RST     (0x6 << 3)
     73#define WR0_TX_IP_RST  (0x5 << 3)
     74#define WR0_ERR_RST    (0x6 << 3)
    7575
    7676/** Receive Interrupts Disabled. */
    77 #define WR1_RID         (0x0 << 3)
     77#define WR1_RID     (0x0 << 3)
    7878/** Receive Interrupt on First Character or Special Condition. */
    79 #define WR1_RIFCSC      (0x1 << 3)
     79#define WR1_RIFCSC  (0x1 << 3)
    8080/** Interrupt on All Receive Characters or Special Conditions. */
    81 #define WR1_IARCSC      (0x2 << 3)
     81#define WR1_IARCSC  (0x2 << 3)
    8282/** Receive Interrupt on Special Condition. */
    83 #define WR1_RISC        (0x3 << 3)
     83#define WR1_RISC    (0x3 << 3)
    8484/** Parity Is Special Condition. */
    85 #define WR1_PISC        (0x1 << 2)
     85#define WR1_PISC    (0x1 << 2)
    8686
    8787/** Rx Enable. */
    88 #define WR3_RX_ENABLE   (0x1 << 0)
     88#define WR3_RX_ENABLE  (0x1 << 0)
    8989/** 8-bits per character. */
    90 #define WR3_RX8BITSCH   (0x3 << 6)
     90#define WR3_RX8BITSCH  (0x3 << 6)
    9191
    9292/** Master Interrupt Enable. */
    93 #define WR9_MIE         (0x1 << 3)
     93#define WR9_MIE  (0x1 << 3)
    9494
    9595/** Receive Character Available. */
    96 #define RR0_RCA         (0x1 << 0)
     96#define RR0_RCA  (0x1 << 0)
    9797
    9898/** z8530's registers. */
    99 struct z8530 {
     99typedef struct {
    100100        union {
    101101                ioport8_t ctl_b;
    … …  
    111111        uint8_t pad3;
    112112        ioport8_t data_a;
    113 } __attribute__ ((packed));
    114 typedef struct z8530 z8530_t;
     113} __attribute__ ((packed)) z8530_t;
    115114
    116115/** Structure representing the z8530 device. */
    … …  
    119118        irq_t irq;
    120119        z8530_t *z8530;
    121         chardev_t *devout;
     120        indev_t kbrdin;
    122121} z8530_instance_t;
    123122
    124 extern bool z8530_init(z8530_t *, devno_t, inr_t, cir_t, void *, chardev_t *);
    125 extern irq_ownership_t z8530_claim(irq_t *);
    126 extern void z8530_irq_handler(irq_t *);
     123extern devin_t *z8530_init(z8530_t *, devno_t, inr_t, cir_t, void *);
    127124
    128125#endif

  • kernel/genarch/src/drivers/i8042/i8042.c

    ra0e1b48 r3c79afe  
    2727 */
    2828
    29 /** @addtogroup genarch 
     29/** @addtogroup genarch
    3030 * @{
    3131 */
    3232/**
    3333 * @file
    34  * @brief       i8042 processor driver
     34 * @brief i8042 processor driver
    3535 *
    3636 * It takes care of the i8042 serial communication.
    … …  
    4343#include <mm/slab.h>
    4444
    45 #define i8042_SET_COMMAND       0x60
    46 #define i8042_COMMAND           0x69
     45indev_operations_t kbrdin_ops = {
     46        .poll = NULL
     47};
    4748
    48 #define i8042_BUFFER_FULL_MASK  0x01
    49 #define i8042_WAIT_MASK         0x02
     49#define i8042_SET_COMMAND  0x60
     50#define i8042_COMMAND      0x69
     51
     52#define i8042_BUFFER_FULL_MASK  0x01
     53#define i8042_WAIT_MASK         0x02
    5054
    5155static irq_ownership_t i8042_claim(irq_t *irq)
    … …  
    5357        i8042_instance_t *i8042_instance = irq->instance;
    5458        i8042_t *dev = i8042_instance->i8042;
     59       
    5560        if (pio_read_8(&dev->status) & i8042_BUFFER_FULL_MASK)
    5661                return IRQ_ACCEPT;
    … …  
    6368        i8042_instance_t *instance = irq->instance;
    6469        i8042_t *dev = instance->i8042;
    65 
    66         uint8_t data;
    6770        uint8_t status;
    68                
     71       
    6972        if (((status = pio_read_8(&dev->status)) & i8042_BUFFER_FULL_MASK)) {
    70                 data = pio_read_8(&dev->data);
    71                        
    72                 if (instance->devout)
    73                         chardev_push_character(instance->devout, data);
     73                uint8_t data = pio_read_8(&dev->data);
     74                indev_push_character(&instance->kbrdin, data);
    7475        }
    7576}
    7677
    7778/** Initialize i8042. */
    78 bool
    79 i8042_init(i8042_t *dev, devno_t devno, inr_t inr, chardev_t *devout)
     79indev_t *i8042_init(i8042_t *dev, devno_t devno, inr_t inr)
    8080{
    81         i8042_instance_t *instance;
    82 
    83         instance = malloc(sizeof(i8042_instance_t), FRAME_ATOMIC);
     81        i8042_instance_t *instance
     82            = malloc(sizeof(i8042_instance_t), FRAME_ATOMIC);
    8483        if (!instance)
    85                 return false;
     84                return NULL;
     85       
     86        indev_initialize("i8042", &instance->kbrdin, &kbrdin_ops);
    8687       
    8788        instance->devno = devno;
    8889        instance->i8042 = dev;
    89         instance->devout = devout;
    9090       
    9191        irq_initialize(&instance->irq);
    … …  
    103103                (void) pio_read_8(&dev->data);
    104104       
    105         return true;
     105        return &instance->kbrdin;
    106106}
    107107

  • kernel/genarch/src/drivers/ns16550/ns16550.c

    ra0e1b48 r3c79afe  
    2727 */
    2828
    29 /** @addtogroup genarch 
     29/** @addtogroup genarch
    3030 * @{
    3131 */
    3232/**
    3333 * @file
    34  * @brief       NS 16550 serial controller driver.
     34 * @brief NS 16550 serial controller driver.
    3535 */
    3636
    … …  
    4141#include <mm/slab.h>
    4242
    43 #define LSR_DATA_READY  0x01
     43#define LSR_DATA_READY  0x01
     44
     45indev_operations_t kbrdin_ops = {
     46        .poll = NULL
     47};
     48
     49static irq_ownership_t ns16550_claim(irq_t *irq)
     50{
     51        ns16550_instance_t *instance = irq->instance;
     52        ns16550_t *dev = instance->ns16550;
     53       
     54        if (pio_read_8(&dev->lsr) & LSR_DATA_READY)
     55                return IRQ_ACCEPT;
     56        else
     57                return IRQ_DECLINE;
     58}
     59
     60static void ns16550_irq_handler(irq_t *irq)
     61{
     62        ns16550_instance_t *instance = irq->instance;
     63        ns16550_t *dev = instance->ns16550;
     64       
     65        if (pio_read_8(&dev->lsr) & LSR_DATA_READY) {
     66                uint8_t x = pio_read_8(&dev->rbr);
     67                chardev_push_character(&instance->kbrdin, x);
     68        }
     69}
    4470
    4571/** Initialize ns16550.
    4672 *
    47  * @param dev           Addrress of the beginning of the device in I/O space.
    48  * @param devno         Device number.
    49  * @param inr           Interrupt number.
    50  * @param cir           Clear interrupt function.
    51  * @param cir_arg       First argument to cir.
    52  * @param devout        Output character device.
     73 * @param dev      Addrress of the beginning of the device in I/O space.
     74 * @param devno    Device number.
     75 * @param inr      Interrupt number.
     76 * @param cir      Clear interrupt function.
     77 * @param cir_arg  First argument to cir.
    5378 *
    54  * @return              True on success, false on failure.
     79 * @return Keyboard device pointer or NULL on failure.
     80 *
    5581 */
    56 bool
    57 ns16550_init(ns16550_t *dev, devno_t devno, inr_t inr, cir_t cir, void *cir_arg,
    58     chardev_t *devout)
     82indev_t *ns16550_init(ns16550_t *dev, devno_t devno, inr_t inr, cir_t cir, void *cir_arg)
    5983{
    60         ns16550_instance_t *instance;
     84        ns16550_instance_t *instance
     85            = malloc(sizeof(ns16550_instance_t), FRAME_ATOMIC);
     86        if (!instance)
     87                return NULL;
    6188       
    62         instance = malloc(sizeof(ns16550_instance_t), FRAME_ATOMIC);
    63         if (!instance)
    64                 return false;
    65 
     89        indev_initialize("ns16550", &instance->kbrdin, &kbrdin_ops);
     90       
    6691        instance->devno = devno;
    6792        instance->ns16550 = dev;
    68         instance->devout = devout;
    6993       
    7094        irq_initialize(&instance->irq);
    … …  
    77101        instance->irq.cir_arg = cir_arg;
    78102        irq_register(&instance->irq);
    79 
     103       
    80104        while ((pio_read_8(&dev->lsr) & LSR_DATA_READY))
    81105                (void) pio_read_8(&dev->rbr);
    … …  
    85109        pio_write_8(&dev->mcr, MCR_OUT2);
    86110       
    87         return true;
    88 }
    89 
    90 irq_ownership_t ns16550_claim(irq_t *irq)
    91 {
    92         ns16550_instance_t *instance = irq->instance;
    93         ns16550_t *dev = instance->ns16550;
    94 
    95         if (pio_read_8(&dev->lsr) & LSR_DATA_READY)
    96                 return IRQ_ACCEPT;
    97         else
    98                 return IRQ_DECLINE;
    99 }
    100 
    101 void ns16550_irq_handler(irq_t *irq)
    102 {
    103         ns16550_instance_t *instance = irq->instance;
    104         ns16550_t *dev = instance->ns16550;
    105 
    106         if (pio_read_8(&dev->lsr) & LSR_DATA_READY) {
    107                 uint8_t x;
    108                
    109                 x = pio_read_8(&dev->rbr);
    110                 if (instance->devout)
    111                         chardev_push_character(instance->devout, x);
    112         }
     111        return &instance->kbrdin;
    113112}
    114113

  • kernel/genarch/src/drivers/z8530/z8530.c

    ra0e1b48 r3c79afe  
    2727 */
    2828
    29 /** @addtogroup genarch 
     29/** @addtogroup genarch
    3030 * @{
    3131 */
    3232/**
    3333 * @file
    34  * @brief       Zilog 8530 serial controller driver.
     34 * @brief Zilog 8530 serial controller driver.
    3535 */
    3636
    … …  
    4141#include <mm/slab.h>
    4242
     43indev_operations_t kbrdin_ops = {
     44        .poll = NULL
     45};
     46
    4347static inline void z8530_write(ioport8_t *ctl, uint8_t reg, uint8_t val)
    4448{
    … …  
    4751         * command as their bit 3 is 1.
    4852         */
    49         pio_write_8(ctl, reg);  /* select register */
    50         pio_write_8(ctl, val);  /* write value */
     53        pio_write_8(ctl, reg);  /* Select register */
     54        pio_write_8(ctl, val);  /* Write value */
    5155}
    5256
    … …  
    5761         * command as their bit 3 is 1.
    5862         */
    59         pio_write_8(ctl, reg);  /* select register */
     63        pio_write_8(ctl, reg);   /* Select register */
    6064        return pio_read_8(ctl);
    6165}
    6266
     67static irq_ownership_t z8530_claim(irq_t *irq)
     68{
     69        z8530_instance_t *instance = irq->instance;
     70        z8530_t *dev = instance->z8530;
     71       
     72        if (z8530_read(&dev->ctl_a, RR0) & RR0_RCA)
     73                return IRQ_ACCEPT;
     74        else
     75                return IRQ_DECLINE;
     76}
     77
     78static void z8530_irq_handler(irq_t *irq)
     79{
     80        z8530_instance_t *instance = irq->instance;
     81        z8530_t *dev = instance->z8530;
     82       
     83        if (z8530_read(&dev->ctl_a, RR0) & RR0_RCA) {
     84                uint8_t x = z8530_read(&dev->ctl_a, RR8);
     85                chardev_push_character(&instance->kbrdin, x);
     86        }
     87}
     88
    6389/** Initialize z8530. */
    64 bool
    65 z8530_init(z8530_t *dev, devno_t devno, inr_t inr, cir_t cir, void *cir_arg,
    66     chardev_t *devout)
     90indev_t *z8530_init(z8530_t *dev, devno_t devno, inr_t inr, cir_t cir, void *cir_arg)
    6791{
    68         z8530_instance_t *instance;
    69 
    70         instance = malloc(sizeof(z8530_instance_t), FRAME_ATOMIC);
     92        z8530_instance_t *instance
     93            = malloc(sizeof(z8530_instance_t), FRAME_ATOMIC);
    7194        if (!instance)
    7295                return false;
    73 
     96       
     97        indev_initialize("z8530", &instance->kbrdin, &kbrdin_ops);
     98       
    7499        instance->devno = devno;
    75100        instance->z8530 = dev;
    76         instance->devout = devout;
    77 
     101       
    78102        irq_initialize(&instance->irq);
    79103        instance->irq.devno = devno;
    … …  
    85109        instance->irq.cir_arg = cir_arg;
    86110        irq_register(&instance->irq);
    87 
     111       
    88112        (void) z8530_read(&dev->ctl_a, RR8);
    89 
     113       
    90114        /*
    91115         * Clear any pending TX interrupts or we never manage
    … …  
    93117         */
    94118        z8530_write(&dev->ctl_a, WR0, WR0_TX_IP_RST);
    95 
     119       
    96120        /* interrupt on all characters */
    97121        z8530_write(&dev->ctl_a, WR1, WR1_IARCSC);
    98 
     122       
    99123        /* 8 bits per character and enable receiver */
    100124        z8530_write(&dev->ctl_a, WR3, WR3_RX8BITSCH | WR3_RX_ENABLE);
    … …  
    102126        /* Master Interrupt Enable. */
    103127        z8530_write(&dev->ctl_a, WR9, WR9_MIE);
    104 
    105         return true;
    106 }
    107 
    108 irq_ownership_t z8530_claim(irq_t *irq)
    109 {
    110         z8530_instance_t *instance = irq->instance;
    111         z8530_t *dev = instance->z8530;
    112 
    113         if (z8530_read(&dev->ctl_a, RR0) & RR0_RCA)
    114                 return IRQ_ACCEPT;
    115         else
    116                 return IRQ_DECLINE;
    117 }
    118 
    119 void z8530_irq_handler(irq_t *irq)
    120 {
    121         z8530_instance_t *instance = irq->instance;
    122         z8530_t *dev = instance->z8530;
    123         uint8_t x;
    124 
    125         if (z8530_read(&dev->ctl_a, RR0) & RR0_RCA) {
    126                 x = z8530_read(&dev->ctl_a, RR8);
    127                 if (instance->devout)
    128                         chardev_push_character(instance->devout, x);
    129         }
     128       
     129        return &instance->kbrdin;
    130130}
    131131
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