Changeset 3bacee1 in mainline for uspace/drv/bus/usb/xhci/hw_struct

Timestamp:

2018-04-12T16:27:17Z (8 years ago)

Author:

Jiri Svoboda <jiri@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/fix-logger-deadlock, topic/msim-upgrade, topic/simplify-dev-export

Children:

3cf22f9

Parents:

76d0981d

git-author:

Jiri Svoboda <jiri@…> (2018-04-11 19:25:33)

git-committer:

Jiri Svoboda <jiri@…> (2018-04-12 16:27:17)

Message:

Make ccheck-fix again and commit more good files.

Location:

uspace/drv/bus/usb/xhci/hw_struct

Files:

• regs.h (modified) (1 diff)
• trb.h (modified) (1 diff)

uspace/drv/bus/usb/xhci/hw_struct/regs.h

@@ -235 +235 @@
 #define XHCI_CAP_CIC          hccparams2, 32,  FLAG,  5
 
-static inline unsigned xhci_get_max_spbuf(xhci_cap_regs_t *cap_regs) {
-        return XHCI_REG_RD(cap_regs, XHCI_CAP_MAX_SPBUF_HI) << 5
-                | XHCI_REG_RD(cap_regs, XHCI_CAP_MAX_SPBUF_LO);
+static inline unsigned xhci_get_max_spbuf(xhci_cap_regs_t *cap_regs)
+{
+        return XHCI_REG_RD(cap_regs, XHCI_CAP_MAX_SPBUF_HI) << 5 |
+            XHCI_REG_RD(cap_regs, XHCI_CAP_MAX_SPBUF_LO);
 }
 

uspace/drv/bus/usb/xhci/hw_struct/trb.h

@@ -166 +166 @@
 
         return chain_bit &&
-            (type == XHCI_TRB_TYPE_NORMAL
-            || type == XHCI_TRB_TYPE_DATA_STAGE
-            || type == XHCI_TRB_TYPE_STATUS_STAGE
-            || type == XHCI_TRB_TYPE_ISOCH);
+            (type == XHCI_TRB_TYPE_NORMAL ||
+            type == XHCI_TRB_TYPE_DATA_STAGE ||
+            type == XHCI_TRB_TYPE_STATUS_STAGE ||
+            type == XHCI_TRB_TYPE_ISOCH);
 }