Index: kernel/arch/amd64/include/arch/asm.h
===================================================================
--- kernel/arch/amd64/include/arch/asm.h	(revision 76d0981d8dda2b7d698201a93e0c555e99215ba5)
+++ kernel/arch/amd64/include/arch/asm.h	(revision 3bacee1839e6f355100ab4ea86bb211e9ecf19ed)
@@ -55,7 +55,7 @@
 
 	asm volatile (
-		"andq %%rsp, %[v]\n"
-		: [v] "=r" (v)
-		: "0" (~((uint64_t) STACK_SIZE - 1))
+	    "andq %%rsp, %[v]\n"
+	    : [v] "=r" (v)
+	    : "0" (~((uint64_t) STACK_SIZE - 1))
 	);
 
@@ -66,5 +66,5 @@
 {
 	asm volatile (
-		"hlt\n"
+	    "hlt\n"
 	);
 }
@@ -74,5 +74,5 @@
 	while (true) {
 		asm volatile (
-			"hlt\n"
+		    "hlt\n"
 		);
 	}
@@ -93,7 +93,7 @@
 
 		asm volatile (
-			"inb %w[port], %b[val]\n"
-			: [val] "=a" (val)
-			: [port] "d" (port)
+		    "inb %w[port], %b[val]\n"
+		    : [val] "=a" (val)
+		    : [port] "d" (port)
 		);
 
@@ -117,7 +117,7 @@
 
 		asm volatile (
-			"inw %w[port], %w[val]\n"
-			: [val] "=a" (val)
-			: [port] "d" (port)
+		    "inw %w[port], %w[val]\n"
+		    : [val] "=a" (val)
+		    : [port] "d" (port)
 		);
 
@@ -141,7 +141,7 @@
 
 		asm volatile (
-			"inl %w[port], %[val]\n"
-			: [val] "=a" (val)
-			: [port] "d" (port)
+		    "inl %w[port], %[val]\n"
+		    : [val] "=a" (val)
+		    : [port] "d" (port)
 		);
 
@@ -163,6 +163,6 @@
 	if (port < (ioport8_t *) IO_SPACE_BOUNDARY) {
 		asm volatile (
-			"outb %b[val], %w[port]\n"
-			:: [val] "a" (val), [port] "d" (port)
+		    "outb %b[val], %w[port]\n"
+		    :: [val] "a" (val), [port] "d" (port)
 		);
 	} else
@@ -182,6 +182,6 @@
 	if (port < (ioport16_t *) IO_SPACE_BOUNDARY) {
 		asm volatile (
-			"outw %w[val], %w[port]\n"
-			:: [val] "a" (val), [port] "d" (port)
+		    "outw %w[val], %w[port]\n"
+		    :: [val] "a" (val), [port] "d" (port)
 		);
 	} else
@@ -201,6 +201,6 @@
 	if (port < (ioport32_t *) IO_SPACE_BOUNDARY) {
 		asm volatile (
-			"outl %[val], %w[port]\n"
-			:: [val] "a" (val), [port] "d" (port)
+		    "outl %[val], %w[port]\n"
+		    :: [val] "a" (val), [port] "d" (port)
 		);
 	} else
@@ -213,7 +213,7 @@
 
 	asm volatile (
-		"pushfq\n"
-		"popq %[v]\n"
-		: [v] "=r" (rflags)
+	    "pushfq\n"
+	    "popq %[v]\n"
+	    : [v] "=r" (rflags)
 	);
 
@@ -224,7 +224,7 @@
 {
 	asm volatile (
-		"pushq %[v]\n"
-		"popfq\n"
-		:: [v] "r" (rflags)
+	    "pushq %[v]\n"
+	    "popfq\n"
+	    :: [v] "r" (rflags)
 	);
 }
@@ -300,8 +300,8 @@
 {
 	asm volatile (
-		"wrmsr\n"
-		:: "c" (msr),
-		   "a" ((uint32_t) (value)),
-		   "d" ((uint32_t) (value >> 32))
+	    "wrmsr\n"
+	    :: "c" (msr),
+	      "a" ((uint32_t) (value)),
+	      "d" ((uint32_t) (value >> 32))
 	);
 }
@@ -312,7 +312,7 @@
 
 	asm volatile (
-		"rdmsr\n"
-		: "=a" (ax), "=d" (dx)
-		: "c" (msr)
+	    "rdmsr\n"
+	    : "=a" (ax), "=d" (dx)
+	    : "c" (msr)
 	);
 
@@ -328,6 +328,6 @@
 {
 	asm volatile (
-		"invlpg %[addr]\n"
-		:: [addr] "m" (*((sysarg_t *) addr))
+	    "invlpg %[addr]\n"
+	    :: [addr] "m" (*((sysarg_t *) addr))
 	);
 }
@@ -341,6 +341,6 @@
 {
 	asm volatile (
-		"lgdtq %[gdtr_reg]\n"
-		:: [gdtr_reg] "m" (*gdtr_reg)
+	    "lgdtq %[gdtr_reg]\n"
+	    :: [gdtr_reg] "m" (*gdtr_reg)
 	);
 }
@@ -354,6 +354,6 @@
 {
 	asm volatile (
-		"sgdtq %[gdtr_reg]\n"
-		:: [gdtr_reg] "m" (*gdtr_reg)
+	    "sgdtq %[gdtr_reg]\n"
+	    :: [gdtr_reg] "m" (*gdtr_reg)
 	);
 }
@@ -367,6 +367,6 @@
 {
 	asm volatile (
-		"lidtq %[idtr_reg]\n"
-		:: [idtr_reg] "m" (*idtr_reg));
+	    "lidtq %[idtr_reg]\n"
+	    :: [idtr_reg] "m" (*idtr_reg));
 }
 
@@ -379,6 +379,6 @@
 {
 	asm volatile (
-		"ltr %[sel]"
-		:: [sel] "r" (sel)
+	    "ltr %[sel]"
+	    :: [sel] "r" (sel)
 	);
 }
Index: kernel/arch/amd64/src/amd64.c
===================================================================
--- kernel/arch/amd64/src/amd64.c	(revision 76d0981d8dda2b7d698201a93e0c555e99215ba5)
+++ kernel/arch/amd64/src/amd64.c	(revision 3bacee1839e6f355100ab4ea86bb211e9ecf19ed)
@@ -215,6 +215,6 @@
 	outdev_t **ns16550_out_ptr = NULL;
 #endif
-	ns16550_instance_t *ns16550_instance
-	    = ns16550_init(NS16550_BASE, 0, IRQ_NS16550, NULL, NULL,
+	ns16550_instance_t *ns16550_instance =
+	    ns16550_init(NS16550_BASE, 0, IRQ_NS16550, NULL, NULL,
 	    ns16550_out_ptr);
 	if (ns16550_instance) {
Index: kernel/arch/arm32/include/arch/asm.h
===================================================================
--- kernel/arch/arm32/include/arch/asm.h	(revision 76d0981d8dda2b7d698201a93e0c555e99215ba5)
+++ kernel/arch/arm32/include/arch/asm.h	(revision 3bacee1839e6f355100ab4ea86bb211e9ecf19ed)
@@ -59,5 +59,5 @@
 {
 #ifdef PROCESSOR_ARCH_armv7_a
-	asm volatile ( "wfe" );
+	asm volatile ("wfe");
 #elif defined(PROCESSOR_ARCH_armv6) | defined(PROCESSOR_arm926ej_s) | defined(PROCESSOR_arm920t)
 	WFI_write(0);
@@ -107,7 +107,7 @@
 
 	asm volatile (
-		"and %[v], sp, %[size]\n"
-		: [v] "=r" (v)
-		: [size] "r" (~(STACK_SIZE - 1))
+	    "and %[v], sp, %[size]\n"
+	    : [v] "=r" (v)
+	    : [size] "r" (~(STACK_SIZE - 1))
 	);
 
Index: kernel/arch/arm32/include/arch/security_ext.h
===================================================================
--- kernel/arch/arm32/include/arch/security_ext.h	(revision 76d0981d8dda2b7d698201a93e0c555e99215ba5)
+++ kernel/arch/arm32/include/arch/security_ext.h	(revision 3bacee1839e6f355100ab4ea86bb211e9ecf19ed)
@@ -77,6 +77,6 @@
 static inline bool sec_ext_is_secure(void)
 {
-	return sec_ext_is_implemented()
-	    && (sec_ext_is_monitor_mode() || !(SCR_read() & SCR_NS_FLAG));
+	return sec_ext_is_implemented() &&
+	    (sec_ext_is_monitor_mode() || !(SCR_read() & SCR_NS_FLAG));
 }
 
Index: kernel/arch/arm32/src/mach/raspberrypi/raspberrypi.c
===================================================================
--- kernel/arch/arm32/src/mach/raspberrypi/raspberrypi.c	(revision 76d0981d8dda2b7d698201a93e0c555e99215ba5)
+++ kernel/arch/arm32/src/mach/raspberrypi/raspberrypi.c	(revision 3bacee1839e6f355100ab4ea86bb211e9ecf19ed)
@@ -103,5 +103,5 @@
 	/* Initialize interrupt controller */
 	raspi.irc = (void *) km_map(BCM2835_IRC_ADDR, sizeof(bcm2835_irc_t),
-				    PAGE_NOT_CACHEABLE);
+	    PAGE_NOT_CACHEABLE);
 	assert(raspi.irc);
 	bcm2835_irc_init(raspi.irc);
@@ -109,6 +109,6 @@
 	/* Initialize system timer */
 	raspi.timer = (void *) km_map(BCM2835_TIMER_ADDR,
-				      sizeof(bcm2835_timer_t),
-				      PAGE_NOT_CACHEABLE);
+	    sizeof(bcm2835_timer_t),
+	    PAGE_NOT_CACHEABLE);
 }
 
@@ -129,5 +129,6 @@
 static void raspberrypi_cpu_halt(void)
 {
-	while (true) ;
+	while (true)
+		;
 }
 
@@ -184,5 +185,5 @@
 #ifdef CONFIG_PL011_UART
 	if (pl011_uart_init(&raspi.uart, BCM2835_UART_IRQ,
-			    BCM2835_UART0_BASE_ADDRESS))
+	    BCM2835_UART0_BASE_ADDRESS))
 		stdout_wire(&raspi.uart.outdev);
 #endif
Index: kernel/arch/arm32/src/mm/page.c
===================================================================
--- kernel/arch/arm32/src/mm/page.c	(revision 76d0981d8dda2b7d698201a93e0c555e99215ba5)
+++ kernel/arch/arm32/src/mm/page.c	(revision 3bacee1839e6f355100ab4ea86bb211e9ecf19ed)
@@ -63,5 +63,5 @@
 	for (uintptr_t cur = PHYSMEM_START_ADDR;
 	    cur < min(KA2PA(config.identity_base) +
-	        config.identity_size, config.physmem_end);
+	    config.identity_size, config.physmem_end);
 	    cur += FRAME_SIZE)
 		page_mapping_insert(AS_KERNEL, PA2KA(cur), cur, flags);
Index: kernel/arch/ia32/include/arch/asm.h
===================================================================
--- kernel/arch/ia32/include/arch/asm.h	(revision 76d0981d8dda2b7d698201a93e0c555e99215ba5)
+++ kernel/arch/ia32/include/arch/asm.h	(revision 3bacee1839e6f355100ab4ea86bb211e9ecf19ed)
@@ -52,5 +52,5 @@
 	while (true) {
 		asm volatile (
-			"hlt\n"
+		    "hlt\n"
 		);
 	}
@@ -60,5 +60,5 @@
 {
 	asm volatile (
-		"hlt\n"
+	    "hlt\n"
 	);
 }
@@ -117,6 +117,6 @@
 	if (port < (ioport8_t *) IO_SPACE_BOUNDARY) {
 		asm volatile (
-			"outb %b[val], %w[port]\n"
-			:: [val] "a" (val), [port] "d" (port)
+		    "outb %b[val], %w[port]\n"
+		    :: [val] "a" (val), [port] "d" (port)
 		);
 	} else
@@ -136,6 +136,6 @@
 	if (port < (ioport16_t *) IO_SPACE_BOUNDARY) {
 		asm volatile (
-			"outw %w[val], %w[port]\n"
-			:: [val] "a" (val), [port] "d" (port)
+		    "outw %w[val], %w[port]\n"
+		    :: [val] "a" (val), [port] "d" (port)
 		);
 	} else
@@ -155,6 +155,6 @@
 	if (port < (ioport32_t *) IO_SPACE_BOUNDARY) {
 		asm volatile (
-			"outl %[val], %w[port]\n"
-			:: [val] "a" (val), [port] "d" (port)
+		    "outl %[val], %w[port]\n"
+		    :: [val] "a" (val), [port] "d" (port)
 		);
 	} else
@@ -176,7 +176,7 @@
 
 		asm volatile (
-			"inb %w[port], %b[val]\n"
-			: [val] "=a" (val)
-			: [port] "d" (port)
+		    "inb %w[port], %b[val]\n"
+		    : [val] "=a" (val)
+		    : [port] "d" (port)
 		);
 
@@ -200,7 +200,7 @@
 
 		asm volatile (
-			"inw %w[port], %w[val]\n"
-			: [val] "=a" (val)
-			: [port] "d" (port)
+		    "inw %w[port], %w[val]\n"
+		    : [val] "=a" (val)
+		    : [port] "d" (port)
 		);
 
@@ -224,7 +224,7 @@
 
 		asm volatile (
-			"inl %w[port], %[val]\n"
-			: [val] "=a" (val)
-			: [port] "d" (port)
+		    "inl %w[port], %[val]\n"
+		    : [val] "=a" (val)
+		    : [port] "d" (port)
 		);
 
@@ -239,7 +239,7 @@
 
 	asm volatile (
-		"pushf\n"
-		"popl %[v]\n"
-		: [v] "=r" (eflags)
+	    "pushf\n"
+	    "popl %[v]\n"
+	    : [v] "=r" (eflags)
 	);
 
@@ -250,7 +250,7 @@
 {
 	asm volatile (
-		"pushl %[v]\n"
-		"popf\n"
-		:: [v] "r" (eflags)
+	    "pushl %[v]\n"
+	    "popf\n"
+	    :: [v] "r" (eflags)
 	);
 }
@@ -326,8 +326,8 @@
 {
 	asm volatile (
-		"wrmsr"
-		:: "c" (msr),
-		   "a" ((uint32_t) (value)),
-		   "d" ((uint32_t) (value >> 32))
+	    "wrmsr"
+	    :: "c" (msr),
+	      "a" ((uint32_t) (value)),
+	      "d" ((uint32_t) (value >> 32))
 	);
 }
@@ -338,8 +338,8 @@
 
 	asm volatile (
-		"rdmsr"
-		: "=a" (ax),
-		  "=d" (dx)
-		: "c" (msr)
+	    "rdmsr"
+	    : "=a" (ax),
+	      "=d" (dx)
+	    : "c" (msr)
 	);
 
@@ -362,7 +362,7 @@
 
 	asm volatile (
-		"andl %%esp, %[v]\n"
-		: [v] "=r" (v)
-		: "0" (~(STACK_SIZE - 1))
+	    "andl %%esp, %[v]\n"
+	    : [v] "=r" (v)
+	    : "0" (~(STACK_SIZE - 1))
 	);
 
@@ -378,6 +378,6 @@
 {
 	asm volatile (
-		"invlpg %[addr]\n"
-		:: [addr] "m" (*(sysarg_t *) addr)
+	    "invlpg %[addr]\n"
+	    :: [addr] "m" (*(sysarg_t *) addr)
 	);
 }
@@ -391,6 +391,6 @@
 {
 	asm volatile (
-		"lgdtl %[gdtr_reg]\n"
-		:: [gdtr_reg] "m" (*gdtr_reg)
+	    "lgdtl %[gdtr_reg]\n"
+	    :: [gdtr_reg] "m" (*gdtr_reg)
 	);
 }
@@ -404,6 +404,6 @@
 {
 	asm volatile (
-		"sgdtl %[gdtr_reg]\n"
-		: [gdtr_reg] "=m" (*gdtr_reg)
+	    "sgdtl %[gdtr_reg]\n"
+	    : [gdtr_reg] "=m" (*gdtr_reg)
 	);
 }
@@ -417,6 +417,6 @@
 {
 	asm volatile (
-		"lidtl %[idtr_reg]\n"
-		:: [idtr_reg] "m" (*idtr_reg)
+	    "lidtl %[idtr_reg]\n"
+	    :: [idtr_reg] "m" (*idtr_reg)
 	);
 }
@@ -430,6 +430,6 @@
 {
 	asm volatile (
-		"ltr %[sel]"
-		:: [sel] "r" (sel)
+	    "ltr %[sel]"
+	    :: [sel] "r" (sel)
 	);
 }
@@ -443,6 +443,6 @@
 {
 	asm volatile (
-		"mov %[sel], %%gs"
-		:: [sel] "r" (sel)
+	    "mov %[sel], %%gs"
+	    :: [sel] "r" (sel)
 	);
 }
Index: kernel/arch/ia32/src/cpu/cpu.c
===================================================================
--- kernel/arch/ia32/src/cpu/cpu.c	(revision 76d0981d8dda2b7d698201a93e0c555e99215ba5)
+++ kernel/arch/ia32/src/cpu/cpu.c	(revision 3bacee1839e6f355100ab4ea86bb211e9ecf19ed)
@@ -101,9 +101,9 @@
 	if (CPU->arch.fi.bits.sse) {
 		asm volatile (
-			"mov %%cr4, %[help]\n"
-			"or %[mask], %[help]\n"
-			"mov %[help], %%cr4\n"
-			: [help] "+r" (help)
-			: [mask] "i" (CR4_OSFXSR | CR4_OSXMMEXCPT)
+		    "mov %%cr4, %[help]\n"
+		    "or %[mask], %[help]\n"
+		    "mov %[help], %%cr4\n"
+		    : [help] "+r" (help)
+		    : [mask] "i" (CR4_OSFXSR | CR4_OSXMMEXCPT)
 		);
 	}
@@ -128,7 +128,7 @@
 		 * Check for AMD processor.
 		 */
-		if ((info.cpuid_ebx == AMD_CPUID_EBX)
-		    && (info.cpuid_ecx == AMD_CPUID_ECX)
-		    && (info.cpuid_edx == AMD_CPUID_EDX))
+		if ((info.cpuid_ebx == AMD_CPUID_EBX) &&
+		    (info.cpuid_ecx == AMD_CPUID_ECX) &&
+		    (info.cpuid_edx == AMD_CPUID_EDX))
 			CPU->arch.vendor = VendorAMD;
 
@@ -136,7 +136,7 @@
 		 * Check for Intel processor.
 		 */
-		if ((info.cpuid_ebx == INTEL_CPUID_EBX)
-		    && (info.cpuid_ecx == INTEL_CPUID_ECX)
-		    && (info.cpuid_edx == INTEL_CPUID_EDX))
+		if ((info.cpuid_ebx == INTEL_CPUID_EBX) &&
+		    (info.cpuid_ecx == INTEL_CPUID_ECX) &&
+		    (info.cpuid_edx == INTEL_CPUID_EDX))
 			CPU->arch.vendor = VendorIntel;
 
@@ -148,9 +148,9 @@
 }
 
-void cpu_print_report(cpu_t* cpu)
+void cpu_print_report(cpu_t *cpu)
 {
 	printf("cpu%u: (%s family=%u model=%u stepping=%u apicid=%u) %" PRIu16
-		" MHz\n", cpu->id, vendor_str[cpu->arch.vendor], cpu->arch.family,
-		cpu->arch.model, cpu->arch.stepping, cpu->arch.id, cpu->frequency_mhz);
+	    " MHz\n", cpu->id, vendor_str[cpu->arch.vendor], cpu->arch.family,
+	    cpu->arch.model, cpu->arch.stepping, cpu->arch.id, cpu->frequency_mhz);
 }
 
Index: kernel/arch/ia32/src/ia32.c
===================================================================
--- kernel/arch/ia32/src/ia32.c	(revision 76d0981d8dda2b7d698201a93e0c555e99215ba5)
+++ kernel/arch/ia32/src/ia32.c	(revision 3bacee1839e6f355100ab4ea86bb211e9ecf19ed)
@@ -200,6 +200,6 @@
 	outdev_t **ns16550_out_ptr = NULL;
 #endif
-	ns16550_instance_t *ns16550_instance
-	    = ns16550_init(NS16550_BASE, 0, IRQ_NS16550, NULL, NULL,
+	ns16550_instance_t *ns16550_instance =
+	    ns16550_init(NS16550_BASE, 0, IRQ_NS16550, NULL, NULL,
 	    ns16550_out_ptr);
 	if (ns16550_instance) {
Index: kernel/arch/ia64/src/drivers/ski.c
===================================================================
--- kernel/arch/ia64/src/drivers/ski.c	(revision 76d0981d8dda2b7d698201a93e0c555e99215ba5)
+++ kernel/arch/ia64/src/drivers/ski.c	(revision 3bacee1839e6f355100ab4ea86bb211e9ecf19ed)
@@ -84,11 +84,11 @@
 
 	asm volatile (
-		"mov r15 = %1\n"
-		"break 0x80000;;\n"  /* modifies r8 */
-		"mov %0 = r8;;\n"
-
-		: "=r" (ch)
-		: "i" (SKI_GETCHAR)
-		: "r15", "r8"
+	    "mov r15 = %1\n"
+	    "break 0x80000;;\n"  /* modifies r8 */
+	    "mov %0 = r8;;\n"
+
+	    : "=r" (ch)
+	    : "i" (SKI_GETCHAR)
+	    : "r15", "r8"
 	);
 
@@ -143,9 +143,9 @@
 
 	asm volatile (
-		"mov r15 = %0\n"
-		"break 0x80000\n"
-		:
-		: "i" (SKI_INIT_CONSOLE)
-		: "r15", "r8"
+	    "mov r15 = %0\n"
+	    "break 0x80000\n"
+	    :
+	    : "i" (SKI_INIT_CONSOLE)
+	    : "r15", "r8"
 	);
 
@@ -169,10 +169,10 @@
 {
 	asm volatile (
-		"mov r15 = %[cmd]\n"
-		"mov r32 = %[ch]\n"   /* r32 is in0 */
-		"break 0x80000\n"     /* modifies r8 */
-		:
-		: [cmd] "i" (SKI_PUTCHAR), [ch] "r" (ch)
-		: "r15", "in0", "r8"
+	    "mov r15 = %[cmd]\n"
+	    "mov r32 = %[ch]\n"   /* r32 is in0 */
+	    "break 0x80000\n"     /* modifies r8 */
+	    :
+	    : [cmd] "i" (SKI_PUTCHAR), [ch] "r" (ch)
+	    : "r15", "in0", "r8"
 	);
 }
Index: kernel/arch/ia64/src/ia64.c
===================================================================
--- kernel/arch/ia64/src/ia64.c	(revision 76d0981d8dda2b7d698201a93e0c555e99215ba5)
+++ kernel/arch/ia64/src/ia64.c	(revision 3bacee1839e6f355100ab4ea86bb211e9ecf19ed)
@@ -181,6 +181,6 @@
 
 #ifdef CONFIG_NS16550
-	ns16550_instance_t *ns16550_instance
-	    = ns16550_init(NS16550_BASE, 0, NS16550_IRQ, NULL, NULL,
+	ns16550_instance_t *ns16550_instance =
+	    ns16550_init(NS16550_BASE, 0, NS16550_IRQ, NULL, NULL,
 	    NULL);
 	if (ns16550_instance) {
@@ -253,5 +253,6 @@
 	    (uintptr_t) kernel_uarg->uspace_uarg, psr.value, rsc.value);
 
-	while (true);
+	while (true)
+		;
 }
 
@@ -259,5 +260,6 @@
 {
 	pio_write_8((ioport8_t *)0x64, 0xfe);
-	while (true);
+	while (true)
+		;
 }
 
Index: kernel/arch/ia64/src/interrupt.c
===================================================================
--- kernel/arch/ia64/src/interrupt.c	(revision 76d0981d8dda2b7d698201a93e0c555e99215ba5)
+++ kernel/arch/ia64/src/interrupt.c	(revision 3bacee1839e6f355100ab4ea86bb211e9ecf19ed)
@@ -229,5 +229,5 @@
 {
 	asm volatile (
-		"mov cr.eoi = r0 ;;"
+	    "mov cr.eoi = r0 ;;"
 	);
 }
@@ -245,5 +245,5 @@
 	case INTERRUPT_SPURIOUS:
 #ifdef CONFIG_DEBUG
- 		printf("cpu%d: spurious interrupt\n", CPU->id);
+		printf("cpu%d: spurious interrupt\n", CPU->id);
 #endif
 		break;
Index: kernel/arch/mips32/include/arch/asm.h
===================================================================
--- kernel/arch/mips32/include/arch/asm.h	(revision 76d0981d8dda2b7d698201a93e0c555e99215ba5)
+++ kernel/arch/mips32/include/arch/asm.h	(revision 3bacee1839e6f355100ab4ea86bb211e9ecf19ed)
@@ -57,7 +57,7 @@
 
 	asm volatile (
-		"and %[base], $29, %[mask]\n"
-		: [base] "=r" (base)
-		: [mask] "r" (~(STACK_SIZE - 1))
+	    "and %[base], $29, %[mask]\n"
+	    : [base] "=r" (base)
+	    : [mask] "r" (~(STACK_SIZE - 1))
 	);
 
Index: kernel/arch/mips32/include/arch/mm/tlb.h
===================================================================
--- kernel/arch/mips32/include/arch/mm/tlb.h	(revision 76d0981d8dda2b7d698201a93e0c555e99215ba5)
+++ kernel/arch/mips32/include/arch/mm/tlb.h	(revision 3bacee1839e6f355100ab4ea86bb211e9ecf19ed)
@@ -82,5 +82,5 @@
 		unsigned : 2;       /* zero */
 #endif
-	} __attribute__ ((packed));
+	} __attribute__((packed));
 	uint32_t value;
 } entry_lo_t;
@@ -97,5 +97,5 @@
 		unsigned vpn2 : 19;
 #endif
-	} __attribute__ ((packed));
+	} __attribute__((packed));
 	uint32_t value;
 } entry_hi_t;
@@ -112,5 +112,5 @@
 		unsigned : 7;
 #endif
-	} __attribute__ ((packed));
+	} __attribute__((packed));
 	uint32_t value;
 } page_mask_t;
@@ -127,5 +127,5 @@
 		unsigned p : 1;
 #endif
-	} __attribute__ ((packed));
+	} __attribute__((packed));
 	uint32_t value;
 } tlb_index_t;
Index: kernel/arch/mips32/src/debugger.c
===================================================================
--- kernel/arch/mips32/src/debugger.c	(revision 76d0981d8dda2b7d698201a93e0c555e99215ba5)
+++ kernel/arch/mips32/src/debugger.c	(revision 3bacee1839e6f355100ab4ea86bb211e9ecf19ed)
@@ -102,28 +102,28 @@
 	uint32_t value;
 } jmpinstr[] = {
-	{0xf3ff0000, 0x41000000},  /* BCzF */
-	{0xf3ff0000, 0x41020000},  /* BCzFL */
-	{0xf3ff0000, 0x41010000},  /* BCzT */
-	{0xf3ff0000, 0x41030000},  /* BCzTL */
-	{0xfc000000, 0x10000000},  /* BEQ */
-	{0xfc000000, 0x50000000},  /* BEQL */
-	{0xfc1f0000, 0x04010000},  /* BEQL */
-	{0xfc1f0000, 0x04110000},  /* BGEZAL */
-	{0xfc1f0000, 0x04130000},  /* BGEZALL */
-	{0xfc1f0000, 0x04030000},  /* BGEZL */
-	{0xfc1f0000, 0x1c000000},  /* BGTZ */
-	{0xfc1f0000, 0x5c000000},  /* BGTZL */
-	{0xfc1f0000, 0x18000000},  /* BLEZ */
-	{0xfc1f0000, 0x58000000},  /* BLEZL */
-	{0xfc1f0000, 0x04000000},  /* BLTZ */
-	{0xfc1f0000, 0x04100000},  /* BLTZAL */
-	{0xfc1f0000, 0x04120000},  /* BLTZALL */
-	{0xfc1f0000, 0x04020000},  /* BLTZL */
-	{0xfc000000, 0x14000000},  /* BNE */
-	{0xfc000000, 0x54000000},  /* BNEL */
-	{0xfc000000, 0x08000000},  /* J */
-	{0xfc000000, 0x0c000000},  /* JAL */
-	{0xfc1f07ff, 0x00000009},  /* JALR */
-	{0, 0}                     /* end of table */
+	{ 0xf3ff0000, 0x41000000 },  /* BCzF */
+	{ 0xf3ff0000, 0x41020000 },  /* BCzFL */
+	{ 0xf3ff0000, 0x41010000 },  /* BCzT */
+	{ 0xf3ff0000, 0x41030000 },  /* BCzTL */
+	{ 0xfc000000, 0x10000000 },  /* BEQ */
+	{ 0xfc000000, 0x50000000 },  /* BEQL */
+	{ 0xfc1f0000, 0x04010000 },  /* BEQL */
+	{ 0xfc1f0000, 0x04110000 },  /* BGEZAL */
+	{ 0xfc1f0000, 0x04130000 },  /* BGEZALL */
+	{ 0xfc1f0000, 0x04030000 },  /* BGEZL */
+	{ 0xfc1f0000, 0x1c000000 },  /* BGTZ */
+	{ 0xfc1f0000, 0x5c000000 },  /* BGTZL */
+	{ 0xfc1f0000, 0x18000000 },  /* BLEZ */
+	{ 0xfc1f0000, 0x58000000 },  /* BLEZL */
+	{ 0xfc1f0000, 0x04000000 },  /* BLTZ */
+	{ 0xfc1f0000, 0x04100000 },  /* BLTZAL */
+	{ 0xfc1f0000, 0x04120000 },  /* BLTZALL */
+	{ 0xfc1f0000, 0x04020000 },  /* BLTZL */
+	{ 0xfc000000, 0x14000000 },  /* BNE */
+	{ 0xfc000000, 0x54000000 },  /* BNEL */
+	{ 0xfc000000, 0x08000000 },  /* J */
+	{ 0xfc000000, 0x0c000000 },  /* JAL */
+	{ 0xfc1f07ff, 0x00000009 },  /* JALR */
+	{ 0, 0 }                     /* end of table */
 };
 
@@ -273,6 +273,6 @@
 			    breakpoints[i].counter, (void *) breakpoints[i].address,
 			    ((breakpoints[i].flags & BKPOINT_INPROG) ? "true" :
-			    "false"), ((breakpoints[i].flags & BKPOINT_ONESHOT)
-			    ? "true" : "false"), ((breakpoints[i].flags &
+			    "false"), ((breakpoints[i].flags & BKPOINT_ONESHOT) ?
+			    "true" : "false"), ((breakpoints[i].flags &
 			    BKPOINT_FUNCCALL) ? "true" : "false"), symbol);
 		}
@@ -382,5 +382,5 @@
 		smc_coherence(cur->address);
 
-		if (! (cur->flags & BKPOINT_ONESHOT)) {
+		if (!(cur->flags & BKPOINT_ONESHOT)) {
 			/* Set Breakpoint on next instruction */
 			((uint32_t *)cur->address)[1] = 0x0d;
@@ -422,6 +422,6 @@
 	}
 
-	if ((cur) && (cur->address == fireaddr)
-	    && ((cur->flags & BKPOINT_INPROG))) {
+	if ((cur) && (cur->address == fireaddr) &&
+	    ((cur->flags & BKPOINT_INPROG))) {
 		/* Remove one-shot breakpoint */
 		if ((cur->flags & BKPOINT_ONESHOT))
Index: kernel/arch/mips32/src/mach/msim/msim.c
===================================================================
--- kernel/arch/mips32/src/mach/msim/msim.c	(revision 76d0981d8dda2b7d698201a93e0c555e99215ba5)
+++ kernel/arch/mips32/src/mach/msim/msim.c	(revision 3bacee1839e6f355100ab4ea86bb211e9ecf19ed)
@@ -94,6 +94,6 @@
 	 * interrupts.
 	 */
-	dsrlnin_instance_t *dsrlnin_instance
-	    = dsrlnin_init((dsrlnin_t *) MSIM_KBD_ADDRESS, MSIM_KBD_IRQ);
+	dsrlnin_instance_t *dsrlnin_instance =
+	    dsrlnin_init((dsrlnin_t *) MSIM_KBD_ADDRESS, MSIM_KBD_IRQ);
 	if (dsrlnin_instance) {
 		srln_instance_t *srln_instance = srln_init();
Index: kernel/arch/mips32/src/mm/km.c
===================================================================
--- kernel/arch/mips32/src/mm/km.c	(revision 76d0981d8dda2b7d698201a93e0c555e99215ba5)
+++ kernel/arch/mips32/src/mm/km.c	(revision 3bacee1839e6f355100ab4ea86bb211e9ecf19ed)
@@ -51,6 +51,6 @@
 bool km_is_non_identity_arch(uintptr_t addr)
 {
-	return iswithin(KM_MIPS32_KSSEG_START, KM_MIPS32_KSSEG_SIZE, addr, 1)
-	    || iswithin(KM_MIPS32_KSEG3_START, KM_MIPS32_KSEG3_SIZE, addr, 1);
+	return iswithin(KM_MIPS32_KSSEG_START, KM_MIPS32_KSSEG_SIZE, addr, 1) ||
+	    iswithin(KM_MIPS32_KSEG3_START, KM_MIPS32_KSEG3_SIZE, addr, 1);
 }
 
Index: kernel/arch/ppc32/src/mm/pht.c
===================================================================
--- kernel/arch/ppc32/src/mm/pht.c	(revision 76d0981d8dda2b7d698201a93e0c555e99215ba5)
+++ kernel/arch/ppc32/src/mm/pht.c	(revision 3bacee1839e6f355100ab4ea86bb211e9ecf19ed)
@@ -109,8 +109,8 @@
 	/* Find colliding PTE in PTEG */
 	for (i = 0; i < 8; i++) {
-		if ((phte[base + i].v)
-		    && (phte[base + i].vsid == vsid)
-		    && (phte[base + i].api == api)
-		    && (phte[base + i].h == 0)) {
+		if ((phte[base + i].v) &&
+		    (phte[base + i].vsid == vsid) &&
+		    (phte[base + i].api == api) &&
+		    (phte[base + i].h == 0)) {
 			found = true;
 			break;
@@ -134,8 +134,8 @@
 		/* Find colliding PTE in PTEG */
 		for (i = 0; i < 8; i++) {
-			if ((phte[base2 + i].v)
-			    && (phte[base2 + i].vsid == vsid)
-			    && (phte[base2 + i].api == api)
-			    && (phte[base2 + i].h == 1)) {
+			if ((phte[base2 + i].v) &&
+			    (phte[base2 + i].vsid == vsid) &&
+			    (phte[base2 + i].api == api) &&
+			    (phte[base2 + i].h == 1)) {
 				found = true;
 				base = base2;
Index: kernel/arch/ppc32/src/ppc32.c
===================================================================
--- kernel/arch/ppc32/src/ppc32.c	(revision 76d0981d8dda2b7d698201a93e0c555e99215ba5)
+++ kernel/arch/ppc32/src/ppc32.c	(revision 3bacee1839e6f355100ab4ea86bb211e9ecf19ed)
@@ -185,6 +185,6 @@
 		fb_scanline = *((uint32_t *) prop->value);
 
-	if ((fb_addr) && (fb_width > 0) && (fb_height > 0)
-	    && (fb_scanline > 0) && (visual != VISUAL_UNKNOWN)) {
+	if ((fb_addr) && (fb_width > 0) && (fb_height > 0) &&
+	    (fb_scanline > 0) && (visual != VISUAL_UNKNOWN)) {
 		fb_properties_t fb_prop = {
 			.addr = fb_addr,
@@ -301,5 +301,6 @@
 
 	/* Unreachable */
-	while (true);
+	while (true)
+		;
 }
 
@@ -321,5 +322,6 @@
 {
 	// TODO
-	while (true);
+	while (true)
+		;
 }
 
Index: kernel/arch/sparc64/include/arch/asm.h
===================================================================
--- kernel/arch/sparc64/include/arch/asm.h	(revision 76d0981d8dda2b7d698201a93e0c555e99215ba5)
+++ kernel/arch/sparc64/include/arch/asm.h	(revision 3bacee1839e6f355100ab4ea86bb211e9ecf19ed)
@@ -93,6 +93,6 @@
 
 	asm volatile (
-		"rdpr %%pstate, %[v]\n"
-		: [v] "=r" (v)
+	    "rdpr %%pstate, %[v]\n"
+	    : [v] "=r" (v)
 	);
 
@@ -108,7 +108,7 @@
 {
 	asm volatile (
-		"wrpr %[v], %[zero], %%pstate\n"
-		:: [v] "r" (v),
-		   [zero] "i" (0)
+	    "wrpr %[v], %[zero], %%pstate\n"
+	    :: [v] "r" (v),
+	      [zero] "i" (0)
 	);
 }
@@ -124,6 +124,6 @@
 
 	asm volatile (
-		"rd %%tick_cmpr, %[v]\n"
-		: [v] "=r" (v)
+	    "rd %%tick_cmpr, %[v]\n"
+	    : [v] "=r" (v)
 	);
 
@@ -139,7 +139,7 @@
 {
 	asm volatile (
-		"wr %[v], %[zero], %%tick_cmpr\n"
-		:: [v] "r" (v),
-		   [zero] "i" (0)
+	    "wr %[v], %[zero], %%tick_cmpr\n"
+	    :: [v] "r" (v),
+	      [zero] "i" (0)
 	);
 }
@@ -155,6 +155,6 @@
 
 	asm volatile (
-		"rd %%asr25, %[v]\n"
-		: [v] "=r" (v)
+	    "rd %%asr25, %[v]\n"
+	    : [v] "=r" (v)
 	);
 
@@ -170,7 +170,7 @@
 {
 	asm volatile (
-		"wr %[v], %[zero], %%asr25\n"
-		:: [v] "r" (v),
-		   [zero] "i" (0)
+	    "wr %[v], %[zero], %%asr25\n"
+	    :: [v] "r" (v),
+	      [zero] "i" (0)
 	);
 }
@@ -186,6 +186,6 @@
 
 	asm volatile (
-		"rdpr %%tick, %[v]\n"
-		: [v] "=r" (v)
+	    "rdpr %%tick, %[v]\n"
+	    : [v] "=r" (v)
 	);
 
@@ -201,7 +201,7 @@
 {
 	asm volatile (
-		"wrpr %[v], %[zero], %%tick\n"
-		:: [v] "r" (v),
-		   [zero] "i" (0)
+	    "wrpr %[v], %[zero], %%tick\n"
+	    :: [v] "r" (v),
+	      [zero] "i" (0)
 	);
 }
@@ -217,6 +217,6 @@
 
 	asm volatile (
-		"rd %%fprs, %[v]\n"
-		: [v] "=r" (v)
+	    "rd %%fprs, %[v]\n"
+	    : [v] "=r" (v)
 	);
 
@@ -232,7 +232,7 @@
 {
 	asm volatile (
-		"wr %[v], %[zero], %%fprs\n"
-		:: [v] "r" (v),
-		   [zero] "i" (0)
+	    "wr %[v], %[zero], %%fprs\n"
+	    :: [v] "r" (v),
+	      [zero] "i" (0)
 	);
 }
@@ -248,6 +248,6 @@
 
 	asm volatile (
-		"rd %%softint, %[v]\n"
-		: [v] "=r" (v)
+	    "rd %%softint, %[v]\n"
+	    : [v] "=r" (v)
 	);
 
@@ -263,7 +263,7 @@
 {
 	asm volatile (
-		"wr %[v], %[zero], %%softint\n"
-		:: [v] "r" (v),
-		   [zero] "i" (0)
+	    "wr %[v], %[zero], %%softint\n"
+	    :: [v] "r" (v),
+	      [zero] "i" (0)
 	);
 }
@@ -279,7 +279,7 @@
 {
 	asm volatile (
-		"wr %[v], %[zero], %%clear_softint\n"
-		:: [v] "r" (v),
-		   [zero] "i" (0)
+	    "wr %[v], %[zero], %%clear_softint\n"
+	    :: [v] "r" (v),
+	      [zero] "i" (0)
 	);
 }
@@ -295,7 +295,7 @@
 {
 	asm volatile (
-		"wr %[v], %[zero], %%set_softint\n"
-		:: [v] "r" (v),
-		   [zero] "i" (0)
+	    "wr %[v], %[zero], %%set_softint\n"
+	    :: [v] "r" (v),
+	      [zero] "i" (0)
 	);
 }
@@ -309,5 +309,6 @@
  *
  */
-NO_TRACE static inline ipl_t interrupts_enable(void) {
+NO_TRACE static inline ipl_t interrupts_enable(void)
+{
 	pstate_reg_t pstate;
 	uint64_t value = pstate_read();
@@ -328,5 +329,6 @@
  *
  */
-NO_TRACE static inline ipl_t interrupts_disable(void) {
+NO_TRACE static inline ipl_t interrupts_disable(void)
+{
 	pstate_reg_t pstate;
 	uint64_t value = pstate_read();
@@ -346,5 +348,6 @@
  *
  */
-NO_TRACE static inline void interrupts_restore(ipl_t ipl) {
+NO_TRACE static inline void interrupts_restore(ipl_t ipl)
+{
 	pstate_reg_t pstate;
 
@@ -361,5 +364,6 @@
  *
  */
-NO_TRACE static inline ipl_t interrupts_read(void) {
+NO_TRACE static inline ipl_t interrupts_read(void)
+{
 	return (ipl_t) pstate_read();
 }
@@ -390,7 +394,7 @@
 
 	asm volatile (
-		"add %%sp, %[stack_bias], %[unbiased_sp]\n"
-		: [unbiased_sp] "=r" (unbiased_sp)
-		: [stack_bias] "i" (STACK_BIAS)
+	    "add %%sp, %[stack_bias], %[unbiased_sp]\n"
+	    : [unbiased_sp] "=r" (unbiased_sp)
+	    : [stack_bias] "i" (STACK_BIAS)
 	);
 
@@ -408,6 +412,6 @@
 
 	asm volatile (
-		"rdpr %%ver, %[v]\n"
-		: [v] "=r" (v)
+	    "rdpr %%ver, %[v]\n"
+	    : [v] "=r" (v)
 	);
 
@@ -425,6 +429,6 @@
 
 	asm volatile (
-		"rdpr %%tpc, %[v]\n"
-		: [v] "=r" (v)
+	    "rdpr %%tpc, %[v]\n"
+	    : [v] "=r" (v)
 	);
 
@@ -442,6 +446,6 @@
 
 	asm volatile (
-		"rdpr %%tl, %[v]\n"
-		: [v] "=r" (v)
+	    "rdpr %%tl, %[v]\n"
+	    : [v] "=r" (v)
 	);
 
@@ -459,6 +463,6 @@
 
 	asm volatile (
-		"rdpr %%tba, %[v]\n"
-		: [v] "=r" (v)
+	    "rdpr %%tba, %[v]\n"
+	    : [v] "=r" (v)
 	);
 
@@ -474,7 +478,7 @@
 {
 	asm volatile (
-		"wrpr %[v], %[zero], %%tba\n"
-		:: [v] "r" (v),
-		   [zero] "i" (0)
+	    "wrpr %[v], %[zero], %%tba\n"
+	    :: [v] "r" (v),
+	      [zero] "i" (0)
 	);
 }
@@ -494,8 +498,8 @@
 
 	asm volatile (
-		"ldxa [%[va]] %[asi], %[v]\n"
-		: [v] "=r" (v)
-		: [va] "r" (va),
-		  [asi] "i" ((unsigned int) asi)
+	    "ldxa [%[va]] %[asi], %[v]\n"
+	    : [v] "=r" (v)
+	    : [va] "r" (va),
+	      [asi] "i" ((unsigned int) asi)
 	);
 
@@ -513,9 +517,9 @@
 {
 	asm volatile (
-		"stxa %[v], [%[va]] %[asi]\n"
-		:: [v] "r" (v),
-		   [va] "r" (va),
-		   [asi] "i" ((unsigned int) asi)
-		: "memory"
+	    "stxa %[v], [%[va]] %[asi]\n"
+	    :: [v] "r" (v),
+	      [va] "r" (va),
+	      [asi] "i" ((unsigned int) asi)
+	    : "memory"
 	);
 }
Index: kernel/arch/sparc64/src/fpu_context.c
===================================================================
--- kernel/arch/sparc64/src/fpu_context.c	(revision 76d0981d8dda2b7d698201a93e0c555e99215ba5)
+++ kernel/arch/sparc64/src/fpu_context.c	(revision 3bacee1839e6f355100ab4ea86bb211e9ecf19ed)
@@ -41,24 +41,24 @@
 {
 	asm volatile (
-		"std %%f0, %0\n"
-		"std %%f2, %1\n"
-		"std %%f4, %2\n"
-		"std %%f6, %3\n"
-		"std %%f8, %4\n"
-		"std %%f10, %5\n"
-		"std %%f12, %6\n"
-		"std %%f14, %7\n"
-		"std %%f16, %8\n"
-		"std %%f18, %9\n"
-		"std %%f20, %10\n"
-		"std %%f22, %11\n"
-		"std %%f24, %12\n"
-		"std %%f26, %13\n"
-		"std %%f28, %14\n"
-		"std %%f30, %15\n"
-		: "=m" (fctx->d[0]), "=m" (fctx->d[1]), "=m" (fctx->d[2]), "=m" (fctx->d[3]),
-		  "=m" (fctx->d[4]), "=m" (fctx->d[5]), "=m" (fctx->d[6]), "=m" (fctx->d[7]),
-		  "=m" (fctx->d[8]), "=m" (fctx->d[9]), "=m" (fctx->d[10]), "=m" (fctx->d[11]),
-		  "=m" (fctx->d[12]), "=m" (fctx->d[13]), "=m" (fctx->d[14]), "=m" (fctx->d[15])
+	    "std %%f0, %0\n"
+	    "std %%f2, %1\n"
+	    "std %%f4, %2\n"
+	    "std %%f6, %3\n"
+	    "std %%f8, %4\n"
+	    "std %%f10, %5\n"
+	    "std %%f12, %6\n"
+	    "std %%f14, %7\n"
+	    "std %%f16, %8\n"
+	    "std %%f18, %9\n"
+	    "std %%f20, %10\n"
+	    "std %%f22, %11\n"
+	    "std %%f24, %12\n"
+	    "std %%f26, %13\n"
+	    "std %%f28, %14\n"
+	    "std %%f30, %15\n"
+	    : "=m" (fctx->d[0]), "=m" (fctx->d[1]), "=m" (fctx->d[2]), "=m" (fctx->d[3]),
+	      "=m" (fctx->d[4]), "=m" (fctx->d[5]), "=m" (fctx->d[6]), "=m" (fctx->d[7]),
+	      "=m" (fctx->d[8]), "=m" (fctx->d[9]), "=m" (fctx->d[10]), "=m" (fctx->d[11]),
+	      "=m" (fctx->d[12]), "=m" (fctx->d[13]), "=m" (fctx->d[14]), "=m" (fctx->d[15])
 	);
 
@@ -69,24 +69,24 @@
 
 	asm volatile (
-		"std %%f32, %0\n"
-		"std %%f34, %1\n"
-		"std %%f36, %2\n"
-		"std %%f38, %3\n"
-		"std %%f40, %4\n"
-		"std %%f42, %5\n"
-		"std %%f44, %6\n"
-		"std %%f46, %7\n"
-		"std %%f48, %8\n"
-		"std %%f50, %9\n"
-		"std %%f52, %10\n"
-		"std %%f54, %11\n"
-		"std %%f56, %12\n"
-		"std %%f58, %13\n"
-		"std %%f60, %14\n"
-		"std %%f62, %15\n"
-		: "=m" (fctx->d[16]), "=m" (fctx->d[17]), "=m" (fctx->d[18]), "=m" (fctx->d[19]),
-		  "=m" (fctx->d[20]), "=m" (fctx->d[21]), "=m" (fctx->d[22]), "=m" (fctx->d[23]),
-		  "=m" (fctx->d[24]), "=m" (fctx->d[25]), "=m" (fctx->d[26]), "=m" (fctx->d[27]),
-		  "=m" (fctx->d[28]), "=m" (fctx->d[29]), "=m" (fctx->d[30]), "=m" (fctx->d[31])
+	    "std %%f32, %0\n"
+	    "std %%f34, %1\n"
+	    "std %%f36, %2\n"
+	    "std %%f38, %3\n"
+	    "std %%f40, %4\n"
+	    "std %%f42, %5\n"
+	    "std %%f44, %6\n"
+	    "std %%f46, %7\n"
+	    "std %%f48, %8\n"
+	    "std %%f50, %9\n"
+	    "std %%f52, %10\n"
+	    "std %%f54, %11\n"
+	    "std %%f56, %12\n"
+	    "std %%f58, %13\n"
+	    "std %%f60, %14\n"
+	    "std %%f62, %15\n"
+	    : "=m" (fctx->d[16]), "=m" (fctx->d[17]), "=m" (fctx->d[18]), "=m" (fctx->d[19]),
+	      "=m" (fctx->d[20]), "=m" (fctx->d[21]), "=m" (fctx->d[22]), "=m" (fctx->d[23]),
+	      "=m" (fctx->d[24]), "=m" (fctx->d[25]), "=m" (fctx->d[26]), "=m" (fctx->d[27]),
+	      "=m" (fctx->d[28]), "=m" (fctx->d[29]), "=m" (fctx->d[30]), "=m" (fctx->d[31])
 	);
 
@@ -97,25 +97,25 @@
 {
 	asm volatile (
-		"ldd %0, %%f0\n"
-		"ldd %1, %%f2\n"
-		"ldd %2, %%f4\n"
-		"ldd %3, %%f6\n"
-		"ldd %4, %%f8\n"
-		"ldd %5, %%f10\n"
-		"ldd %6, %%f12\n"
-		"ldd %7, %%f14\n"
-		"ldd %8, %%f16\n"
-		"ldd %9, %%f18\n"
-		"ldd %10, %%f20\n"
-		"ldd %11, %%f22\n"
-		"ldd %12, %%f24\n"
-		"ldd %13, %%f26\n"
-		"ldd %14, %%f28\n"
-		"ldd %15, %%f30\n"
-		:
-		: "m" (fctx->d[0]), "m" (fctx->d[1]), "m" (fctx->d[2]), "m" (fctx->d[3]),
-		  "m" (fctx->d[4]), "m" (fctx->d[5]), "m" (fctx->d[6]), "m" (fctx->d[7]),
-		  "m" (fctx->d[8]), "m" (fctx->d[9]), "m" (fctx->d[10]), "m" (fctx->d[11]),
-		  "m" (fctx->d[12]), "m" (fctx->d[13]), "m" (fctx->d[14]), "m" (fctx->d[15])
+	    "ldd %0, %%f0\n"
+	    "ldd %1, %%f2\n"
+	    "ldd %2, %%f4\n"
+	    "ldd %3, %%f6\n"
+	    "ldd %4, %%f8\n"
+	    "ldd %5, %%f10\n"
+	    "ldd %6, %%f12\n"
+	    "ldd %7, %%f14\n"
+	    "ldd %8, %%f16\n"
+	    "ldd %9, %%f18\n"
+	    "ldd %10, %%f20\n"
+	    "ldd %11, %%f22\n"
+	    "ldd %12, %%f24\n"
+	    "ldd %13, %%f26\n"
+	    "ldd %14, %%f28\n"
+	    "ldd %15, %%f30\n"
+	    :
+	    : "m" (fctx->d[0]), "m" (fctx->d[1]), "m" (fctx->d[2]), "m" (fctx->d[3]),
+	      "m" (fctx->d[4]), "m" (fctx->d[5]), "m" (fctx->d[6]), "m" (fctx->d[7]),
+	      "m" (fctx->d[8]), "m" (fctx->d[9]), "m" (fctx->d[10]), "m" (fctx->d[11]),
+	      "m" (fctx->d[12]), "m" (fctx->d[13]), "m" (fctx->d[14]), "m" (fctx->d[15])
 	);
 
@@ -126,25 +126,25 @@
 
 	asm volatile (
-		"ldd %0, %%f32\n"
-		"ldd %1, %%f34\n"
-		"ldd %2, %%f36\n"
-		"ldd %3, %%f38\n"
-		"ldd %4, %%f40\n"
-		"ldd %5, %%f42\n"
-		"ldd %6, %%f44\n"
-		"ldd %7, %%f46\n"
-		"ldd %8, %%f48\n"
-		"ldd %9, %%f50\n"
-		"ldd %10, %%f52\n"
-		"ldd %11, %%f54\n"
-		"ldd %12, %%f56\n"
-		"ldd %13, %%f58\n"
-		"ldd %14, %%f60\n"
-		"ldd %15, %%f62\n"
-		:
-		: "m" (fctx->d[16]), "m" (fctx->d[17]), "m" (fctx->d[18]), "m" (fctx->d[19]),
-		  "m" (fctx->d[20]), "m" (fctx->d[21]), "m" (fctx->d[22]), "m" (fctx->d[23]),
-		  "m" (fctx->d[24]), "m" (fctx->d[25]), "m" (fctx->d[26]), "m" (fctx->d[27]),
-		  "m" (fctx->d[28]), "m" (fctx->d[29]), "m" (fctx->d[30]), "m" (fctx->d[31])
+	    "ldd %0, %%f32\n"
+	    "ldd %1, %%f34\n"
+	    "ldd %2, %%f36\n"
+	    "ldd %3, %%f38\n"
+	    "ldd %4, %%f40\n"
+	    "ldd %5, %%f42\n"
+	    "ldd %6, %%f44\n"
+	    "ldd %7, %%f46\n"
+	    "ldd %8, %%f48\n"
+	    "ldd %9, %%f50\n"
+	    "ldd %10, %%f52\n"
+	    "ldd %11, %%f54\n"
+	    "ldd %12, %%f56\n"
+	    "ldd %13, %%f58\n"
+	    "ldd %14, %%f60\n"
+	    "ldd %15, %%f62\n"
+	    :
+	    : "m" (fctx->d[16]), "m" (fctx->d[17]), "m" (fctx->d[18]), "m" (fctx->d[19]),
+	      "m" (fctx->d[20]), "m" (fctx->d[21]), "m" (fctx->d[22]), "m" (fctx->d[23]),
+	      "m" (fctx->d[24]), "m" (fctx->d[25]), "m" (fctx->d[26]), "m" (fctx->d[27]),
+	      "m" (fctx->d[28]), "m" (fctx->d[29]), "m" (fctx->d[30]), "m" (fctx->d[31])
 	);
 
Index: kernel/arch/sparc64/src/sun4v/md.c
===================================================================
--- kernel/arch/sparc64/src/sun4v/md.c	(revision 76d0981d8dda2b7d698201a93e0c555e99215ba5)
+++ kernel/arch/sparc64/src/sun4v/md.c	(revision 3bacee1839e6f355100ab4ea86bb211e9ecf19ed)
@@ -62,5 +62,5 @@
 	uint32_t name_blk_sz;		/**< Size in bytes of name block */
 	uint32_t data_blk_sz;		/**< Size in bytes of data block */
-} __attribute__ ((packed)) md_header_t;
+} __attribute__((packed)) md_header_t;
 
 /** machine description element (in the node block) */
@@ -91,5 +91,5 @@
 		uint64_t val;
 	} d;
-} __attribute__ ((packed)) md_element_t;
+} __attribute__((packed)) md_element_t;
 
 /** index of the element within the node block */
@@ -98,5 +98,5 @@
 /** buffer to which the machine description will be saved */
 static uint8_t mach_desc[MD_MAX_SIZE]
-	 __attribute__ ((aligned (16)));
+    __attribute__((aligned(16)));
 
 
@@ -129,5 +129,5 @@
  */
 bool md_get_integer_property(md_node_t node, const char *key,
-	uint64_t *result)
+    uint64_t *result)
 {
 	element_idx_t idx = node;
@@ -152,5 +152,5 @@
  */
 bool md_get_string_property(md_node_t node, const char *key,
-	const char **result)
+    const char **result)
 {
 	md_header_t *md_header = (md_header_t *) mach_desc;