Index: arch/ia32/include/cpu.h
===================================================================
--- arch/ia32/include/cpu.h	(revision b62948369eebdd55f7f90cbe37736fa42c181871)
+++ arch/ia32/include/cpu.h	(revision 3b05862f7b2d26301add7f960fdd87e9c37d6392)
@@ -42,3 +42,6 @@
 };
 
+
+#define CR4_OSFXSR_MASK (1<<9)
+
 #endif
Index: arch/ia32/include/cpuid.h
===================================================================
--- arch/ia32/include/cpuid.h	(revision b62948369eebdd55f7f90cbe37736fa42c181871)
+++ arch/ia32/include/cpuid.h	(revision 3b05862f7b2d26301add7f960fdd87e9c37d6392)
@@ -38,4 +38,32 @@
 	__u32 cpuid_edx;
 } __attribute__ ((packed));
+
+struct __cpuid_extended_feature_info {
+	unsigned sse3 :  1;
+	unsigned      : 31;
+} __attribute__ ((packed));
+
+typedef union cpuid_extended_feature_info 
+{
+	struct __cpuid_extended_feature_info bits;
+	__u32                                word;
+}cpuid_extended_feature_info;
+
+
+struct __cpuid_feature_info {
+	unsigned 			: 23;
+	unsigned mmx  :  1;
+	unsigned fxsr :  1;
+	unsigned sse  :  1;
+	unsigned sse2 :  1;
+	unsigned      :  5;
+} __attribute__ ((packed));
+
+typedef union cpuid_feature_info 
+{
+	struct __cpuid_feature_info bits;
+	__u32                word       ;
+}cpuid_feature_info;
+
 
 static inline __u32 has_cpuid(void)
Index: arch/ia32/include/fpu_context.h
===================================================================
--- arch/ia32/include/fpu_context.h	(revision b62948369eebdd55f7f90cbe37736fa42c181871)
+++ arch/ia32/include/fpu_context.h	(revision 3b05862f7b2d26301add7f960fdd87e9c37d6392)
@@ -35,4 +35,8 @@
 #define FPU_CONTEXT_ALIGN 16
 
+void fpu_fxsr(void);
+void fpu_fsr(void);
+
+
 struct fpu_context {
 	/* TODO: We need malloc that aligns structures on 16-byte boundary */
Index: arch/ia32/include/interrupt.h
===================================================================
--- arch/ia32/include/interrupt.h	(revision b62948369eebdd55f7f90cbe37736fa42c181871)
+++ arch/ia32/include/interrupt.h	(revision 3b05862f7b2d26301add7f960fdd87e9c37d6392)
@@ -85,4 +85,5 @@
 extern void nm_fault(int n, istate_t *istate);
 extern void ss_fault(int n, istate_t *istate);
+extern void simd_fp_exception(int n, istate_t *istate);
 extern void page_fault(int n, istate_t *istate);
 extern void syscall(int n, istate_t *istate);
Index: arch/ia32/src/cpu/cpu.c
===================================================================
--- arch/ia32/src/cpu/cpu.c	(revision b62948369eebdd55f7f90cbe37736fa42c181871)
+++ arch/ia32/src/cpu/cpu.c	(revision 3b05862f7b2d26301add7f960fdd87e9c37d6392)
@@ -93,6 +93,29 @@
 void cpu_arch_init(void)
 {
+	__u32 help=0;
+	
 	CPU->arch.tss = tss_p;
 	CPU->fpu_owner=NULL;
+
+	cpuid_feature_info fi;
+	cpuid_extended_feature_info efi;
+
+	cpu_info_t info;
+	cpuid(1, &info);
+
+	fi.word=info.cpuid_edx;
+	efi.word=info.cpuid_ecx;
+	
+	if(fi.bits.fxsr) 	fpu_fxsr();
+	else fpu_fsr();	
+	
+	if(fi.bits.sse)	asm volatile (
+		"mov %%cr4,%0;\n"
+		"or %1,%0;\n"
+		"mov %0,%%cr4;\n"
+		:"+r"(help)
+		:"i"(CR4_OSFXSR_MASK|(1<<10)) 
+	);
+	
 }
 
Index: arch/ia32/src/fpu_context.c
===================================================================
--- arch/ia32/src/fpu_context.c	(revision b62948369eebdd55f7f90cbe37736fa42c181871)
+++ arch/ia32/src/fpu_context.c	(revision 3b05862f7b2d26301add7f960fdd87e9c37d6392)
@@ -32,5 +32,11 @@
 #include <cpu.h>
 
-void fpu_context_save(fpu_context_t *fctx)
+typedef void (*fpu_context_function)(fpu_context_t *fctx);
+
+static fpu_context_function fpu_save,fpu_restore;
+
+
+
+static void fpu_context_f_save(fpu_context_t *fctx)
 {
 	__asm__ volatile (
@@ -40,6 +46,5 @@
 }
 
-
-void fpu_context_restore(fpu_context_t *fctx)
+static void fpu_context_f_restore(fpu_context_t *fctx)
 {
 	__asm__ volatile (
@@ -49,8 +54,63 @@
 }
 
+static void fpu_context_fx_save(fpu_context_t *fctx)
+{
+	__asm__ volatile (
+		"fxsave %0"
+		: "=m"(*fctx)
+		);
+}
+
+static void fpu_context_fx_restore(fpu_context_t *fctx)
+{
+	__asm__ volatile (
+		"fxrstor %0"
+		: "=m"(*fctx)
+		);
+}
+
+/*
+	Setup using fxsr instruction
+*/
+void fpu_fxsr(void)
+{
+	fpu_save=fpu_context_fx_save;
+	fpu_restore=fpu_context_fx_restore;
+}
+/*
+	Setup using not fxsr instruction
+*/
+void fpu_fsr(void)
+{
+	fpu_save=fpu_context_f_save;
+	fpu_restore=fpu_context_f_restore;
+}
+
+
+
+void fpu_context_save(fpu_context_t *fctx)
+{
+	fpu_save(fctx);
+}
+
+void fpu_context_restore(fpu_context_t *fctx)
+{
+	fpu_restore(fctx);
+}
+
+
+
 void fpu_init()
 {
+	__u32 help0=0,help1=0;
 	__asm__ volatile (
-		"fninit;"
+		"fninit;\n"
+		"stmxcsr %0\n"
+		"mov %0,%1;\n"
+		"or %2,%1;\n"
+		"mov %1,%0;\n"
+		"ldmxcsr %0;\n"
+		:"+m"(help0),"+r"(help1)
+		:"i"(0x1f80)
 	);
 }
Index: arch/ia32/src/interrupt.c
===================================================================
--- arch/ia32/src/interrupt.c	(revision b62948369eebdd55f7f90cbe37736fa42c181871)
+++ arch/ia32/src/interrupt.c	(revision 3b05862f7b2d26301add7f960fdd87e9c37d6392)
@@ -89,4 +89,18 @@
 }
 
+void simd_fp_exception(int n, istate_t *istate)
+{
+
+	PRINT_INFO_ERRCODE(istate);
+	__u32 mxcsr;
+	asm
+	(
+		"stmxcsr %0;\n"
+		:"=m"(mxcsr)
+	);
+	printf("MXCSR: %X\n",(__native)(mxcsr));
+	panic("SIMD FP exception(19)\n");
+}
+
 void nm_fault(int n, istate_t *istate)
 {
Index: arch/ia32/src/pm.c
===================================================================
--- arch/ia32/src/pm.c	(revision b62948369eebdd55f7f90cbe37736fa42c181871)
+++ arch/ia32/src/pm.c	(revision 3b05862f7b2d26301add7f960fdd87e9c37d6392)
@@ -131,4 +131,5 @@
 	exc_register( 7, "nm_fault", (iroutine) nm_fault);
 	exc_register(12, "ss_fault", (iroutine) ss_fault);
+	exc_register(19, "simd_fp", (iroutine) simd_fp_exception);
 }