Changeset 3a0a4d8 in mainline for uspace/drv
- Timestamp:
- 2013-09-12T07:54:05Z (13 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/fix-logger-deadlock, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- 95027b5
- Parents:
- 47f5a77 (diff), 64f3d3b (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the(diff)links above to see all the changes relative to each parent. - Location:
- uspace/drv
- Files:
-
- 17 added
- 19 edited
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audio/sb16/Makefile (added)
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audio/sb16/ddf_log.h (added)
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audio/sb16/dsp.c (added)
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audio/sb16/dsp.h (added)
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audio/sb16/dsp_commands.h (added)
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audio/sb16/main.c (added)
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audio/sb16/mixer.c (added)
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audio/sb16/mixer.h (added)
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audio/sb16/mixer_iface.c (added)
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audio/sb16/pcm_iface.c (added)
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audio/sb16/registers.h (added)
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audio/sb16/sb16.c (added)
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audio/sb16/sb16.h (added)
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audio/sb16/sb16.ma (added)
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block/ahci/ahci.c (modified) (18 diffs)
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bus/isa/i8237.c (modified) (9 diffs)
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bus/isa/i8237.h (modified) (1 diff)
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bus/isa/isa.c (modified) (29 diffs)
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bus/pci/pciintel/pci.c (modified) (13 diffs)
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bus/pci/pciintel/pci.h (modified) (3 diffs)
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bus/usb/uhci/utils/malloc32.h (modified) (2 diffs)
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bus/usb/usbmid/explore.c (modified) (2 diffs)
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bus/usb/usbmid/usbmid.c (modified) (1 diff)
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bus/usb/vhc/transfer.c (modified) (1 diff)
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fb/amdm37x_dispc/amdm37x_dispc.c (modified) (1 diff)
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fb/kfb/port.c (modified) (1 diff)
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infrastructure/root/root.c (modified) (1 diff)
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infrastructure/rootamdm37x/rootamdm37x.c (modified) (5 diffs)
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infrastructure/rootamdm37x/uhh.h (modified) (1 diff)
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infrastructure/rootmalta/Makefile (added)
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infrastructure/rootmalta/rootmalta.c (added)
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infrastructure/rootmalta/rootmalta.ma (added)
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infrastructure/rootpc/rootpc.c (modified) (6 diffs)
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nic/e1k/e1k.c (modified) (15 diffs)
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nic/rtl8139/driver.c (modified) (2 diffs)
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nic/rtl8139/driver.h (modified) (2 diffs)
Legend:
- Unmodified
- Added
- Removed
-
uspace/drv/block/ahci/ahci.c
r47f5a77 r3a0a4d8 119 119 static int ahci_identify_device(sata_dev_t *); 120 120 static int ahci_set_highest_ultra_dma_mode(sata_dev_t *); 121 static int ahci_rb_fpdma(sata_dev_t *, void *, uint64_t);122 static int ahci_wb_fpdma(sata_dev_t *, void *, uint64_t);121 static int ahci_rb_fpdma(sata_dev_t *, uintptr_t, uint64_t); 122 static int ahci_wb_fpdma(sata_dev_t *, uintptr_t, uint64_t); 123 123 124 124 static void ahci_sata_devices_create(ahci_dev_t *, ddf_dev_t *); … … 233 233 sata_dev_t *sata = fun_sata_dev(fun); 234 234 235 void *phys;235 uintptr_t phys; 236 236 void *ibuf; 237 int rc = dmamem_map_anonymous(sata->block_size, AS_AREA_READ | AS_AREA_WRITE,238 0, &phys, (void **)&ibuf);237 int rc = dmamem_map_anonymous(sata->block_size, DMAMEM_4GiB, 238 AS_AREA_READ | AS_AREA_WRITE, 0, &phys, &ibuf); 239 239 if (rc != EOK) { 240 240 ddf_msg(LVL_ERROR, "Cannot allocate read buffer."); … … 276 276 sata_dev_t *sata = fun_sata_dev(fun); 277 277 278 void *phys;278 uintptr_t phys; 279 279 void *ibuf; 280 int rc = dmamem_map_anonymous(sata->block_size, AS_AREA_READ | AS_AREA_WRITE,281 0, &phys, (void **)&ibuf);280 int rc = dmamem_map_anonymous(sata->block_size, DMAMEM_4GiB, 281 AS_AREA_READ | AS_AREA_WRITE, 0, &phys, &ibuf); 282 282 if (rc != EOK) { 283 283 ddf_msg(LVL_ERROR, "Cannot allocate write buffer."); … … 336 336 * 337 337 */ 338 static void ahci_identify_device_cmd(sata_dev_t *sata, void *phys)338 static void ahci_identify_device_cmd(sata_dev_t *sata, uintptr_t phys) 339 339 { 340 340 volatile sata_std_command_frame_t *cmd = … … 381 381 * 382 382 */ 383 static void ahci_identify_packet_device_cmd(sata_dev_t *sata, void *phys)383 static void ahci_identify_packet_device_cmd(sata_dev_t *sata, uintptr_t phys) 384 384 { 385 385 volatile sata_std_command_frame_t *cmd = … … 435 435 } 436 436 437 void *phys;437 uintptr_t phys; 438 438 sata_identify_data_t *idata; 439 439 int rc = dmamem_map_anonymous(SATA_IDENTIFY_DEVICE_BUFFER_LENGTH, 440 AS_AREA_READ | AS_AREA_WRITE, 0, &phys, (void **) &idata); 440 DMAMEM_4GiB, AS_AREA_READ | AS_AREA_WRITE, 0, &phys, 441 (void **) &idata); 441 442 if (rc != EOK) { 442 443 ddf_msg(LVL_ERROR, "Cannot allocate buffer to identify device."); … … 561 562 * 562 563 */ 563 static void ahci_set_mode_cmd(sata_dev_t *sata, void*phys, uint8_t mode)564 static void ahci_set_mode_cmd(sata_dev_t *sata, uintptr_t phys, uint8_t mode) 564 565 { 565 566 volatile sata_std_command_frame_t *cmd = … … 567 568 568 569 cmd->fis_type = SATA_CMD_FIS_TYPE; 569 cmd->c = SATA_CMD_FIS_COMMAND_INDICATOR; 570 cmd->c = SATA_CMD_FIS_COMMAND_INDICATOR; 570 571 cmd->command = 0xef; 571 572 cmd->features = 0x03; … … 628 629 } 629 630 630 void *phys;631 uintptr_t phys; 631 632 sata_identify_data_t *idata; 632 633 int rc = dmamem_map_anonymous(SATA_SET_FEATURE_BUFFER_LENGTH, 633 AS_AREA_READ | AS_AREA_WRITE, 0, &phys, (void **) &idata); 634 DMAMEM_4GiB, AS_AREA_READ | AS_AREA_WRITE, 0, &phys, 635 (void **) &idata); 634 636 if (rc != EOK) { 635 637 ddf_msg(LVL_ERROR, "Cannot allocate buffer for device set mode."); … … 677 679 * 678 680 */ 679 static void ahci_rb_fpdma_cmd(sata_dev_t *sata, void *phys, uint64_t blocknum) 681 static void ahci_rb_fpdma_cmd(sata_dev_t *sata, uintptr_t phys, 682 uint64_t blocknum) 680 683 { 681 684 volatile sata_ncq_command_frame_t *cmd = … … 734 737 * 735 738 */ 736 static int ahci_rb_fpdma(sata_dev_t *sata, void *phys, uint64_t blocknum)739 static int ahci_rb_fpdma(sata_dev_t *sata, uintptr_t phys, uint64_t blocknum) 737 740 { 738 741 if (sata->is_invalid_device) { … … 763 766 * 764 767 */ 765 static void ahci_wb_fpdma_cmd(sata_dev_t *sata, void *phys, uint64_t blocknum) 768 static void ahci_wb_fpdma_cmd(sata_dev_t *sata, uintptr_t phys, 769 uint64_t blocknum) 766 770 { 767 771 volatile sata_ncq_command_frame_t *cmd = … … 821 825 * 822 826 */ 823 static int ahci_wb_fpdma(sata_dev_t *sata, void *phys, uint64_t blocknum)827 static int ahci_wb_fpdma(sata_dev_t *sata, uintptr_t phys, uint64_t blocknum) 824 828 { 825 829 if (sata->is_invalid_device) { … … 933 937 { 934 938 size_t size = 4096; 935 void *phys = NULL;939 uintptr_t phys = 0; 936 940 void *virt_fb = NULL; 937 941 void *virt_cmd = NULL; … … 949 953 950 954 /* Allocate and init retfis structure. */ 951 int rc = dmamem_map_anonymous(size, AS_AREA_READ | AS_AREA_WRITE, 0,952 &phys, &virt_fb);955 int rc = dmamem_map_anonymous(size, DMAMEM_4GiB, 956 AS_AREA_READ | AS_AREA_WRITE, 0, &phys, &virt_fb); 953 957 if (rc != EOK) 954 958 goto error_retfis; … … 959 963 960 964 /* Allocate and init command header structure. */ 961 rc = dmamem_map_anonymous(size, AS_AREA_READ | AS_AREA_WRITE, 0,962 &phys, &virt_cmd);965 rc = dmamem_map_anonymous(size, DMAMEM_4GiB, 966 AS_AREA_READ | AS_AREA_WRITE, 0, &phys, &virt_cmd); 963 967 if (rc != EOK) 964 968 goto error_cmd; … … 970 974 971 975 /* Allocate and init command table structure. */ 972 rc = dmamem_map_anonymous(size, AS_AREA_READ | AS_AREA_WRITE, 0,973 &phys, &virt_table);976 rc = dmamem_map_anonymous(size, DMAMEM_4GiB, 977 AS_AREA_READ | AS_AREA_WRITE, 0, &phys, &virt_table); 974 978 if (rc != EOK) 975 979 goto error_table; … … 1153 1157 ahci->memregs = NULL; 1154 1158 1155 physmem_map(( void *) (size_t) (hw_res_parsed.mem_ranges.ranges[0].address),1159 physmem_map((uintptr_t) (hw_res_parsed.mem_ranges.ranges[0].address), 1156 1160 AHCI_MEMREGS_PAGES_COUNT, AS_AREA_READ | AS_AREA_WRITE, 1157 1161 (void **) &ahci->memregs); -
uspace/drv/bus/isa/i8237.c
r47f5a77 r3a0a4d8 38 38 #include <stdbool.h> 39 39 #include <errno.h> 40 #include <ddi.h> 41 #include <ddf/log.h> 40 42 #include <fibril_synch.h> 41 43 #include <ddi.h> … … 198 200 .channels = { 199 201 /* The first chip 8-bit */ 200 { 201 (uint8_t *) 0x00,202 (uint8_t *) 0x01,203 (uint8_t *) 0x87,204 (uint8_t *) 0x0a,205 (uint8_t *) 0x0b,206 (uint8_t *) 0x0c,207 }, 208 { 209 (uint8_t *) 0x02,210 (uint8_t *) 0x03,211 (uint8_t *) 0x83,212 (uint8_t *) 0x0a,213 (uint8_t *) 0x0b,214 (uint8_t *) 0x0c,215 }, 216 { 217 (uint8_t *) 0x04,218 (uint8_t *) 0x05,219 (uint8_t *) 0x81,220 (uint8_t *) 0x0a,221 (uint8_t *) 0x0b,222 (uint8_t *) 0x0c,223 }, 224 { 225 (uint8_t *) 0x06,226 (uint8_t *) 0x07,227 (uint8_t *) 0x82,228 (uint8_t *) 0x0a,229 (uint8_t *) 0x0b,230 (uint8_t *) 0x0c,202 { /* Channel 0 - Unusable*/ 203 .offset_reg_address = (uint8_t *) 0x00, 204 .size_reg_address = (uint8_t *) 0x01, 205 .page_reg_address = (uint8_t *) 0x87, 206 .single_mask_address = (uint8_t *) 0x0a, 207 .mode_address = (uint8_t *) 0x0b, 208 .flip_flop_address = (uint8_t *) 0x0c, 209 }, 210 { /* Channel 1 */ 211 .offset_reg_address = (uint8_t *) 0x02, 212 .size_reg_address = (uint8_t *) 0x03, 213 .page_reg_address = (uint8_t *) 0x83, 214 .single_mask_address = (uint8_t *) 0x0a, 215 .mode_address = (uint8_t *) 0x0b, 216 .flip_flop_address = (uint8_t *) 0x0c, 217 }, 218 { /* Channel 2 */ 219 .offset_reg_address = (uint8_t *) 0x04, 220 .size_reg_address = (uint8_t *) 0x05, 221 .page_reg_address = (uint8_t *) 0x81, 222 .single_mask_address = (uint8_t *) 0x0a, 223 .mode_address = (uint8_t *) 0x0b, 224 .flip_flop_address = (uint8_t *) 0x0c, 225 }, 226 { /* Channel 3 */ 227 .offset_reg_address = (uint8_t *) 0x06, 228 .size_reg_address = (uint8_t *) 0x07, 229 .page_reg_address = (uint8_t *) 0x82, 230 .single_mask_address = (uint8_t *) 0x0a, 231 .mode_address = (uint8_t *) 0x0b, 232 .flip_flop_address = (uint8_t *) 0x0c, 231 233 }, 232 234 233 235 /* The second chip 16-bit */ 234 { 235 (uint8_t *) 0xc0,236 (uint8_t *) 0xc2,237 (uint8_t *) 0x8f,238 (uint8_t *) 0xd4,239 (uint8_t *) 0xd6,240 (uint8_t *) 0xd8,241 }, 242 { 243 (uint8_t *) 0xc4,244 (uint8_t *) 0xc6,245 (uint8_t *) 0x8b,246 (uint8_t *) 0xd4,247 (uint8_t *) 0xd6,248 (uint8_t *) 0xd8,249 }, 250 { 251 (uint8_t *) 0xc8,252 (uint8_t *) 0xca,253 (uint8_t *) 0x89,254 (uint8_t *) 0xd4,255 (uint8_t *) 0xd6,256 (uint8_t *) 0xd8,257 }, 258 { 259 (uint8_t *) 0xcc,260 (uint8_t *) 0xce,261 (uint8_t *) 0x8a,262 (uint8_t *) 0xd4,263 (uint8_t *) 0xd6,264 (uint8_t *) 0xd8,236 { /* Channel 4 - Unusable */ 237 .offset_reg_address = (uint8_t *) 0xc0, 238 .size_reg_address = (uint8_t *) 0xc2, 239 .page_reg_address = (uint8_t *) 0x8f, 240 .single_mask_address = (uint8_t *) 0xd4, 241 .mode_address = (uint8_t *) 0xd6, 242 .flip_flop_address = (uint8_t *) 0xd8, 243 }, 244 { /* Channel 5 */ 245 .offset_reg_address = (uint8_t *) 0xc4, 246 .size_reg_address = (uint8_t *) 0xc6, 247 .page_reg_address = (uint8_t *) 0x8b, 248 .single_mask_address = (uint8_t *) 0xd4, 249 .mode_address = (uint8_t *) 0xd6, 250 .flip_flop_address = (uint8_t *) 0xd8, 251 }, 252 { /* Channel 6 */ 253 .offset_reg_address = (uint8_t *) 0xc8, 254 .size_reg_address = (uint8_t *) 0xca, 255 .page_reg_address = (uint8_t *) 0x89, 256 .single_mask_address = (uint8_t *) 0xd4, 257 .mode_address = (uint8_t *) 0xd6, 258 .flip_flop_address = (uint8_t *) 0xd8, 259 }, 260 { /* Channel 7 */ 261 .offset_reg_address = (uint8_t *) 0xcc, 262 .size_reg_address = (uint8_t *) 0xce, 263 .page_reg_address = (uint8_t *) 0x8a, 264 .single_mask_address = (uint8_t *) 0xd4, 265 .mode_address = (uint8_t *) 0xd6, 266 .flip_flop_address = (uint8_t *) 0xd8, 265 267 }, 266 268 }, … … 272 274 }; 273 275 274 /* Initialize I/O access to DMA controller I/O ports.276 /** Initialize I/O access to DMA controller I/O ports. 275 277 * 276 278 * @param controller DMA Controller structure to initialize. … … 304 306 305 307 return EOK; 308 } 309 310 /** Helper function. Channels 4,5,6, and 7 are 8 bit DMA. 311 * @pram channel DMA channel. 312 * @reutrn True, if channel is 4,5,6, or 7, false otherwise. 313 */ 314 static inline bool is_dma16(unsigned channel) 315 { 316 return (channel >= 4) && (channel < 8); 317 } 318 319 /** Helper function. Channels 0,1,2, and 3 are 8 bit DMA. 320 * @pram channel DMA channel. 321 * @reutrn True, if channel is 0,1,2, or 3, false otherwise. 322 */ 323 static inline bool is_dma8(unsigned channel) 324 { 325 return (channel < 4); 306 326 } 307 327 … … 320 340 * 321 341 * @return Error code. 322 * 323 */ 324 int dma_setup_channel(unsigned int channel, uint32_t pa, uint16_t size, 342 */ 343 int dma_channel_setup(unsigned int channel, uint32_t pa, uint32_t size, 325 344 uint8_t mode) 326 345 { 346 if (!is_dma8(channel) && !is_dma16(channel)) 347 return ENOENT; 348 327 349 if ((channel == 0) || (channel == 4)) 328 350 return ENOTSUP; 329 330 if (channel > 7)331 return ENOENT;332 351 333 352 /* DMA is limited to 24bit addresses. */ … … 336 355 337 356 /* 8 bit channels use only 4 bits from the page register. */ 338 if ((channel > 0) && (channel < 4) && (pa >= (1 << 20))) 357 if (is_dma8(channel) && (pa >= (1 << 20))) 358 return EINVAL; 359 360 /* Buffers cannot cross 64K page boundaries */ 361 if ((pa & 0xffff0000) != ((pa + size - 1) & 0xffff0000)) 339 362 return EINVAL; 340 363 … … 352 375 ddf_msg(LVL_DEBUG, "Unspoiled address %#" PRIx32 " (size %" PRIu16 ")", 353 376 pa, size); 354 if ( channel > 4) {377 if (is_dma16(channel)) { 355 378 /* Size must be aligned to 16 bits */ 356 379 if ((size & 1) != 0) { … … 358 381 return EINVAL; 359 382 } 360 383 /* Size is in 2byte words */ 361 384 size >>= 1; 362 363 385 /* Address is fun: lower 16 bits need to be shifted by 1 */ 364 386 pa = ((pa & 0xffff) >> 1) | (pa & 0xff0000); … … 426 448 } 427 449 450 /** Query remaining buffer size. 451 * 452 * @param channel DMA Channel 1, 2, 3 for 8 bit transfers, 453 * 5, 6, 7 for 16 bit. 454 * @param size Place to store number of bytes pending in the assigned buffer. 455 * 456 * @return Error code. 457 */ 458 int dma_channel_remain(unsigned channel, size_t *size) 459 { 460 assert(size); 461 if (!is_dma8(channel) && !is_dma16(channel)) 462 return ENOENT; 463 464 if ((channel == 0) || (channel == 4)) 465 return ENOTSUP; 466 467 fibril_mutex_lock(&guard); 468 if (!controller_8237.initialized) { 469 fibril_mutex_unlock(&guard); 470 return EIO; 471 } 472 473 const dma_channel_t dma_channel = controller_8237.channels[channel]; 474 /* Get size - reset flip-flop */ 475 pio_write_8(dma_channel.flip_flop_address, 0); 476 477 /* Low byte */ 478 const uint8_t value_low = pio_read_8(dma_channel.size_reg_address); 479 ddf_msg(LVL_DEBUG2, "Read size low byte: %p:%x.", 480 dma_channel.size_reg_address, value_low); 481 482 /* High byte */ 483 const uint8_t value_high = pio_read_8(dma_channel.size_reg_address); 484 ddf_msg(LVL_DEBUG2, "Read size high byte: %p:%x.", 485 dma_channel.size_reg_address, value_high); 486 fibril_mutex_unlock(&guard); 487 488 uint16_t remain = (value_high << 8 | value_low) ; 489 /* 16 bit DMA size is in words, 490 * the upper bits are bogus for 16bit transfers so we need to get 491 * rid of them. Using limited type works well.*/ 492 if (is_dma16(channel)) 493 remain <<= 1; 494 *size = is_dma16(channel) ? remain + 2: remain + 1; 495 return EOK; 496 } 428 497 /** 429 498 * @} -
uspace/drv/bus/isa/i8237.h
r47f5a77 r3a0a4d8 38 38 #define DRV_BUS_ISA_I8237_H 39 39 40 extern int dma_setup_channel(unsigned int, uint32_t, uint16_t, uint8_t); 40 extern int dma_channel_setup(unsigned, uint32_t, uint32_t, uint8_t); 41 extern int dma_channel_remain(unsigned, size_t *); 41 42 42 43 #endif -
uspace/drv/bus/isa/isa.c
r47f5a77 r3a0a4d8 67 67 68 68 #include <device/hw_res.h> 69 #include <device/pio_window.h> 69 70 70 71 #include "i8237.h" … … 79 80 ddf_dev_t *dev; 80 81 ddf_fun_t *fctl; 82 pio_window_t pio_win; 81 83 list_t functions; 82 84 } isa_bus_t; … … 85 87 fibril_mutex_t mutex; 86 88 ddf_fun_t *fnode; 89 hw_resource_t resources[ISA_MAX_HW_RES]; 87 90 hw_resource_list_t hw_resources; 88 91 link_t bus_link; … … 103 106 static hw_resource_list_t *isa_get_fun_resources(ddf_fun_t *fnode) 104 107 { 105 isa_fun_t * fun= isa_fun(fnode);106 assert( fun != NULL);107 108 return & fun->hw_resources;109 } 110 111 static bool isa_ enable_fun_interrupt(ddf_fun_t *fnode)108 isa_fun_t *isa = isa_fun(fnode); 109 assert(isa); 110 111 return &isa->hw_resources; 112 } 113 114 static bool isa_fun_enable_interrupt(ddf_fun_t *fnode) 112 115 { 113 116 /* This is an old ugly way, copied from pci driver */ 114 117 assert(fnode); 115 isa_fun_t *fun = isa_fun(fnode); 118 isa_fun_t *isa = isa_fun(fnode); 119 assert(isa); 116 120 117 121 sysarg_t apic; … … 129 133 return false; 130 134 131 const hw_resource_list_t *res = & fun->hw_resources;135 const hw_resource_list_t *res = &isa->hw_resources; 132 136 assert(res); 133 137 for (size_t i = 0; i < res->count; ++i) { … … 151 155 } 152 156 153 static int isa_ dma_channel_fun_setup(ddf_fun_t *fnode,154 unsigned int channel, uint32_t pa, uint 16_t size, uint8_t mode)157 static int isa_fun_setup_dma(ddf_fun_t *fnode, 158 unsigned int channel, uint32_t pa, uint32_t size, uint8_t mode) 155 159 { 156 160 assert(fnode); 157 isa_fun_t *fun = isa_fun(fnode); 158 const hw_resource_list_t *res = &fun->hw_resources; 161 isa_fun_t *isa = isa_fun(fnode); 162 assert(isa); 163 const hw_resource_list_t *res = &isa->hw_resources; 159 164 assert(res); 160 161 const unsigned int ch = channel; 165 162 166 for (size_t i = 0; i < res->count; ++i) { 167 /* Check for assigned channel */ 163 168 if (((res->resources[i].type == DMA_CHANNEL_16) && 164 (res->resources[i].res.dma_channel.dma16 == ch )) ||169 (res->resources[i].res.dma_channel.dma16 == channel)) || 165 170 ((res->resources[i].type == DMA_CHANNEL_8) && 166 (res->resources[i].res.dma_channel.dma8 == ch))) { 167 return dma_setup_channel(channel, pa, size, mode); 168 } 169 } 170 171 (res->resources[i].res.dma_channel.dma8 == channel))) { 172 return dma_channel_setup(channel, pa, size, mode); 173 } 174 } 175 176 return EINVAL; 177 } 178 179 static int isa_fun_remain_dma(ddf_fun_t *fnode, 180 unsigned channel, size_t *size) 181 { 182 assert(size); 183 assert(fnode); 184 isa_fun_t *isa = isa_fun(fnode); 185 assert(isa); 186 const hw_resource_list_t *res = &isa->hw_resources; 187 assert(res); 188 189 for (size_t i = 0; i < res->count; ++i) { 190 /* Check for assigned channel */ 191 if (((res->resources[i].type == DMA_CHANNEL_16) && 192 (res->resources[i].res.dma_channel.dma16 == channel)) || 193 ((res->resources[i].type == DMA_CHANNEL_8) && 194 (res->resources[i].res.dma_channel.dma8 == channel))) { 195 return dma_channel_remain(channel, size); 196 } 197 } 198 171 199 return EINVAL; 172 200 } … … 174 202 static hw_res_ops_t isa_fun_hw_res_ops = { 175 203 .get_resource_list = isa_get_fun_resources, 176 .enable_interrupt = isa_enable_fun_interrupt, 177 .dma_channel_setup = isa_dma_channel_fun_setup, 204 .enable_interrupt = isa_fun_enable_interrupt, 205 .dma_channel_setup = isa_fun_setup_dma, 206 .dma_channel_remain = isa_fun_remain_dma, 178 207 }; 179 208 180 static ddf_dev_ops_t isa_fun_ops; 209 static ddf_dev_ops_t isa_fun_ops= { 210 .interfaces[HW_RES_DEV_IFACE] = &isa_fun_hw_res_ops, 211 }; 181 212 182 213 static int isa_dev_add(ddf_dev_t *dev); … … 212 243 213 244 fibril_mutex_initialize(&fun->mutex); 245 fun->hw_resources.resources = fun->resources; 246 214 247 fun->fnode = fnode; 215 248 return fun; … … 270 303 { 271 304 char *line = str; 305 *next = NULL; 272 306 273 307 if (str == NULL) { 274 *next = NULL;275 308 return NULL; 276 309 } … … 282 315 if (*str != '\0') { 283 316 *next = str + 1; 284 } else {285 *next = NULL;286 317 } 287 318 … … 310 341 /* Get the name part of the rest of the line. */ 311 342 strtok(line, ":"); 312 313 /* Allocate output buffer. */ 314 size_t size = str_size(line) + 1; 315 char *name = malloc(size); 316 317 if (name != NULL) { 318 /* Copy the result to the output buffer. */ 319 str_cpy(name, size, line); 320 } 321 322 return name; 323 } 324 325 static inline char *skip_spaces(char *line) 343 return line; 344 } 345 346 static inline const char *skip_spaces(const char *line) 326 347 { 327 348 /* Skip leading spaces. */ … … 332 353 } 333 354 334 static void isa_fun_ set_irq(isa_fun_t *fun, int irq)355 static void isa_fun_add_irq(isa_fun_t *fun, int irq) 335 356 { 336 357 size_t count = fun->hw_resources.count; … … 348 369 } 349 370 350 static void isa_fun_ set_dma(isa_fun_t *fun, int dma)371 static void isa_fun_add_dma(isa_fun_t *fun, int dma) 351 372 { 352 373 size_t count = fun->hw_resources.count; … … 381 402 } 382 403 383 static void isa_fun_ set_io_range(isa_fun_t *fun, size_t addr, size_t len)404 static void isa_fun_add_io_range(isa_fun_t *fun, size_t addr, size_t len) 384 405 { 385 406 size_t count = fun->hw_resources.count; 386 407 hw_resource_t *resources = fun->hw_resources.resources; 408 409 isa_bus_t *isa = isa_bus(ddf_fun_get_dev(fun->fnode)); 387 410 388 411 if (count < ISA_MAX_HW_RES) { 389 412 resources[count].type = IO_RANGE; 390 413 resources[count].res.io_range.address = addr; 414 resources[count].res.io_range.address += isa->pio_win.io.base; 391 415 resources[count].res.io_range.size = len; 392 416 resources[count].res.io_range.endianness = LITTLE_ENDIAN; … … 400 424 } 401 425 402 static void fun_parse_irq(isa_fun_t *fun, c har *val)426 static void fun_parse_irq(isa_fun_t *fun, const char *val) 403 427 { 404 428 int irq = 0; … … 409 433 410 434 if (val != end) 411 isa_fun_set_irq(fun, irq); 412 } 413 414 static void fun_parse_dma(isa_fun_t *fun, char *val) 415 { 416 unsigned int dma = 0; 435 isa_fun_add_irq(fun, irq); 436 } 437 438 static void fun_parse_dma(isa_fun_t *fun, const char *val) 439 { 417 440 char *end = NULL; 418 441 419 442 val = skip_spaces(val); 420 dma = (unsigned int)strtol(val, &end, 10);443 const int dma = strtol(val, &end, 10); 421 444 422 445 if (val != end) 423 isa_fun_ set_dma(fun, dma);424 } 425 426 static void fun_parse_io_range(isa_fun_t *fun, c har *val)446 isa_fun_add_dma(fun, dma); 447 } 448 449 static void fun_parse_io_range(isa_fun_t *fun, const char *val) 427 450 { 428 451 size_t addr, len; … … 441 464 return; 442 465 443 isa_fun_ set_io_range(fun, addr, len);444 } 445 446 static void get_match_id(char **id, c har *val)447 { 448 c har *end = val;466 isa_fun_add_io_range(fun, addr, len); 467 } 468 469 static void get_match_id(char **id, const char *val) 470 { 471 const char *end = val; 449 472 450 473 while (!isspace(*end)) … … 456 479 } 457 480 458 static void fun_parse_match_id(isa_fun_t *fun, c har *val)481 static void fun_parse_match_id(isa_fun_t *fun, const char *val) 459 482 { 460 483 char *id = NULL; 461 int score = 0;462 484 char *end = NULL; 463 int rc;464 485 465 486 val = skip_spaces(val); 466 487 467 score = (int)strtol(val, &end, 10);488 int score = (int)strtol(val, &end, 10); 468 489 if (val == end) { 469 490 ddf_msg(LVL_ERROR, "Cannot read match score for function " … … 483 504 "function %s", id, score, ddf_fun_get_name(fun->fnode)); 484 505 485 rc = ddf_fun_add_match_id(fun->fnode, id, score);506 int rc = ddf_fun_add_match_id(fun->fnode, id, score); 486 507 if (rc != EOK) { 487 508 ddf_msg(LVL_ERROR, "Failed adding match ID: %s", … … 492 513 } 493 514 494 static bool prop_parse(isa_fun_t *fun, c har *line, const char *prop,495 void (*read_fn)(isa_fun_t *, c har *))515 static bool prop_parse(isa_fun_t *fun, const char *line, const char *prop, 516 void (*read_fn)(isa_fun_t *, const char *)) 496 517 { 497 518 size_t proplen = str_size(prop); … … 508 529 } 509 530 510 static void fun_prop_parse(isa_fun_t *fun, c har *line)531 static void fun_prop_parse(isa_fun_t *fun, const char *line) 511 532 { 512 533 /* Skip leading spaces. */ … … 523 544 } 524 545 525 static void fun_hw_res_alloc(isa_fun_t *fun)526 {527 fun->hw_resources.resources =528 (hw_resource_t *) malloc(sizeof(hw_resource_t) * ISA_MAX_HW_RES);529 }530 531 static void fun_hw_res_free(isa_fun_t *fun)532 {533 free(fun->hw_resources.resources);534 fun->hw_resources.resources = NULL;535 }536 537 546 static char *isa_fun_read_info(char *fun_conf, isa_bus_t *isa) 538 547 { 539 548 char *line; 540 char *fun_name = NULL;541 549 542 550 /* Skip empty lines. */ 543 while (true){551 do { 544 552 line = str_get_line(fun_conf, &fun_conf); 545 553 … … 549 557 } 550 558 551 if (!line_empty(line)) 552 break; 553 } 559 } while (line_empty(line)); 554 560 555 561 /* Get device name. */ 556 fun_name = get_device_name(line);562 const char *fun_name = get_device_name(line); 557 563 if (fun_name == NULL) 558 564 return NULL; 559 565 560 566 isa_fun_t *fun = isa_fun_create(isa, fun_name); 561 free(fun_name);562 567 if (fun == NULL) { 563 568 return NULL; 564 569 } 565 566 /* Allocate buffer for the list of hardware resources of the device. */567 fun_hw_res_alloc(fun);568 570 569 571 /* Get properties of the device (match ids, irq and io range). */ … … 596 598 } 597 599 598 static void fun_conf_parse(char *conf, isa_bus_t *isa) 599 { 600 static void isa_functions_add(isa_bus_t *isa) 601 { 602 char *conf = fun_conf_read(CHILD_FUN_CONF_PATH); 600 603 while (conf != NULL && *conf != '\0') { 601 604 conf = isa_fun_read_info(conf, isa); 602 605 } 603 } 604 605 static void isa_functions_add(isa_bus_t *isa) 606 { 607 char *fun_conf; 608 609 fun_conf = fun_conf_read(CHILD_FUN_CONF_PATH); 610 if (fun_conf != NULL) { 611 fun_conf_parse(fun_conf, isa); 612 free(fun_conf); 613 } 606 free(conf); 614 607 } 615 608 616 609 static int isa_dev_add(ddf_dev_t *dev) 617 610 { 618 isa_bus_t *isa; 611 async_sess_t *sess; 612 int rc; 619 613 620 614 ddf_msg(LVL_DEBUG, "isa_dev_add, device handle = %d", 621 615 (int) ddf_dev_get_handle(dev)); 622 616 623 isa = ddf_dev_data_alloc(dev, sizeof(isa_bus_t));617 isa_bus_t *isa = ddf_dev_data_alloc(dev, sizeof(isa_bus_t)); 624 618 if (isa == NULL) 625 619 return ENOMEM; … … 628 622 isa->dev = dev; 629 623 list_initialize(&isa->functions); 624 625 sess = ddf_dev_parent_sess_create(dev, EXCHANGE_SERIALIZE); 626 if (sess == NULL) { 627 ddf_msg(LVL_ERROR, "isa_dev_add failed to connect to the " 628 "parent driver."); 629 return ENOENT; 630 } 631 632 rc = pio_window_get(sess, &isa->pio_win); 633 if (rc != EOK) { 634 ddf_msg(LVL_ERROR, "isa_dev_add failed to get PIO window " 635 "for the device."); 636 return rc; 637 } 630 638 631 639 /* Make the bus device more visible. Does not do anything. */ … … 658 666 { 659 667 isa_bus_t *isa = isa_bus(dev); 660 int rc;661 668 662 669 fibril_mutex_lock(&isa->mutex); … … 666 673 isa_fun_t, bus_link); 667 674 668 rc = ddf_fun_offline(fun->fnode);675 int rc = ddf_fun_offline(fun->fnode); 669 676 if (rc != EOK) { 670 677 fibril_mutex_unlock(&isa->mutex); … … 682 689 list_remove(&fun->bus_link); 683 690 684 fun_hw_res_free(fun);685 691 ddf_fun_destroy(fun->fnode); 686 692 } … … 709 715 } 710 716 711 712 static void isa_init() 713 { 717 int main(int argc, char *argv[]) 718 { 719 printf(NAME ": HelenOS ISA bus driver\n"); 714 720 ddf_log_init(NAME); 715 isa_fun_ops.interfaces[HW_RES_DEV_IFACE] = &isa_fun_hw_res_ops;716 }717 718 int main(int argc, char *argv[])719 {720 printf(NAME ": HelenOS ISA bus driver\n");721 isa_init();722 721 return ddf_driver_main(&isa_driver); 723 722 } -
uspace/drv/bus/pci/pciintel/pci.c
r47f5a77 r3a0a4d8 57 57 #include <ops/hw_res.h> 58 58 #include <device/hw_res.h> 59 #include <ops/pio_window.h> 60 #include <device/pio_window.h> 59 61 #include <ddi.h> 60 62 #include <pci_dev_iface.h> … … 141 143 } 142 144 145 static pio_window_t *pciintel_get_pio_window(ddf_fun_t *fnode) 146 { 147 pci_fun_t *fun = pci_fun(fnode); 148 149 if (fun == NULL) 150 return NULL; 151 return &fun->pio_window; 152 } 153 154 143 155 static int pci_config_space_write_32(ddf_fun_t *fun, uint32_t address, 144 156 uint32_t data) … … 198 210 .get_resource_list = &pciintel_get_resources, 199 211 .enable_interrupt = &pciintel_enable_interrupt, 212 }; 213 214 static pio_window_ops_t pciintel_pio_window_ops = { 215 .get_pio_window = &pciintel_get_pio_window 200 216 }; 201 217 … … 211 227 static ddf_dev_ops_t pci_fun_ops = { 212 228 .interfaces[HW_RES_DEV_IFACE] = &pciintel_hw_res_ops, 229 .interfaces[PIO_WINDOW_DEV_IFACE] = &pciintel_pio_window_ops, 213 230 .interfaces[PCI_DEV_IFACE] = &pci_dev_ops 214 231 }; … … 233 250 static void pci_conf_read(pci_fun_t *fun, int reg, uint8_t *buf, size_t len) 234 251 { 252 const uint32_t conf_addr = CONF_ADDR(fun->bus, fun->dev, fun->fn, reg); 235 253 pci_bus_t *bus = pci_bus_from_fun(fun); 254 uint32_t val; 236 255 237 256 fibril_mutex_lock(&bus->conf_mutex); 238 239 const uint32_t conf_addr = CONF_ADDR(fun->bus, fun->dev, fun->fn, reg); 240 void *addr = bus->conf_data_port + (reg & 3); 241 257 242 258 pio_write_32(bus->conf_addr_port, host2uint32_t_le(conf_addr)); 243 259 260 /* 261 * Always read full 32-bits from the PCI conf_data_port register and 262 * get the desired portion of it afterwards. Some architectures do not 263 * support shorter PIO reads offset from this register. 264 */ 265 val = uint32_t_le2host(pio_read_32(bus->conf_data_port)); 266 244 267 switch (len) { 245 268 case 1: 246 /* No endianness change for 1 byte */ 247 buf[0] = pio_read_8(addr); 269 *buf = (uint8_t) (val >> ((reg & 3) * 8)); 248 270 break; 249 271 case 2: 250 ((uint16_t *) buf)[0] = uint16_t_le2host(pio_read_16(addr));272 *((uint16_t *) buf) = (uint16_t) (val >> ((reg & 3)) * 8); 251 273 break; 252 274 case 4: 253 ((uint32_t *) buf)[0] = uint32_t_le2host(pio_read_32(addr));275 *((uint32_t *) buf) = (uint32_t) val; 254 276 break; 255 277 } … … 260 282 static void pci_conf_write(pci_fun_t *fun, int reg, uint8_t *buf, size_t len) 261 283 { 284 const uint32_t conf_addr = CONF_ADDR(fun->bus, fun->dev, fun->fn, reg); 262 285 pci_bus_t *bus = pci_bus_from_fun(fun); 286 uint32_t val; 263 287 264 288 fibril_mutex_lock(&bus->conf_mutex); 265 266 const uint32_t conf_addr = CONF_ADDR(fun->bus, fun->dev, fun->fn, reg); 267 void *addr = bus->conf_data_port + (reg & 3); 268 269 pio_write_32(bus->conf_addr_port, host2uint32_t_le(conf_addr)); 289 290 /* 291 * Prepare to write full 32-bits to the PCI conf_data_port register. 292 * Some architectures do not support shorter PIO writes offset from this 293 * register. 294 */ 295 296 if (len < 4) { 297 /* 298 * We have fewer than full 32-bits, so we need to read the 299 * missing bits first. 300 */ 301 pio_write_32(bus->conf_addr_port, host2uint32_t_le(conf_addr)); 302 val = uint32_t_le2host(pio_read_32(bus->conf_data_port)); 303 } 270 304 271 305 switch (len) { 272 306 case 1: 273 /* No endianness change for 1 byte */274 pio_write_8(addr, buf[0]);307 val &= ~(0xffU << ((reg & 3) * 8)); 308 val |= *buf << ((reg & 3) * 8); 275 309 break; 276 310 case 2: 277 pio_write_16(addr, host2uint16_t_le(((uint16_t *) buf)[0])); 311 val &= ~(0xffffU << ((reg & 3) * 8)); 312 val |= *((uint16_t *) buf) << ((reg & 3) * 8); 278 313 break; 279 314 case 4: 280 pio_write_32(addr, host2uint32_t_le(((uint32_t *) buf)[0]));315 val = *((uint32_t *) buf); 281 316 break; 282 317 } 318 319 pio_write_32(bus->conf_addr_port, host2uint32_t_le(conf_addr)); 320 pio_write_32(bus->conf_data_port, host2uint32_t_le(val)); 283 321 284 322 fibril_mutex_unlock(&bus->conf_mutex); … … 433 471 { 434 472 /* Value of the BAR */ 435 uint32_t val, mask; 473 uint32_t val; 474 uint32_t bar; 475 uint32_t mask; 476 436 477 /* IO space address */ 437 478 bool io; … … 471 512 /* Get the address mask. */ 472 513 pci_conf_write_32(fun, addr, 0xffffffff); 473 mask &= pci_conf_read_32(fun, addr); 474 514 bar = pci_conf_read_32(fun, addr); 515 516 /* 517 * Unimplemented BARs read back as all 0's. 518 */ 519 if (!bar) 520 return addr + (addrw64 ? 8 : 4); 521 522 mask &= bar; 523 475 524 /* Restore the original value. */ 476 525 pci_conf_write_32(fun, addr, val); … … 520 569 { 521 570 uint8_t irq = pci_conf_read_8(fun, PCI_BRIDGE_INT_LINE); 522 if (irq != 0xff) 571 uint8_t pin = pci_conf_read_8(fun, PCI_BRIDGE_INT_PIN); 572 573 if (pin != 0 && irq != 0xff) 523 574 pci_add_interrupt(fun, irq); 524 575 } … … 583 634 pci_read_bars(fun); 584 635 pci_read_interrupt(fun); 636 637 /* Propagate the PIO window to the function. */ 638 fun->pio_window = bus->pio_win; 585 639 586 640 ddf_fun_set_ops(fun->fnode, &pci_fun_ops); … … 613 667 static int pci_dev_add(ddf_dev_t *dnode) 614 668 { 669 hw_resource_list_t hw_resources; 615 670 pci_bus_t *bus = NULL; 616 671 ddf_fun_t *ctl = NULL; … … 638 693 goto fail; 639 694 } 640 641 hw_resource_list_t hw_resources; 695 696 rc = pio_window_get(sess, &bus->pio_win); 697 if (rc != EOK) { 698 ddf_msg(LVL_ERROR, "pci_dev_add failed to get PIO window " 699 "for the device."); 700 goto fail; 701 } 642 702 643 703 rc = hw_res_get_resource_list(sess, &hw_resources); … … 729 789 { 730 790 ddf_log_init(NAME); 731 pci_fun_ops.interfaces[HW_RES_DEV_IFACE] = &pciintel_hw_res_ops;732 pci_fun_ops.interfaces[PCI_DEV_IFACE] = &pci_dev_ops;733 791 } 734 792 -
uspace/drv/bus/pci/pciintel/pci.h
r47f5a77 r3a0a4d8 40 40 #include "pci_regs.h" 41 41 42 #define PCI_MAX_HW_RES 842 #define PCI_MAX_HW_RES 10 43 43 44 44 typedef struct pciintel_bus { … … 49 49 void *conf_data_port; 50 50 void *conf_addr_port; 51 pio_window_t pio_win; 51 52 fibril_mutex_t conf_mutex; 52 53 } pci_bus_t; … … 68 69 hw_resource_list_t hw_resources; 69 70 hw_resource_t resources[PCI_MAX_HW_RES]; 71 pio_window_t pio_window; 70 72 } pci_fun_t; 71 73 -
uspace/drv/bus/usb/uhci/utils/malloc32.h
r47f5a77 r3a0a4d8 92 92 */ 93 93 static inline void free32(void *addr) 94 { free(addr); } 94 { 95 free(addr); 96 } 95 97 96 98 /** Create 4KB page mapping … … 98 100 * @return Address of the mapped page, NULL on failure. 99 101 */ 100 static inline void * get_page(void)102 static inline void *get_page(void) 101 103 { 102 void *address, *phys; 104 uintptr_t phys; 105 void *address; 106 103 107 const int ret = dmamem_map_anonymous(UHCI_REQUIRED_PAGE_SIZE, 104 AS_AREA_READ | AS_AREA_WRITE, 0, &phys, &address); 105 return ret == EOK ? address : NULL; 108 DMAMEM_4GiB, AS_AREA_READ | AS_AREA_WRITE, 0, &phys, 109 &address); 110 111 return ((ret == EOK) ? address : NULL); 106 112 } 107 113 -
uspace/drv/bus/usb/usbmid/explore.c
r47f5a77 r3a0a4d8 56 56 static bool interface_in_list(const list_t *list, int interface_no) 57 57 { 58 list_foreach(*list, l) { 59 usbmid_interface_t *iface = usbmid_interface_from_link(l); 58 list_foreach(*list, link, usbmid_interface_t, iface) { 60 59 if (iface->interface_no == interface_no) { 61 60 return true; … … 190 189 191 190 /* Start child function for every interface. */ 192 list_foreach(usb_mid->interface_list, link) { 193 usbmid_interface_t *iface = usbmid_interface_from_link(link); 194 191 list_foreach(usb_mid->interface_list, link, usbmid_interface_t, iface) { 195 192 usb_log_info("Creating child for interface %d (%s).\n", 196 193 iface->interface_no, -
uspace/drv/bus/usb/usbmid/usbmid.c
r47f5a77 r3a0a4d8 135 135 } 136 136 137 list_foreach(match_ids.ids, link) { 138 match_id_t *match_id = list_get_instance(link, match_id_t, link); 137 list_foreach(match_ids.ids, link, match_id_t, match_id) { 139 138 rc = ddf_fun_add_match_id(child, match_id->id, match_id->score); 140 139 if (rc != EOK) { -
uspace/drv/bus/usb/vhc/transfer.c
r47f5a77 r3a0a4d8 92 92 93 93 bool target_found = false; 94 list_foreach(vhc->devices, pos) { 95 vhc_virtdev_t *dev = list_get_instance(pos, vhc_virtdev_t, link); 94 list_foreach(vhc->devices, link, vhc_virtdev_t, dev) { 96 95 fibril_mutex_lock(&dev->guard); 97 96 if (dev->address == transfer->address) { -
uspace/drv/fb/amdm37x_dispc/amdm37x_dispc.c
r47f5a77 r3a0a4d8 273 273 ddf_log_note("Setting mode: %ux%ux%u\n", x, y, bpp*8); 274 274 const size_t size = ALIGN_UP(x * y * bpp, PAGE_SIZE); 275 void *buffer, *pa; 276 int ret = dmamem_map_anonymous(size, AS_AREA_READ | AS_AREA_WRITE, 277 0, &pa, &buffer); 275 uintptr_t pa; 276 void *buffer; 277 int ret = dmamem_map_anonymous(size, DMAMEM_4GiB, 278 AS_AREA_READ | AS_AREA_WRITE, 0, &pa, &buffer); 278 279 if (ret != EOK) { 279 280 ddf_log_error("Failed to get new FB\n"); 280 281 return ret; 281 282 } 283 282 284 amdm37x_dispc_setup_fb(dispc->regs, x, y, bpp *8, (uint32_t)pa); 283 285 dispc->active_fb.idx = mode.index; -
uspace/drv/fb/kfb/port.c
r47f5a77 r3a0a4d8 333 333 334 334 kfb.size = scanline * height; 335 rc = physmem_map( (void *)paddr + offset,335 rc = physmem_map(paddr + offset, 336 336 ALIGN_UP(kfb.size, PAGE_SIZE) >> PAGE_WIDTH, 337 337 AS_AREA_READ | AS_AREA_WRITE, (void *) &kfb.addr); -
uspace/drv/infrastructure/root/root.c
r47f5a77 r3a0a4d8 208 208 /* 209 209 * Register virtual devices root. 210 * We ignoreerror occurrence because virtual devices shall not be210 * We warn on error occurrence because virtual devices shall not be 211 211 * vital for the system. 212 212 */ 213 (void) add_virtual_root_fun(dev); 213 int res = add_virtual_root_fun(dev); 214 if (res != EOK) 215 ddf_msg(LVL_WARN, "Failed to add virtual child."); 214 216 215 217 /* Register root device's children. */ 216 intres = add_platform_fun(dev);218 res = add_platform_fun(dev); 217 219 if (EOK != res) 218 220 ddf_msg(LVL_ERROR, "Failed adding child device for platform."); -
uspace/drv/infrastructure/rootamdm37x/rootamdm37x.c
r47f5a77 r3a0a4d8 48 48 49 49 typedef struct { 50 const char *name; 51 match_id_t match_id; 50 52 hw_resource_list_t hw_resources; 51 53 } rootamdm37x_fun_t; 52 54 53 /* See amdm37x TRM page. 3316 for these values */ 54 #define OHCI_BASE_ADDRESS 0x48064400 55 #define OHCI_SIZE 1024 56 #define EHCI_BASE_ADDRESS 0x48064800 57 #define EHCI_SIZE 1024 55 /* See amdm37x TRM page 3316 for these values */ 56 #define OHCI_BASE_ADDRESS 0x48064400 57 #define OHCI_SIZE 1024 58 #define EHCI_BASE_ADDRESS 0x48064800 59 #define EHCI_SIZE 1024 60 61 /* See amdm37x TRM page 1813 for these values */ 62 #define DSS_BASE_ADDRESS 0x48050000 63 #define DSS_SIZE 512 64 #define DISPC_BASE_ADDRESS 0x48050400 65 #define DISPC_SIZE 1024 66 #define VIDEO_ENC_BASE_ADDRESS 0x48050C00 67 #define VIDEO_ENC_SIZE 256 68 58 69 59 70 static hw_resource_t ohci_res[] = { … … 88 99 }; 89 100 90 static const rootamdm37x_fun_t ohci = { 91 .hw_resources = { 92 .resources = ohci_res, 93 .count = sizeof(ohci_res)/sizeof(ohci_res[0]), 94 } 95 }; 96 97 static const rootamdm37x_fun_t ehci = { 98 .hw_resources = { 99 .resources = ehci_res, 100 .count = sizeof(ehci_res) / sizeof(ehci_res[0]), 101 } 102 }; 101 static hw_resource_t disp_res[] = { 102 { 103 .type = MEM_RANGE, 104 .res.io_range = { 105 .address = DSS_BASE_ADDRESS, 106 .size = DSS_SIZE, 107 .endianness = LITTLE_ENDIAN 108 }, 109 }, 110 { 111 .type = MEM_RANGE, 112 .res.io_range = { 113 .address = DISPC_BASE_ADDRESS, 114 .size = DISPC_SIZE, 115 .endianness = LITTLE_ENDIAN 116 }, 117 }, 118 { 119 .type = MEM_RANGE, 120 .res.io_range = { 121 .address = VIDEO_ENC_BASE_ADDRESS, 122 .size = VIDEO_ENC_SIZE, 123 .endianness = LITTLE_ENDIAN 124 }, 125 }, 126 { 127 .type = INTERRUPT, 128 .res.interrupt = { .irq = 25 }, 129 }, 130 }; 131 132 static const rootamdm37x_fun_t amdm37x_funcs[] = { 133 { 134 .name = "ohci", 135 .match_id = { .id = "usb/host=ohci", .score = 90 }, 136 .hw_resources = { .resources = ohci_res, .count = ARRAY_SIZE(ohci_res) } 137 }, 138 { 139 .name = "ehci", 140 .match_id = { .id = "usb/host=ehci", .score = 90 }, 141 .hw_resources = { .resources = ehci_res, .count = ARRAY_SIZE(ehci_res) } 142 }, 143 { 144 .name = "fb", 145 .match_id = { .id = "amdm37x&dispc", .score = 90 }, 146 .hw_resources = { .resources = disp_res, .count = ARRAY_SIZE(disp_res) } 147 }, 148 }; 149 103 150 104 151 static hw_resource_list_t *rootamdm37x_get_resources(ddf_fun_t *fnode); … … 114 161 }; 115 162 116 static int rootamdm37x_add_fun(ddf_dev_t *dev, const char *name, 117 const char *str_match_id, const rootamdm37x_fun_t *fun) 118 { 119 ddf_msg(LVL_DEBUG, "Adding new function '%s'.", name); 120 163 static int rootamdm37x_add_fun(ddf_dev_t *dev, const rootamdm37x_fun_t *fun) 164 { 165 assert(dev); 166 assert(fun); 167 168 ddf_msg(LVL_DEBUG, "Adding new function '%s'.", fun->name); 169 121 170 /* Create new device function. */ 122 ddf_fun_t *fnode = ddf_fun_create(dev, fun_inner, name);171 ddf_fun_t *fnode = ddf_fun_create(dev, fun_inner, fun->name); 123 172 if (fnode == NULL) 124 173 return ENOMEM; 125 174 126 175 /* Add match id */ 127 int ret = ddf_fun_add_match_id(fnode, str_match_id, 100); 176 int ret = ddf_fun_add_match_id(fnode, 177 fun->match_id.id, fun->match_id.score); 128 178 if (ret != EOK) { 129 179 ddf_fun_destroy(fnode); … … 146 196 ret = ddf_fun_bind(fnode); 147 197 if (ret != EOK) { 148 ddf_msg(LVL_ERROR, "Failed binding function %s.", name);198 ddf_msg(LVL_ERROR, "Failed binding function %s.", fun->name); 149 199 ddf_fun_destroy(fnode); 150 200 return ret; … … 189 239 190 240 /* Register functions */ 191 if (rootamdm37x_add_fun(dev, "ohci", "usb/host=ohci", &ohci) != EOK) 192 ddf_msg(LVL_ERROR, "Failed to add OHCI function for " 193 "BeagleBoard-xM platform."); 194 if (rootamdm37x_add_fun(dev, "ehci", "usb/host=ehci", &ehci) != EOK) 195 ddf_msg(LVL_ERROR, "Failed to add EHCI function for " 196 "BeagleBoard-xM platform."); 197 if (rootamdm37x_add_fun(dev, "dispc", "amdm37x&dispc", &ehci) != EOK) 198 ddf_msg(LVL_ERROR, "Failed to add dispc function for " 199 "BeagleBoard-xM platform."); 200 241 for (unsigned i = 0; i < ARRAY_SIZE(amdm37x_funcs); ++i) { 242 if (rootamdm37x_add_fun(dev, &amdm37x_funcs[i]) != EOK) 243 ddf_msg(LVL_ERROR, "Failed to add %s function for " 244 "BeagleBoard-xM platform.", amdm37x_funcs[i].name); 245 } 201 246 return EOK; 202 247 } -
uspace/drv/infrastructure/rootamdm37x/uhh.h
r47f5a77 r3a0a4d8 85 85 #define UHH_DEBUG_CSR_EHCI_SIMULATION_MODE_FLAG (1 << 6) 86 86 #define UHH_DEBUG_CSR_OHCI_CNTSEL_FLAG (1 << 7) 87 #define UHH_DEBUG_CSR_OHCI_GLOBAL_ sUSPEND_FLAG (1 << 16)87 #define UHH_DEBUG_CSR_OHCI_GLOBAL_SUSPEND_FLAG (1 << 16) 88 88 #define UHH_DEBUG_CSR_OHCI_CCS1_FLAG (1 << 17) 89 89 #define UHH_DEBUG_CSR_OHCI_CCS2_FLAG (1 << 18) -
uspace/drv/infrastructure/rootpc/rootpc.c
r47f5a77 r3a0a4d8 51 51 #include <ops/hw_res.h> 52 52 #include <device/hw_res.h> 53 #include <ops/pio_window.h> 54 #include <device/pio_window.h> 53 55 54 56 #define NAME "rootpc" … … 56 58 typedef struct rootpc_fun { 57 59 hw_resource_list_t hw_resources; 60 pio_window_t pio_window; 58 61 } rootpc_fun_t; 59 62 … … 93 96 static rootpc_fun_t pci_data = { 94 97 .hw_resources = { 95 sizeof(pci_conf_regs) /sizeof(pci_conf_regs[0]),98 sizeof(pci_conf_regs) / sizeof(pci_conf_regs[0]), 96 99 pci_conf_regs 100 }, 101 .pio_window = { 102 .mem = { 103 .base = UINT32_C(0), 104 .size = UINT32_C(0xffffffff) /* practical maximum */ 105 }, 106 .io = { 107 .base = UINT32_C(0), 108 .size = UINT32_C(0x10000) 109 } 97 110 } 98 111 }; … … 117 130 118 131 return false; 132 } 133 134 static pio_window_t *rootpc_get_pio_window(ddf_fun_t *fnode) 135 { 136 rootpc_fun_t *fun = rootpc_fun(fnode); 137 138 assert(fun != NULL); 139 return &fun->pio_window; 119 140 } 120 141 … … 122 143 .get_resource_list = &rootpc_get_resources, 123 144 .enable_interrupt = &rootpc_enable_interrupt, 145 }; 146 147 static pio_window_ops_t fun_pio_window_ops = { 148 .get_pio_window = &rootpc_get_pio_window 124 149 }; 125 150 … … 197 222 ddf_log_init(NAME); 198 223 rootpc_fun_ops.interfaces[HW_RES_DEV_IFACE] = &fun_hw_res_ops; 224 rootpc_fun_ops.interfaces[PIO_WINDOW_DEV_IFACE] = &fun_pio_window_ops; 199 225 } 200 226 -
uspace/drv/nic/e1k/e1k.c
r47f5a77 r3a0a4d8 129 129 130 130 /** Physical tx ring address */ 131 void *tx_ring_phys;131 uintptr_t tx_ring_phys; 132 132 /** Virtual tx ring address */ 133 133 void *tx_ring_virt; 134 134 135 135 /** Ring of TX frames, physical address */ 136 void **tx_frame_phys;136 uintptr_t *tx_frame_phys; 137 137 /** Ring of TX frames, virtual address */ 138 138 void **tx_frame_virt; 139 139 140 140 /** Physical rx ring address */ 141 void *rx_ring_phys;141 uintptr_t rx_ring_phys; 142 142 /** Virtual rx ring address */ 143 143 void *rx_ring_virt; 144 144 145 145 /** Ring of RX frames, physical address */ 146 void **rx_frame_phys;146 uintptr_t *rx_frame_phys; 147 147 /** Ring of RX frames, virtual address */ 148 148 void **rx_frame_virt; … … 1377 1377 int rc = dmamem_map_anonymous( 1378 1378 E1000_RX_FRAME_COUNT * sizeof(e1000_rx_descriptor_t), 1379 AS_AREA_READ | AS_AREA_WRITE, 0, &e1000->rx_ring_phys,1380 &e1000->rx_ring_ virt);1379 DMAMEM_4GiB, AS_AREA_READ | AS_AREA_WRITE, 0, 1380 &e1000->rx_ring_phys, &e1000->rx_ring_virt); 1381 1381 if (rc != EOK) 1382 1382 return rc; … … 1387 1387 (uint32_t) PTR_TO_U64(e1000->rx_ring_phys)); 1388 1388 1389 e1000->rx_frame_phys = 1390 calloc(E1000_RX_FRAME_COUNT, sizeof( void *));1389 e1000->rx_frame_phys = (uintptr_t *) 1390 calloc(E1000_RX_FRAME_COUNT, sizeof(uintptr_t)); 1391 1391 e1000->rx_frame_virt = 1392 1392 calloc(E1000_RX_FRAME_COUNT, sizeof(void *)); 1393 if ( e1000->rx_frame_phys == NULL || e1000->rx_frame_virt == NULL) {1393 if ((e1000->rx_frame_phys == NULL) || (e1000->rx_frame_virt == NULL)) { 1394 1394 rc = ENOMEM; 1395 1395 goto error; … … 1397 1397 1398 1398 size_t i; 1399 uintptr_t frame_phys; 1399 1400 void *frame_virt; 1400 void *frame_phys;1401 1401 1402 1402 for (i = 0; i < E1000_RX_FRAME_COUNT; i++) { 1403 rc = dmamem_map_anonymous( 1404 E1000_MAX_SEND_FRAME_SIZE, AS_AREA_READ | AS_AREA_WRITE,1405 0,&frame_phys, &frame_virt);1403 rc = dmamem_map_anonymous(E1000_MAX_SEND_FRAME_SIZE, 1404 DMAMEM_4GiB, AS_AREA_READ | AS_AREA_WRITE, 0, 1405 &frame_phys, &frame_virt); 1406 1406 if (rc != EOK) 1407 1407 goto error; 1408 1408 1409 e1000->rx_frame_phys[i] = frame_phys; 1409 1410 e1000->rx_frame_virt[i] = frame_virt; 1410 e1000->rx_frame_phys[i] = frame_phys;1411 1411 } 1412 1412 … … 1424 1424 if (e1000->rx_frame_virt[i] != NULL) { 1425 1425 dmamem_unmap_anonymous(e1000->rx_frame_virt[i]); 1426 e1000->rx_frame_phys[i] = 0; 1426 1427 e1000->rx_frame_virt[i] = NULL; 1427 e1000->rx_frame_phys[i] = NULL;1428 1428 } 1429 1429 } … … 1436 1436 if (e1000->rx_frame_virt != NULL) { 1437 1437 free(e1000->rx_frame_virt); 1438 e1000->rx_frame_ phys= NULL;1438 e1000->rx_frame_virt = NULL; 1439 1439 } 1440 1440 … … 1454 1454 for (unsigned int offset = 0; offset < E1000_RX_FRAME_COUNT; offset++) { 1455 1455 dmamem_unmap_anonymous(e1000->rx_frame_virt[offset]); 1456 e1000->rx_frame_phys[offset] = 0; 1456 1457 e1000->rx_frame_virt[offset] = NULL; 1457 e1000->rx_frame_phys[offset] = NULL;1458 1458 } 1459 1459 1460 1460 free(e1000->rx_frame_virt); 1461 free(e1000->rx_frame_phys); 1461 1462 e1000->rx_frame_phys = NULL; 1462 1463 e1000->rx_frame_virt = NULL; 1463 e1000->rx_frame_phys = NULL;1464 1464 1465 dmamem_unmap_anonymous(e1000->rx_ring_virt); 1465 1466 } … … 1569 1570 fibril_mutex_lock(&e1000->tx_lock); 1570 1571 1571 e1000->tx_ring_phys = NULL;1572 e1000->tx_ring_phys = 0; 1572 1573 e1000->tx_ring_virt = NULL; 1574 1573 1575 e1000->tx_frame_phys = NULL; 1574 1576 e1000->tx_frame_virt = NULL; … … 1576 1578 int rc = dmamem_map_anonymous( 1577 1579 E1000_TX_FRAME_COUNT * sizeof(e1000_tx_descriptor_t), 1578 AS_AREA_READ | AS_AREA_WRITE, 0, &e1000->tx_ring_phys,1579 &e1000->tx_ring_ virt);1580 DMAMEM_4GiB, AS_AREA_READ | AS_AREA_WRITE, 0, 1581 &e1000->tx_ring_phys, &e1000->tx_ring_virt); 1580 1582 if (rc != EOK) 1581 1583 goto error; … … 1584 1586 E1000_TX_FRAME_COUNT * sizeof(e1000_tx_descriptor_t)); 1585 1587 1586 e1000->tx_frame_phys = calloc(E1000_TX_FRAME_COUNT, sizeof(void *)); 1587 e1000->tx_frame_virt = calloc(E1000_TX_FRAME_COUNT, sizeof(void *)); 1588 1589 if (e1000->tx_frame_phys == NULL || e1000->tx_frame_virt == NULL) { 1588 e1000->tx_frame_phys = (uintptr_t *) 1589 calloc(E1000_TX_FRAME_COUNT, sizeof(uintptr_t)); 1590 e1000->tx_frame_virt = 1591 calloc(E1000_TX_FRAME_COUNT, sizeof(void *)); 1592 1593 if ((e1000->tx_frame_phys == NULL) || (e1000->tx_frame_virt == NULL)) { 1590 1594 rc = ENOMEM; 1591 1595 goto error; … … 1593 1597 1594 1598 for (i = 0; i < E1000_TX_FRAME_COUNT; i++) { 1595 rc = dmamem_map_anonymous( 1596 E1000_MAX_SEND_FRAME_SIZE, AS_AREA_READ | AS_AREA_WRITE,1599 rc = dmamem_map_anonymous(E1000_MAX_SEND_FRAME_SIZE, 1600 DMAMEM_4GiB, AS_AREA_READ | AS_AREA_WRITE, 1597 1601 0, &e1000->tx_frame_phys[i], &e1000->tx_frame_virt[i]); 1598 1602 if (rc != EOK) … … 1616 1620 } 1617 1621 1618 if ( e1000->tx_frame_phys != NULL && e1000->tx_frame_virt != NULL) {1622 if ((e1000->tx_frame_phys != NULL) && (e1000->tx_frame_virt != NULL)) { 1619 1623 for (i = 0; i < E1000_TX_FRAME_COUNT; i++) { 1620 1624 if (e1000->tx_frame_virt[i] != NULL) { 1621 1625 dmamem_unmap_anonymous(e1000->tx_frame_virt[i]); 1626 e1000->tx_frame_phys[i] = 0; 1622 1627 e1000->tx_frame_virt[i] = NULL; 1623 e1000->tx_frame_phys[i] = NULL;1624 1628 } 1625 1629 } … … 1633 1637 if (e1000->tx_frame_virt != NULL) { 1634 1638 free(e1000->tx_frame_virt); 1635 e1000->tx_frame_ phys= NULL;1639 e1000->tx_frame_virt = NULL; 1636 1640 } 1637 1641 … … 1650 1654 for (i = 0; i < E1000_TX_FRAME_COUNT; i++) { 1651 1655 dmamem_unmap_anonymous(e1000->tx_frame_virt[i]); 1656 e1000->tx_frame_phys[i] = 0; 1652 1657 e1000->tx_frame_virt[i] = NULL; 1653 e1000->tx_frame_phys[i] = NULL;1654 1658 } 1655 1659 … … 1661 1665 if (e1000->tx_frame_virt != NULL) { 1662 1666 free(e1000->tx_frame_virt); 1663 e1000->tx_frame_ phys= NULL;1667 e1000->tx_frame_virt = NULL; 1664 1668 } 1665 1669 -
uspace/drv/nic/rtl8139/driver.c
r47f5a77 r3a0a4d8 1144 1144 ddf_msg(LVL_DEBUG, "Creating buffers"); 1145 1145 1146 rc = dmamem_map_anonymous(TX_PAGES * PAGE_SIZE, AS_AREA_WRITE, 0,1147 &rtl8139->tx_buff_phys, &rtl8139->tx_buff_virt);1146 rc = dmamem_map_anonymous(TX_PAGES * PAGE_SIZE, DMAMEM_4GiB, 1147 AS_AREA_WRITE, 0, &rtl8139->tx_buff_phys, &rtl8139->tx_buff_virt); 1148 1148 if (rc != EOK) { 1149 1149 ddf_msg(LVL_ERROR, "Can not allocate transmitter buffers."); … … 1164 1164 RxBUF_TOT_LENGTH); 1165 1165 1166 rc = dmamem_map_anonymous(RxBUF_TOT_LENGTH, AS_AREA_READ, 0,1167 &rtl8139->rx_buff_phys, &rtl8139->rx_buff_virt);1166 rc = dmamem_map_anonymous(RxBUF_TOT_LENGTH, DMAMEM_4GiB, 1167 AS_AREA_READ, 0, &rtl8139->rx_buff_phys, &rtl8139->rx_buff_virt); 1168 1168 if (rc != EOK) { 1169 1169 ddf_msg(LVL_ERROR, "Can not allocate receive buffer."); -
uspace/drv/nic/rtl8139/driver.h
r47f5a77 r3a0a4d8 100 100 * Each buffer takes 2kB 101 101 */ 102 void *tx_buff_phys;102 uintptr_t tx_buff_phys; 103 103 void *tx_buff_virt; 104 104 … … 117 117 118 118 /** Buffer for receiving frames */ 119 void *rx_buff_phys;119 uintptr_t rx_buff_phys; 120 120 void *rx_buff_virt; 121 121
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