Changeset 3a0a4d8 in mainline for kernel/arch/mips32

Timestamp:

2013-09-12T07:54:05Z (12 years ago)

Author:

Maurizio Lombardi <m.lombardi85@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

95027b5

Parents:

47f5a77 (diff), 64f3d3b (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the (diff) links above to see all the changes relative to each parent.

Message:

merge mainline changes

Location:

kernel/arch/mips32

Files:

• include/arch/mm/page.h (modified) (3 diffs)
• src/mach/malta/malta.c (modified) (1 diff)
• src/mm/tlb.c (modified) (3 diffs)

kernel/arch/mips32/include/arch/mm/page.h

@@ -27 +27 @@
  */
 
-/** @addtogroup mips32mm        
+/** @addtogroup mips32mm
  * @{
  */
@@ -70 +70 @@
  * - PTL3 has 4096 entries (12 bits)
  */
- 
+
 /* Macros describing number of entries in each level. */
-#define PTL0_ENTRIES_ARCH       64
-#define PTL1_ENTRIES_ARCH       0
-#define PTL2_ENTRIES_ARCH       0
-#define PTL3_ENTRIES_ARCH       4096
+#define PTL0_ENTRIES_ARCH  64
+#define PTL1_ENTRIES_ARCH  0
+#define PTL2_ENTRIES_ARCH  0
+#define PTL3_ENTRIES_ARCH  4096
 
 /* Macros describing size of page tables in each level. */
-#define PTL0_SIZE_ARCH          ONE_FRAME
-#define PTL1_SIZE_ARCH          0
-#define PTL2_SIZE_ARCH          0
-#define PTL3_SIZE_ARCH          ONE_FRAME
+#define PTL0_FRAMES_ARCH  1
+#define PTL1_FRAMES_ARCH  1
+#define PTL2_FRAMES_ARCH  1
+#define PTL3_FRAMES_ARCH  1
 
 /* Macros calculating entry indices for each level. */
-#define PTL0_INDEX_ARCH(vaddr)  ((vaddr) >> 26) 
-#define PTL1_INDEX_ARCH(vaddr)  0
-#define PTL2_INDEX_ARCH(vaddr)  0
-#define PTL3_INDEX_ARCH(vaddr)  (((vaddr) >> 14) & 0xfff)
+#define PTL0_INDEX_ARCH(vaddr)  ((vaddr) >> 26)
+#define PTL1_INDEX_ARCH(vaddr)  0
+#define PTL2_INDEX_ARCH(vaddr)  0
+#define PTL3_INDEX_ARCH(vaddr)  (((vaddr) >> 14) & 0xfff)
 
 /* Set accessor for PTL0 address. */
 #define SET_PTL0_ADDRESS_ARCH(ptl0)
 
-/* Get PTE address accessors for each level. */ 
+/* Get PTE address accessors for each level. */
 #define GET_PTL1_ADDRESS_ARCH(ptl0, i) \
         (((pte_t *) (ptl0))[(i)].pfn << 12)
@@ -196 +196 @@
         p->p = 1;
 }
-        
 
 extern void page_arch_init(void);

kernel/arch/mips32/src/mach/malta/malta.c

@@ -103 +103 @@
 void malta_input_init(void)
 {
+        (void) stdin_wire();
 }
 

kernel/arch/mips32/src/mm/tlb.c

@@ -48 +48 @@
 #include <symtab.h>
 
-#define PFN_SHIFT       12
-#define VPN_SHIFT       12
-#define ADDR2VPN(a)     ((a) >> VPN_SHIFT)
-#define ADDR2VPN2(a)    (ADDR2VPN((a)) >> 1)
-#define VPN2ADDR(vpn)   ((vpn) << VPN_SHIFT)
-#define VPN22ADDR(vpn2) (VPN2ADDR(vpn2) << 1)
-#define PFN2ADDR(pfn)   ((pfn) << PFN_SHIFT)
-
-#define BANK_SELECT_BIT(a)      (((a) >> PAGE_WIDTH) & 1) 
-        
+#define PFN_SHIFT  12
+#define VPN_SHIFT  12
+
+#define ADDR2HI_VPN(a)   ((a) >> VPN_SHIFT)
+#define ADDR2HI_VPN2(a)  (ADDR2HI_VPN((a)) >> 1)
+
+#define HI_VPN2ADDR(vpn)    ((vpn) << VPN_SHIFT)
+#define HI_VPN22ADDR(vpn2)  (HI_VPN2ADDR(vpn2) << 1)
+
+#define LO_PFN2ADDR(pfn)  ((pfn) << PFN_SHIFT)
+
+#define BANK_SELECT_BIT(a)  (((a) >> PAGE_WIDTH) & 1)
 
 /** Initialize TLB.
@@ -266 +268 @@
 {
         hi->value = 0;
-        hi->vpn2 = ADDR2VPN2(ALIGN_DOWN(addr, PAGE_SIZE));
+        hi->vpn2 = ADDR2HI_VPN2(ALIGN_DOWN(addr, PAGE_SIZE));
         hi->asid = asid;
 }
@@ -295 +297 @@
                 
                 printf("%-4u %-6u %0#10x %-#6x  %1u%1u%1u%1u  %0#10x\n",
-                    i, hi.asid, VPN22ADDR(hi.vpn2), mask.mask,
-                    lo0.g, lo0.v, lo0.d, lo0.c, PFN2ADDR(lo0.pfn));
+                    i, hi.asid, HI_VPN22ADDR(hi.vpn2), mask.mask,
+                    lo0.g, lo0.v, lo0.d, lo0.c, LO_PFN2ADDR(lo0.pfn));
                 printf("                               %1u%1u%1u%1u  %0#10x\n",
-                    lo1.g, lo1.v, lo1.d, lo1.c, PFN2ADDR(lo1.pfn));
+                    lo1.g, lo1.v, lo1.d, lo1.c, LO_PFN2ADDR(lo1.pfn));
         }