Index: arch/mips/Makefile.inc =================================================================== --- arch/mips/Makefile.inc (revision b0edf3b2dee68a5024674c89cad7b78b9d0b5aa2) +++ arch/mips/Makefile.inc (revision 38de8a54725cd7608700bfd9591eab3fc416d848) @@ -25,5 +25,5 @@ arch/mips.c \ arch/dummy.S \ - arch/putchar.c \ + arch/console.c \ arch/asm.S \ arch/exception.c \ Index: arch/mips/_link.ld =================================================================== --- arch/mips/_link.ld (revision b0edf3b2dee68a5024674c89cad7b78b9d0b5aa2) +++ arch/mips/_link.ld (revision 38de8a54725cd7608700bfd9591eab3fc416d848) @@ -7,9 +7,12 @@ */ +/* OUTPUT_FORMAT(ecoff-littlemips) */ OUTPUT_FORMAT(binary) +/* OUTPUT_FORMAT(elf32-little) */ + ENTRY(kernel_image_start) SECTIONS { - .image 0x80000000: AT (0x80000000) { + .image 0x80000000: AT (0) { _gp = 0x00000000; @@ -28,4 +31,7 @@ *(.sdata); *(.sbss); + *(.comment); + *(.pdr); + hardcoded_ktext_size = .; LONG(ktext_end - ktext_start); @@ -43,4 +49,4 @@ kdata_end = .; - } = 0x00000000 + } } Index: arch/mips/src/console.c =================================================================== --- arch/mips/src/console.c (revision 38de8a54725cd7608700bfd9591eab3fc416d848) +++ arch/mips/src/console.c (revision 38de8a54725cd7608700bfd9591eab3fc416d848) @@ -0,0 +1,67 @@ +/* + * Copyright (C) 2005 Ondrej Palkovsky + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include + +static void (*putchar_func)(const char ch) = NULL; + +static void cons_putchar(const char ch) +{ + *((char *) VIDEORAM) = ch; +} + + +static void serial_putchar(const char ch) +{ + int i; + + if (ch=='\n') + putchar('\r'); + + /* Wait until transmit buffer empty */ + while (! ((*SERIAL_LSR) & (1< -#include +#include -struct { +struct data_t { char *vendor; char *model; -} imp_data[] = { +}; + +static struct data_t imp_data[] = { { "Invalid", "Invalid" }, /* 0x00 */ { "MIPS", "R2000" }, /* 0x01 */ @@ -79,4 +81,11 @@ }; +static struct data_t imp_data80[] = { + { "MIPS", "4Kc" }, /* 0x80 */ + {"Invalid","Invalid"}, /* 0x81 */ + {"Invalid","Invalid"}, /* 0x82 */ + {"MIPS","4Km & 4Kp"} /* 0x83 */ +}; + void cpu_arch_init(void) { @@ -91,5 +100,13 @@ void cpu_print_report(cpu_t *m) { + struct data_t *data; + + if (m->arch.imp_num & 0x80) { + data = &imp_data80[m->arch.imp_num & 0x7f]; + } else + data = &imp_data[m->arch.imp_num]; + printf("cpu%d: %s %s (rev=%d.%d, imp=%d)\n", - m->id, imp_data[m->arch.imp_num].vendor, imp_data[m->arch.imp_num].model, m->arch.rev_num >> 4, m->arch.rev_num & 0xf, m->arch.imp_num); + m->id, data->vendor, data->model, m->arch.rev_num >> 4, + m->arch.rev_num & 0xf, m->arch.imp_num); } Index: arch/mips/src/interrupt.c =================================================================== --- arch/mips/src/interrupt.c (revision b0edf3b2dee68a5024674c89cad7b78b9d0b5aa2) +++ arch/mips/src/interrupt.c (revision 38de8a54725cd7608700bfd9591eab3fc416d848) @@ -58,5 +58,4 @@ } - void interrupt(void) { @@ -84,7 +83,6 @@ break; case 7: /* Timer Interrupt */ - cp0_compare_write(cp0_compare_value); /* clear timer interrupt */ + cp0_compare_write(cp0_count_read() + cp0_compare_value); /* clear timer interrupt */ /* start counting over again */ - cp0_count_write(0); clock(); break; Index: arch/mips/src/mips.c =================================================================== --- arch/mips/src/mips.c (revision b0edf3b2dee68a5024674c89cad7b78b9d0b5aa2) +++ arch/mips/src/mips.c (revision 38de8a54725cd7608700bfd9591eab3fc416d848) @@ -34,4 +34,5 @@ #include #include +#include void arch_pre_mm_init(void) @@ -51,6 +52,7 @@ * Start hardware clock. */ - cp0_compare_write(cp0_compare_value); - cp0_count_write(0); + cp0_compare_write(cp0_compare_value + cp0_count_read()); + + console_init(); } Index: arch/mips/src/mm/tlb.c =================================================================== --- arch/mips/src/mm/tlb.c (revision b0edf3b2dee68a5024674c89cad7b78b9d0b5aa2) +++ arch/mips/src/mm/tlb.c (revision 38de8a54725cd7608700bfd9591eab3fc416d848) @@ -38,5 +38,17 @@ void tlb_refill(struct exception_regdump *pstate) { - panic("tlb_refill exception\n"); + char *symbol = ""; + char *sym2 = ""; + + if (THREAD) { + char *s = get_symtab_entry(pstate->epc); + if (s) + symbol = s; + s = get_symtab_entry(pstate->ra); + if (s) + sym2 = s; + } + panic("%X: tlb_refill exception at %X(%s<-%s)\n", cp0_badvaddr_read(), + pstate->epc, symbol,sym2); } Index: ch/mips/src/putchar.c =================================================================== --- arch/mips/src/putchar.c (revision b0edf3b2dee68a5024674c89cad7b78b9d0b5aa2) +++ (revision ) @@ -1,42 +1,0 @@ -/* - * Copyright (C) 2003-2004 Jakub Jermar - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include -#include - -#define VIDEORAM 0xB0000000 - -void putchar(const char ch) -{ -// __u32 status = cp0_status_read(); - -// cp0_status_write(cp0_status_read() | cp0_status_erl_error_bit); - *((char *) VIDEORAM) = ch; -// cp0_status_write(status); -} Index: contrib/conf/SPMIPS.simics =================================================================== --- contrib/conf/SPMIPS.simics (revision 38de8a54725cd7608700bfd9591eab3fc416d848) +++ contrib/conf/SPMIPS.simics (revision 38de8a54725cd7608700bfd9591eab3fc416d848) @@ -0,0 +1,14 @@ +run-python-file ../scripts/extrapath.py + +add-directory ../../import/mips +read-configuration spmips.conf + +set-pc (cpu0.load-binary ../../../SPARTAN/src/kernel.bin) + +# Setup uart to use 8 bits +@conf.tty0.lcr = 0xf; + +# Set date +rtc0.set-date-time 2001 01 01 01 01 01 +@century = 20 +@ignore=SIM_set_attribute_idx(conf.rtc0, "nvram", 0x32, century) Index: contrib/conf/spmips.conf =================================================================== --- contrib/conf/spmips.conf (revision 38de8a54725cd7608700bfd9591eab3fc416d848) +++ contrib/conf/spmips.conf (revision 38de8a54725cd7608700bfd9591eab3fc416d848) @@ -0,0 +1,252 @@ +OBJECT cpu0 TYPE mips-4kc { + freq-mhz: 10 + queue: cpu0 + physical-memory: phys-mem0 +} + +OBJECT phys-mem0 TYPE memory-space { + map: ((0x18000020, pic0, 0, 0x20, 1), + (0x18000021, pic0, 0, 0x21, 1), + (0x180000a0, pic0, 0, 0xa0, 1), + (0x180000a1, pic0, 0, 0xa1, 1), + (0x180004d0, pic0, 0, 0x4d0, 1), + (0x180004d1, pic0, 0, 0x4d1, 1), + (0x18000070, rtc0, 0, 0, 1), + (0x18000071, rtc0, 0, 1, 1), + (0x180003f8, tty0, 0, 0, 1), + (0x180003f9, tty0, 0, 1, 1), + (0x180003fa, tty0, 0, 2, 1), + (0x180003fb, tty0, 0, 3, 1), + (0x180003fc, tty0, 0, 4, 1), + (0x180003fd, tty0, 0, 5, 1), + (0x180003fe, tty0, 0, 6, 1), + (0x180003ff, tty0, 0, 7, 1), + (0x1c000000, hfs0, 0, 0, 16)) +} + +OBJECT cbus-space TYPE memory-space { + map: ((0x1f000000, malta0, 0, 0, 0xc00000), + (0x1fc00000, rom0, 0, 0, 0x400000)) +} + +OBJECT memory0 TYPE ram { + image: memory0-image +} +OBJECT memory0-image TYPE image { + queue: cpu0 + size: 0x08000000 +} +OBJECT rom0 TYPE rom { + image: rom0-image +} +OBJECT rom0-image TYPE image { + queue: cpu0 + size: 0x00400000 +} + +OBJECT tty0 TYPE NS16550 { + irq-dev: pic0 + irq-level: 4 + queue: cpu0 + console: con0 + recorder: rec0 +} + +OBJECT pic0 TYPE i8259x2 { + queue: cpu0 + irq-dev: gt64120-0 + # It seems like Linux expects the master 8259 to have VBA 0. + # Maybe that would be set up by YAMON? + vba: (0, 1) +} + +OBJECT con0 TYPE xterm-console { + title: "mips32-test-machine" + bg-color: "black" + fg-color: "green" + queue: cpu0 + device: tty0 + output-timeout: 120 +} + +OBJECT rtc0 TYPE DS12887 { + irq-dev: pic0 + irq-level: 8 + queue: cpu0 +} + +OBJECT malta0 TYPE malta { + console: display0 +} + +OBJECT display0 TYPE xterm-console { + title: "MALTA Display" + bg-color: "black" + fg-color: "red" + width: 8 + height: 1 + scrollbar: 0 + x11-font: "-*-*-*-r-*-*-*-240-*-*-m-*-*-*" + win32-font: "Lucida Console:Bold:48" + queue: cpu0 + output-timeout: 120 +} + +# PCI buses +OBJECT pci-bus0 TYPE pci-bus { + queue: cpu0 + bridge: gt64120-0-pci-0-0 + interrupt: gt64120-0-pci-0-0 + conf-space: pci-bus0-conf-space + memory-space: pci-bus0-memory-space + io-space: pci-bus0-io-space + + pci-devices: ((0, 0, gt64120-0-pci-0-0), + (0, 1, gt64120-0-pci-0-1)) +} + +OBJECT pci-bus0-conf-space TYPE memory-space { + queue: cpu0 +} + +OBJECT pci-bus1-conf-space TYPE memory-space { + queue: cpu0 +} + +OBJECT pci-bus0-memory-space TYPE memory-space { + queue: cpu0 +} + +OBJECT pci-bus1 TYPE pci-bus { + queue: cpu0 + bridge: gt64120-0-pci-1-0 + interrupt: gt64120-0-pci-1-0 + conf-space: pci-bus1-conf-space + memory-space: pci-bus1-memory-space + io-space: pci-bus1-io-space + + pci-devices: ((0, 0, gt64120-0-pci-1-0), + (0, 1, gt64120-0-pci-1-1)) +} + +OBJECT pci-bus1-memory-space TYPE memory-space { + queue: cpu0 +} + +OBJECT pci-bus0-io-space TYPE memory-space { + queue: cpu0 +} + +OBJECT pci-bus1-io-space TYPE memory-space { + queue: cpu0 +} + +# GT64120 chipset +OBJECT gt64120-0 TYPE GT64120 { + queue: cpu0 + cpu-mem: phys-mem0 + + pci-0-0: gt64120-0-pci-0-0 + pci-0-1: gt64120-0-pci-0-1 + pci-1-0: gt64120-0-pci-1-0 + pci-1-1: gt64120-0-pci-1-1 + + scs0: memory0 + cs3: cbus-space + bootcs: cbus-space + pci-0-conf: pci-bus0-conf-space + pci-0-io: pci-bus0-io-space + pci-0-memory: pci-bus0-memory-space + pci-1-conf: pci-bus1-conf-space + pci-1-io: pci-bus1-io-space + pci-1-memory: pci-bus1-memory-space + + irq-dev: cpu0 + irq-level: 2 + + # Little endian + cpu_interface_configuration: 0x00041000 + + # Map 128MB RAM. + scs10-high-decode-address: 0x40 + scs0-low-decode-address: 0x0 + scs0-high-decode-address: 0x7f + + # Map the internal registers at 0x1be00000. + internal-space-decode: 0xdf + + # Disable host-PCI mappings + pci-0-io-high-decode-address: 0 + pci-0-io-low-decode-address: 1 + pci-0-io-remap: 1 + pci-0-memory-0-high-decode-address: 0 + pci-0-memory-0-low-decode-address: 1 + pci-0-memory-0-remap: 1 + pci-0-memory-1-high-decode-address: 0 + pci-0-memory-1-low-decode-address: 1 + pci-0-memory-1-remap: 1 + pci-1-io-high-decode-address: 0 + pci-1-io-low-decode-address: 1 + pci-1-io-remap: 1 + pci-1-memory-0-high-decode-address: 0 + pci-1-memory-0-low-decode-address: 1 + pci-1-memory-0-remap: 1 + pci-1-memory-1-high-decode-address: 0 + pci-1-memory-1-low-decode-address: 1 + pci-1-memory-1-remap: 1 + + # Disable PCI-host mappings + pci-0-base-address-registers-enable: 0x1ff + pci-1-base-address-registers-enable: 0x1ff +} + +OBJECT gt64120-0-pci-0-0 TYPE GT64120-pci { + queue: cpu0 + + gt64120: gt64120-0 + bridge-num: 0 + function-num: 0 + + pci-bus: pci-bus0 +} + +OBJECT gt64120-0-pci-0-1 TYPE GT64120-pci { + queue: cpu0 + + gt64120: gt64120-0 + bridge-num: 0 + function-num: 1 + + pci-bus: pci-bus0 +} + +OBJECT gt64120-0-pci-1-0 TYPE GT64120-pci { + queue: cpu0 + + gt64120: gt64120-0 + bridge-num: 1 + function-num: 0 + + pci-bus: pci-bus1 +} + +OBJECT gt64120-0-pci-1-1 TYPE GT64120-pci { + queue: cpu0 + + gt64120: gt64120-0 + bridge-num: 1 + function-num: 1 + + pci-bus: pci-bus1 +} + +# Various +OBJECT rec0 TYPE recorder { +} + +OBJECT hfs0 TYPE hostfs { +} + +OBJECT sim TYPE sim { + handle-outside-memory: 1 +}