Index: kernel/arch/mips32/include/asm.h
===================================================================
--- kernel/arch/mips32/include/asm.h	(revision 0f3fc9b4dfadc676e3337514570c32d8d8c9b162)
+++ kernel/arch/mips32/include/asm.h	(revision 3802fcddbc0b5f3740b4c514f4e79bfe4d256c27)
@@ -37,5 +37,4 @@
 
 #include <arch/types.h>
-#include <typedefs.h>
 #include <config.h>
 
Index: kernel/arch/mips32/include/cache.h
===================================================================
--- kernel/arch/mips32/include/cache.h	(revision 0f3fc9b4dfadc676e3337514570c32d8d8c9b162)
+++ kernel/arch/mips32/include/cache.h	(revision 3802fcddbc0b5f3740b4c514f4e79bfe4d256c27)
@@ -36,5 +36,5 @@
 #define KERN_mips32_CACHE_H_
 
-#include <typedefs.h>
+#include <arch/exception.h>
 
 extern void cache_error(istate_t *istate);
Index: kernel/arch/mips32/include/context_offset.h
===================================================================
--- kernel/arch/mips32/include/context_offset.h	(revision 0f3fc9b4dfadc676e3337514570c32d8d8c9b162)
+++ kernel/arch/mips32/include/context_offset.h	(revision 3802fcddbc0b5f3740b4c514f4e79bfe4d256c27)
@@ -43,5 +43,5 @@
 #define OFFSET_GP      0x2c
 
-/* struct istate */
+/* istate_t */
 #define EOFFSET_AT     0x0
 #define EOFFSET_V0     0x4
Index: kernel/arch/mips32/include/cp0.h
===================================================================
--- kernel/arch/mips32/include/cp0.h	(revision 0f3fc9b4dfadc676e3337514570c32d8d8c9b162)
+++ kernel/arch/mips32/include/cp0.h	(revision 3802fcddbc0b5f3740b4c514f4e79bfe4d256c27)
@@ -37,12 +37,11 @@
 
 #include <arch/types.h>
-#include <arch/mm/tlb.h>
 
-#define cp0_status_ie_enabled_bit	(1<<0)
-#define cp0_status_exl_exception_bit	(1<<1)
-#define cp0_status_erl_error_bit	(1<<2)
-#define cp0_status_um_bit	        (1<<4)
-#define cp0_status_bev_bootstrap_bit	(1<<22)
-#define cp0_status_fpu_bit              (1<<29)
+#define cp0_status_ie_enabled_bit	(1 << 0)
+#define cp0_status_exl_exception_bit	(1 << 1)
+#define cp0_status_erl_error_bit	(1 << 2)
+#define cp0_status_um_bit	        (1 << 4)
+#define cp0_status_bev_bootstrap_bit	(1 << 22)
+#define cp0_status_fpu_bit              (1 << 29)
 
 #define cp0_status_im_shift		8
@@ -61,6 +60,6 @@
 #define cp0_mask_all_int() cp0_status_write(cp0_status_read() & ~(cp0_status_im_mask))
 #define cp0_unmask_all_int() cp0_status_write(cp0_status_read() | cp0_status_im_mask)
-#define cp0_mask_int(it) cp0_status_write(cp0_status_read() & ~(1<<(cp0_status_im_shift+(it))))
-#define cp0_unmask_int(it) cp0_status_write(cp0_status_read() | (1<<(cp0_status_im_shift+(it))))
+#define cp0_mask_int(it) cp0_status_write(cp0_status_read() & ~(1 << (cp0_status_im_shift + (it))))
+#define cp0_unmask_int(it) cp0_status_write(cp0_status_read() | (1 << (cp0_status_im_shift + (it))))
 
 #define GEN_READ_CP0(nm,reg) static inline uint32_t cp0_ ##nm##_read(void) \
Index: kernel/arch/mips32/include/cpu.h
===================================================================
--- kernel/arch/mips32/include/cpu.h	(revision 0f3fc9b4dfadc676e3337514570c32d8d8c9b162)
+++ kernel/arch/mips32/include/cpu.h	(revision 3802fcddbc0b5f3740b4c514f4e79bfe4d256c27)
@@ -37,4 +37,5 @@
 
 #include <arch/types.h>
+#include <arch/asm.h>
 
 typedef struct {
Index: kernel/arch/mips32/include/debugger.h
===================================================================
--- kernel/arch/mips32/include/debugger.h	(revision 0f3fc9b4dfadc676e3337514570c32d8d8c9b162)
+++ kernel/arch/mips32/include/debugger.h	(revision 3802fcddbc0b5f3740b4c514f4e79bfe4d256c27)
@@ -36,5 +36,4 @@
 #define KERN_mips32_DEBUGGER_H_
 
-#include <typedefs.h>
 #include <arch/exception.h>
 #include <arch/types.h>
Index: kernel/arch/mips32/include/exception.h
===================================================================
--- kernel/arch/mips32/include/exception.h	(revision 0f3fc9b4dfadc676e3337514570c32d8d8c9b162)
+++ kernel/arch/mips32/include/exception.h	(revision 3802fcddbc0b5f3740b4c514f4e79bfe4d256c27)
@@ -37,5 +37,4 @@
 
 #include <arch/types.h>
-#include <typedefs.h>
 #include <arch/cp0.h>
 
@@ -59,5 +58,5 @@
 #define EXC_VCED	31
 
-struct istate {
+typedef struct {
 	uint32_t at;
 	uint32_t v0;
@@ -96,5 +95,5 @@
 	uint32_t epc; /* cp0_epc */
 	uint32_t k1; /* We use it as thread-local pointer */
-};
+} istate_t;
 
 static inline void istate_set_retaddr(istate_t *istate, uintptr_t retaddr)
Index: kernel/arch/mips32/include/interrupt.h
===================================================================
--- kernel/arch/mips32/include/interrupt.h	(revision 0f3fc9b4dfadc676e3337514570c32d8d8c9b162)
+++ kernel/arch/mips32/include/interrupt.h	(revision 3802fcddbc0b5f3740b4c514f4e79bfe4d256c27)
@@ -36,4 +36,5 @@
 #define KERN_mips32_INTERRUPT_H_
 
+#include <typedefs.h>
 #include <arch/exception.h>
 
Index: kernel/arch/mips32/include/mm/as.h
===================================================================
--- kernel/arch/mips32/include/mm/as.h	(revision 0f3fc9b4dfadc676e3337514570c32d8d8c9b162)
+++ kernel/arch/mips32/include/mm/as.h	(revision 3802fcddbc0b5f3740b4c514f4e79bfe4d256c27)
@@ -43,8 +43,10 @@
 #define USER_ADDRESS_SPACE_END_ARCH		(unsigned long) 0x7fffffff
 
-#define USTACK_ADDRESS_ARCH	(0x80000000-PAGE_SIZE)
+#define USTACK_ADDRESS_ARCH	(0x80000000 - PAGE_SIZE)
 
 typedef struct {
 } as_arch_t;
+
+#include <genarch/mm/as_pt.h>
 
 #define as_constructor_arch(as, flags)		(as != as)
Index: kernel/arch/mips32/include/mm/page.h
===================================================================
--- kernel/arch/mips32/include/mm/page.h	(revision 0f3fc9b4dfadc676e3337514570c32d8d8c9b162)
+++ kernel/arch/mips32/include/mm/page.h	(revision 3802fcddbc0b5f3740b4c514f4e79bfe4d256c27)
@@ -44,9 +44,9 @@
 
 #ifndef __ASM__
-#  define KA2PA(x)	(((uintptr_t) (x)) - 0x80000000)
-#  define PA2KA(x)	(((uintptr_t) (x)) + 0x80000000)
+#	define KA2PA(x)	(((uintptr_t) (x)) - 0x80000000)
+#	define PA2KA(x)	(((uintptr_t) (x)) + 0x80000000)
 #else
-#  define KA2PA(x)	((x) - 0x80000000)
-#  define PA2KA(x)	((x) + 0x80000000)
+#	define KA2PA(x)	((x) - 0x80000000)
+#	define PA2KA(x)	((x) + 0x80000000)
 #endif
 
@@ -110,8 +110,6 @@
 #ifndef __ASM__
 
-#include <arch/mm/tlb.h>
-#include <mm/page.h>
-#include <arch/mm/frame.h>
-#include <arch/types.h>
+#include <mm/mm.h>
+#include <arch/exception.h>
 
 static inline int get_pt_flags(pte_t *pt, index_t i)
Index: kernel/arch/mips32/include/mm/tlb.h
===================================================================
--- kernel/arch/mips32/include/mm/tlb.h	(revision 0f3fc9b4dfadc676e3337514570c32d8d8c9b162)
+++ kernel/arch/mips32/include/mm/tlb.h	(revision 3802fcddbc0b5f3740b4c514f4e79bfe4d256c27)
@@ -37,5 +37,4 @@
 
 #include <arch/exception.h>
-#include <typedefs.h>
 
 #ifdef TLBCNT
@@ -53,10 +52,5 @@
 #define PAGE_CACHEABLE_EXC_WRITE	5
 
-typedef union entry_lo entry_lo_t;
-typedef union entry_hi entry_hi_t;
-typedef union page_mask page_mask_t;
-typedef union index tlb_index_t;
-
-union entry_lo {
+typedef union {
 	struct {
 #ifdef BIG_ENDIAN
@@ -77,20 +71,7 @@
 	} __attribute__ ((packed));
 	uint32_t value;
-};
+} entry_lo_t;
 
-/** Page Table Entry. */
-struct pte {
-	unsigned g : 1;			/**< Global bit. */
-	unsigned p : 1;			/**< Present bit. */
-	unsigned d : 1;			/**< Dirty bit. */
-	unsigned cacheable : 1;		/**< Cacheable bit. */
-	unsigned : 1;			/**< Unused. */
-	unsigned soft_valid : 1;	/**< Valid content even if not present. */
-	unsigned pfn : 24;		/**< Physical frame number. */
-	unsigned w : 1;			/**< Page writable bit. */
-	unsigned a : 1;			/**< Accessed bit. */
-};
-
-union entry_hi {
+typedef union {
 	struct {
 #ifdef BIG_ENDIAN
@@ -105,7 +86,7 @@
 	} __attribute__ ((packed));
 	uint32_t value;
-};
+} entry_hi_t;
 
-union page_mask {
+typedef union {
 	struct {
 #ifdef BIG_ENDIAN
@@ -120,7 +101,7 @@
 	} __attribute__ ((packed));
 	uint32_t value;
-};
+} page_mask_t;
 
-union index {
+typedef union {
 	struct {
 #ifdef BIG_ENDIAN
@@ -135,5 +116,5 @@
 	} __attribute__ ((packed));
 	uint32_t value;
-};
+} tlb_index_t;
 
 /** Probe TLB for Matching Entry
Index: kernel/arch/mips32/include/types.h
===================================================================
--- kernel/arch/mips32/include/types.h	(revision 0f3fc9b4dfadc676e3337514570c32d8d8c9b162)
+++ kernel/arch/mips32/include/types.h	(revision 3802fcddbc0b5f3740b4c514f4e79bfe4d256c27)
@@ -36,19 +36,24 @@
 #define KERN_mips32_TYPES_H_
 
-#define NULL	0
+#define NULL 0
+#define false 0
+#define true 1
 
 typedef signed char int8_t;
-typedef unsigned char uint8_t;
-
 typedef signed short int16_t;
-typedef unsigned short uint16_t;
-
-typedef unsigned long uint32_t;
 typedef signed long int32_t;
-
-typedef unsigned long long uint64_t;
 typedef signed long long int64_t;
 
+typedef unsigned char uint8_t;
+typedef unsigned short uint16_t;
+typedef unsigned long uint32_t;
+typedef unsigned long long uint64_t;
+
+typedef uint32_t size_t;
+typedef uint32_t count_t;
+typedef uint32_t index_t;
+
 typedef uint32_t uintptr_t;
+typedef uint32_t pfn_t;
 
 typedef uint32_t ipl_t;
@@ -57,7 +62,23 @@
 typedef int32_t native_t;
 
-typedef struct pte pte_t;
+typedef uint8_t bool;
+typedef uint64_t task_id_t;
+typedef uint32_t context_id_t;
 
-typedef uint32_t pfn_t;
+typedef int32_t inr_t;
+typedef int32_t devno_t;
+
+/** Page Table Entry. */
+typedef struct {
+	unsigned g : 1;			/**< Global bit. */
+	unsigned p : 1;			/**< Present bit. */
+	unsigned d : 1;			/**< Dirty bit. */
+	unsigned cacheable : 1;		/**< Cacheable bit. */
+	unsigned : 1;			/**< Unused. */
+	unsigned soft_valid : 1;	/**< Valid content even if not present. */
+	unsigned pfn : 24;		/**< Physical frame number. */
+	unsigned w : 1;			/**< Page writable bit. */
+	unsigned a : 1;			/**< Accessed bit. */
+} pte_t;
 
 #endif
Index: kernel/arch/mips32/src/cache.c
===================================================================
--- kernel/arch/mips32/src/cache.c	(revision 0f3fc9b4dfadc676e3337514570c32d8d8c9b162)
+++ kernel/arch/mips32/src/cache.c	(revision 3802fcddbc0b5f3740b4c514f4e79bfe4d256c27)
@@ -35,5 +35,4 @@
 #include <arch/cache.h>
 #include <arch/exception.h>
-#include <typedefs.h>
 #include <panic.h>
 
Index: kernel/arch/mips32/src/cpu/cpu.c
===================================================================
--- kernel/arch/mips32/src/cpu/cpu.c	(revision 0f3fc9b4dfadc676e3337514570c32d8d8c9b162)
+++ kernel/arch/mips32/src/cpu/cpu.c	(revision 3802fcddbc0b5f3740b4c514f4e79bfe4d256c27)
@@ -35,10 +35,6 @@
 #include <arch/cpu.h>
 #include <cpu.h>
-
 #include <arch.h>
-
 #include <arch/cp0.h>
-
-#include <typedefs.h>
 #include <print.h>	
 
Index: kernel/arch/mips32/src/ddi/ddi.c
===================================================================
--- kernel/arch/mips32/src/ddi/ddi.c	(revision 0f3fc9b4dfadc676e3337514570c32d8d8c9b162)
+++ kernel/arch/mips32/src/ddi/ddi.c	(revision 3802fcddbc0b5f3740b4c514f4e79bfe4d256c27)
@@ -36,5 +36,4 @@
 #include <proc/task.h>
 #include <arch/types.h>
-#include <typedefs.h>
 #include <security/cap.h>
 #include <arch.h>
Index: kernel/arch/mips32/src/drivers/msim.c
===================================================================
--- kernel/arch/mips32/src/drivers/msim.c	(revision 0f3fc9b4dfadc676e3337514570c32d8d8c9b162)
+++ kernel/arch/mips32/src/drivers/msim.c	(revision 3802fcddbc0b5f3740b4c514f4e79bfe4d256c27)
@@ -34,9 +34,9 @@
 
 #include <interrupt.h>
+#include <ipc/irq.h>
 #include <console/chardev.h>
 #include <arch/drivers/msim.h>
 #include <arch/cp0.h>
 #include <console/console.h>
-#include <ddi/irq.h>
 #include <sysinfo/sysinfo.h>
 
Index: kernel/arch/mips32/src/drivers/serial.c
===================================================================
--- kernel/arch/mips32/src/drivers/serial.c	(revision 0f3fc9b4dfadc676e3337514570c32d8d8c9b162)
+++ kernel/arch/mips32/src/drivers/serial.c	(revision 3802fcddbc0b5f3740b4c514f4e79bfe4d256c27)
@@ -35,8 +35,8 @@
 #include <interrupt.h>
 #include <arch/cp0.h>
+#include <ipc/irq.h>
 #include <arch/drivers/serial.h>
 #include <console/chardev.h>
 #include <console/console.h>
-#include <ddi/irq.h>
 
 #define SERIAL_IRQ 2
Index: kernel/arch/mips32/src/exception.c
===================================================================
--- kernel/arch/mips32/src/exception.c	(revision 0f3fc9b4dfadc676e3337514570c32d8d8c9b162)
+++ kernel/arch/mips32/src/exception.c	(revision 3802fcddbc0b5f3740b4c514f4e79bfe4d256c27)
@@ -35,4 +35,5 @@
 #include <arch/exception.h>
 #include <arch/interrupt.h>
+#include <arch/mm/tlb.h>
 #include <panic.h>
 #include <arch/cp0.h>
Index: kernel/arch/mips32/src/interrupt.c
===================================================================
--- kernel/arch/mips32/src/interrupt.c	(revision 0f3fc9b4dfadc676e3337514570c32d8d8c9b162)
+++ kernel/arch/mips32/src/interrupt.c	(revision 3802fcddbc0b5f3740b4c514f4e79bfe4d256c27)
@@ -42,5 +42,4 @@
 #include <ipc/sysipc.h>
 #include <ddi/device.h>
-#include <ddi/irq.h>
 
 #define IRQ_COUNT 8
Index: kernel/arch/mips32/src/mips32.c
===================================================================
--- kernel/arch/mips32/src/mips32.c	(revision 0f3fc9b4dfadc676e3337514570c32d8d8c9b162)
+++ kernel/arch/mips32/src/mips32.c	(revision 3802fcddbc0b5f3740b4c514f4e79bfe4d256c27)
@@ -37,5 +37,4 @@
 #include <arch/cp0.h>
 #include <arch/exception.h>
-#include <arch/asm.h>
 #include <mm/as.h>