Changeset 3526f4f3 in mainline
- Timestamp:
- 2024-05-21T13:42:25Z (8 months ago)
- Branches:
- master
- Children:
- b6f8f69
- Parents:
- 443695e
- git-author:
- Jiri Svoboda <jiri@…> (2024-05-20 18:42:12)
- git-committer:
- Jiri Svoboda <jiri@…> (2024-05-21 13:42:25)
- Location:
- kernel/arch
- Files:
-
- 2 edited
Legend:
- Unmodified
- Added
- Removed
-
kernel/arch/amd64/include/arch/mm/pat.h
r443695e r3526f4f3 1 1 /* 2 * Copyright (c) 2024 Jiri Svoboda 2 3 * Copyright (c) 2024 Jiří Zárevúcky 3 4 * All rights reserved. … … 50 51 } pat_type_t; 51 52 53 #ifndef PROCESSOR_i486 52 54 /** 53 55 * Assign caching type for a particular combination of PAT, … … 65 67 write_msr(MSR_IA32_PAT, r); 66 68 } 69 #endif 67 70 68 71 static inline bool pat_supported(void) -
kernel/arch/ia32/src/ia32.c
r443695e r3526f4f3 1 1 /* 2 * Copyright (c) 2024 Jiri Svoboda 2 3 * Copyright (c) 2001-2004 Jakub Jermar 3 * Copyright (c) 2009 Jiri Svoboda4 4 * Copyright (c) 2009 Martin Decky 5 5 * All rights reserved. … … 106 106 pm_init(); 107 107 108 #ifndef PROCESSOR_i486 108 109 /* Use PCD+PWT bit combination in PTE to mean write-combining mode. */ 109 110 if (pat_supported()) 110 111 pat_set_mapping(false, true, true, PAT_TYPE_WRITE_COMBINING); 112 #endif 111 113 112 114 if (config.cpu_active == 1) {
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