Changeset 3500f75 in mainline

Timestamp:

2010-05-21T22:50:45Z (14 years ago)

Author:

Martin Decky <martin@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

7c8e1e1

Parents:

339249f

Message:

ppc32: add interrupts_disabled(), simplify CPU identification

Location:

kernel/arch/ppc32

Files:

• include/asm.h (modified) (6 diffs)
• include/cpu.h (modified) (1 diff)
• include/cpuid.h (deleted)
• src/cpu/cpu.c (modified) (2 diffs)

kernel/arch/ppc32/include/asm.h

@@ -38 +38 @@
 #include <typedefs.h>
 #include <config.h>
+#include <arch/cpu.h>
+
+static inline uint32_t msr_read(void)
+{
+        uint32_t msr;
+        
+        asm volatile (
+                "mfmsr %[msr]\n"
+                : [msr] "=r" (msr)
+        );
+        
+        return msr;
+}
+
+static inline void msr_write(uint32_t msr)
+{
+        asm volatile (
+                "mtmsr %[msr]\n"
+                :: [msr] "r" (msr)
+        );
+}
 
 /** Enable interrupts.
@@ -45 +66 @@
  *
  * @return Old interrupt priority level.
+ *
  */
 static inline ipl_t interrupts_enable(void)
 {
-        ipl_t v;
-        ipl_t tmp;
-        
-        asm volatile (
-                "mfmsr %0\n"
-                "mfmsr %1\n"
-                "ori %1, %1, 1 << 15\n"
-                "mtmsr %1\n"
-                : "=r" (v), "=r" (tmp)
-        );
-        return v;
+        ipl_t ipl = msr_read();
+        msr_write(ipl | MSR_EE);
+        return ipl;
 }
 
@@ -67 +81 @@
  *
  * @return Old interrupt priority level.
+ *
  */
 static inline ipl_t interrupts_disable(void)
 {
-        ipl_t v;
-        ipl_t tmp;
-        
-        asm volatile (
-                "mfmsr %0\n"
-                "mfmsr %1\n"
-                "rlwinm %1, %1, 0, 17, 15\n"
-                "mtmsr %1\n"
-                : "=r" (v), "=r" (tmp)
-        );
-        return v;
+        ipl_t ipl = msr_read();
+        msr_write(ipl & (~MSR_EE));
+        return ipl;
 }
 
@@ -88 +95 @@
  *
  * @param ipl Saved interrupt priority level.
+ *
  */
 static inline void interrupts_restore(ipl_t ipl)
 {
-        ipl_t tmp;
-        
-        asm volatile (
-                "mfmsr %1\n"
-                "rlwimi  %0, %1, 0, 17, 15\n"
-                "cmpw 0, %0, %1\n"
-                "beq 0f\n"
-                "mtmsr %0\n"
-                "0:\n"
-                : "=r" (ipl), "=r" (tmp)
-                : "0" (ipl)
-                : "cr0"
-        );
+        msr_write((msr_read() & (~MSR_EE)) | (ipl & MSR_EE));
 }
 
@@ -111 +107 @@
  *
  * @return Current interrupt priority level.
+ *
  */
 static inline ipl_t interrupts_read(void)
 {
-        ipl_t v;
-        
-        asm volatile (
-                "mfmsr %0\n"
-                : "=r" (v)
-        );
-        return v;
+        return msr_read();
+}
+
+/** Check whether interrupts are disabled.
+ *
+ * @return True if interrupts are disabled.
+ *
+ */
+static inline bool interrupts_disabled(void)
+{
+        return ((msr_read() & MSR_EE) == 0);
 }
 
@@ -128 +129 @@
  * The stack is assumed to be STACK_SIZE bytes long.
  * The stack must start on page boundary.
+ *
  */
 static inline uintptr_t get_stack_base(void)
 {
-        uintptr_t v;
+        uintptr_t base;
         
         asm volatile (
-                "and %0, %%sp, %1\n"
-                : "=r" (v)
-                : "r" (~(STACK_SIZE - 1))
+                "and %[base], %%sp, %[mask]\n"
+                : [base] "=r" (base)
+                : [mask] "r" (~(STACK_SIZE - 1))
         );
-        return v;
+        
+        return base;
 }
 

kernel/arch/ppc32/include/cpu.h

@@ -36 +36 @@
 #define KERN_ppc32_CPU_H_
 
-#include <arch/asm.h>
+/* MSR bits */
+#define MSR_DR  (1 << 4)
+#define MSR_IR  (1 << 5)
+#define MSR_PR  (1 << 14)
+#define MSR_EE  (1 << 15)
+
+/* HID0 bits */
+#define HID0_STEN  (1 << 24)
+#define HID0_ICE   (1 << 15)
+#define HID0_DCE   (1 << 14)
+#define HID0_ICFI  (1 << 11)
+#define HID0_DCI   (1 << 10)
+
+#ifndef __ASM__
+
+#include <typedefs.h>
 
 typedef struct {
-        int version;
-        int revision;
-} cpu_arch_t;
-        
+        uint16_t version;
+        uint16_t revision;
+} __attribute__ ((packed)) cpu_arch_t;
+
+static inline void cpu_version(cpu_arch_t *info)
+{
+        asm volatile (
+                "mfpvr %[cpu_info]\n"
+                : [cpu_info] "=r" (*info)
+        );
+}
+
+#endif /* __ASM__ */
+
 #endif
 

kernel/arch/ppc32/src/cpu/cpu.c

@@ -34 +34 @@
 
 #include <arch/cpu.h>
-#include <arch/cpuid.h>
 #include <cpu.h>
 #include <arch.h>
@@ -45 +44 @@
 void cpu_identify(void)
 {
-        cpu_info_t info;
-        
-        cpu_version(&info);
-        CPU->arch.version = info.version;
-        CPU->arch.revision = info.revision;
+        cpu_version(&CPU->arch);
 }
 
-void cpu_print_report(cpu_t *m)
+void cpu_print_report(cpu_t *cpu)
 {
         const char *name;
         
-        switch (m->arch.version) {
+        switch (cpu->arch.version) {
                 case 8:
-                        name = " (PowerPC 750)";
+                        name = "PowerPC 750";
                         break;
                 case 9:
-                        name = " (PowerPC 604e)";
+                        name = "PowerPC 604e";
                         break;
                 case 0x81:
-                        name = " (PowerPC 8260)";
+                        name = "PowerPC 8260";
                         break;
                 case 0x8081:
-                        name = " (PowerPC 826xA)";
+                        name = "PowerPC 826xA";
                         break;
                 default:
-                        name = "";
+                        name = "unknown";
         }
         
-        printf("cpu%d: version=%d%s, revision=%d\n", m->id, m->arch.version, name, m->arch.revision);
+        printf("cpu%" PRIs ": version=%" PRIu16" (%s), revision=%" PRIu16 "\n", cpu->id,
+            cpu->arch.version, name, cpu->arch.revision);
 }