Index: kernel/arch/ia32/src/asm.S
===================================================================
--- kernel/arch/ia32/src/asm.S	(revision 06ae793150dfa79fa455b8d805a4e29fd70413fe)
+++ kernel/arch/ia32/src/asm.S	(revision 3061bc129a855122d429fbba1e623a521aaa164c)
@@ -139,5 +139,5 @@
  * and without the error word.
  */
-#define ISTATE_SOFT_SIZE	ISTATE_SIZE - (6 * 4) 
+#define ISTATE_SOFT_SIZE	ISTATE_SIZE - (6 * 4)
 
 /*
@@ -329,5 +329,5 @@
 	.else
 		/*
-		 * Interrupt: fake up an error word 
+		 * Interrupt: fake up an error word
 		 */
 		subl $(ISTATE_SOFT_SIZE + 4), %esp
@@ -433,5 +433,5 @@
 
 interrupt_handlers:
-.irp cnt, LIST_0_63 
+.irp cnt, LIST_0_63
 	handler \cnt
 .endr
Index: kernel/arch/ia32/src/atomic.S
===================================================================
--- kernel/arch/ia32/src/atomic.S	(revision 06ae793150dfa79fa455b8d805a4e29fd70413fe)
+++ kernel/arch/ia32/src/atomic.S	(revision 3061bc129a855122d429fbba1e623a521aaa164c)
@@ -34,5 +34,5 @@
 
 #
-# This is a bus-and-hyperthreading-friendly implementation of spinlock 
+# This is a bus-and-hyperthreading-friendly implementation of spinlock
 #
 FUNCTION_BEGIN(spinlock_arch)
@@ -42,5 +42,5 @@
 	movl 12(%esp),%ebx
 
-0:	
+0:
 	pause			# Pentium 4's with HT love this instruction
 	movl (%ebx),%eax
Index: kernel/arch/ia32/src/context.S
===================================================================
--- kernel/arch/ia32/src/context.S	(revision 06ae793150dfa79fa455b8d805a4e29fd70413fe)
+++ kernel/arch/ia32/src/context.S	(revision 3061bc129a855122d429fbba1e623a521aaa164c)
@@ -39,6 +39,6 @@
 #
 FUNCTION_BEGIN(context_save_arch)
-	movl 0(%esp), %eax	# save pc value into eax	
-	movl 4(%esp), %edx	# address of the context variable to save context to 
+	movl 0(%esp), %eax	# save pc value into eax
+	movl 4(%esp), %edx	# address of the context variable to save context to
 
 	# save registers to given structure
Index: kernel/arch/ia32/src/cpu/cpu.c
===================================================================
--- kernel/arch/ia32/src/cpu/cpu.c	(revision 06ae793150dfa79fa455b8d805a4e29fd70413fe)
+++ kernel/arch/ia32/src/cpu/cpu.c	(revision 3061bc129a855122d429fbba1e623a521aaa164c)
@@ -72,10 +72,10 @@
 void fpu_disable(void)
 {
-	write_cr0(read_cr0() & ~CR0_TS); 
+	write_cr0(read_cr0() & ~CR0_TS);
 }
 
 void fpu_enable(void)
 {
-	write_cr0(read_cr0() | CR0_TS); 
+	write_cr0(read_cr0() | CR0_TS);
 }
 
@@ -150,5 +150,5 @@
 void cpu_print_report(cpu_t* cpu)
 {
-	printf("cpu%u: (%s family=%u model=%u stepping=%u apicid=%u) %" PRIu16 
+	printf("cpu%u: (%s family=%u model=%u stepping=%u apicid=%u) %" PRIu16
 		" MHz\n", cpu->id, vendor_str[cpu->arch.vendor], cpu->arch.family,
 		cpu->arch.model, cpu->arch.stepping, cpu->arch.id, cpu->frequency_mhz);
Index: kernel/arch/ia32/src/smp/ap.S
===================================================================
--- kernel/arch/ia32/src/smp/ap.S	(revision 06ae793150dfa79fa455b8d805a4e29fd70413fe)
+++ kernel/arch/ia32/src/smp/ap.S	(revision 3061bc129a855122d429fbba1e623a521aaa164c)
@@ -47,5 +47,5 @@
 KDATA=16
 
-/* 
+/*
  * This piece of code is real-mode and is meant to be aligned at 4K boundary.
  * The requirement for such an alignment comes from MP Specification's
Index: kernel/arch/ia32/src/smp/smp.c
===================================================================
--- kernel/arch/ia32/src/smp/smp.c	(revision 06ae793150dfa79fa455b8d805a4e29fd70413fe)
+++ kernel/arch/ia32/src/smp/smp.c	(revision 3061bc129a855122d429fbba1e623a521aaa164c)
@@ -106,5 +106,5 @@
 
 	/*
-	 * SMP initialized, cpus array allocated. Assign each CPU its 
+	 * SMP initialized, cpus array allocated. Assign each CPU its
 	 * physical APIC ID.
 	 */
Index: kernel/arch/ia32/src/vreg.c
===================================================================
--- kernel/arch/ia32/src/vreg.c	(revision 06ae793150dfa79fa455b8d805a4e29fd70413fe)
+++ kernel/arch/ia32/src/vreg.c	(revision 3061bc129a855122d429fbba1e623a521aaa164c)
@@ -75,5 +75,5 @@
 	gs_load(GDT_SELECTOR(VREG_DES));
 
-	vreg_ptr = NULL; 
+	vreg_ptr = NULL;
 }