Changeset 2f40fe4 in mainline for arch/mips32/src


Ignore:
Timestamp:
2006-07-01T21:40:36Z (20 years ago)
Author:
Jakub Jermar <jakub@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
5eabe73
Parents:
7ee0e2f
Message:

Change cache_error exception to take istate * as a parameter.
Make cache_error() print epc in the panic message.
Do not rely on the compiler to generate 'nop' after 'beq' in atomic_add()
and put it there explicitly.
Indentation fixes and cosmetic changes.

Location:
arch/mips32/src
Files:
3 edited

Legend:

Unmodified
Added
Removed

  • arch/mips32/src/cache.c

    r7ee0e2f r2f40fe4  
    2727 */
    2828
    29  /** @addtogroup mips32
     29/** @addtogroup mips32 
    3030 * @{
    3131 */
    … …  
    3434
    3535#include <arch/cache.h>
     36#include <arch/exception.h>
     37#include <typedefs.h>
    3638#include <panic.h>
    3739
    38 void cache_error(void)
     40void cache_error(istate_t *istate)
    3941{
    40         panic("cache_error exception\n");
     42        panic("cache_error exception (epc=%p)\n", istate->epc);
    4143}
    4244
    43  /** @}
     45/** @}
    4446 */
    4547

  • arch/mips32/src/exception.c

    r7ee0e2f r2f40fe4  
    4949
    5050static char * exctable[] = {
    51         "Interrupt","TLB Modified","TLB Invalid","TLB Invalid Store",
    52                 "Address Error - load/instr. fetch",
    53                 "Address Error - store",
    54                 "Bus Error - fetch instruction",
    55                 "Bus Error - data reference",
    56                 "Syscall",
    57                 "BreakPoint",
    58                 "Reserved Instruction",
    59                 "Coprocessor Unusable",
    60                 "Arithmetic Overflow",
    61                 "Trap",
    62                 "Virtual Coherency - instruction",
    63                 "Floating Point",
    64                 NULL, NULL, NULL, NULL, NULL, NULL, NULL,
    65                 "WatchHi/WatchLo", /* 23 */
    66                 NULL, NULL, NULL, NULL, NULL, NULL, NULL,
    67                 "Virtual Coherency - data",
     51        "Interrupt",
     52        "TLB Modified",
     53        "TLB Invalid",
     54        "TLB Invalid Store",
     55        "Address Error - load/instr. fetch",
     56        "Address Error - store",
     57        "Bus Error - fetch instruction",
     58        "Bus Error - data reference",
     59        "Syscall",
     60        "BreakPoint",
     61        "Reserved Instruction",
     62        "Coprocessor Unusable",
     63        "Arithmetic Overflow",
     64        "Trap",
     65        "Virtual Coherency - instruction",
     66        "Floating Point",
     67        NULL, NULL, NULL, NULL, NULL, NULL, NULL,
     68        "WatchHi/WatchLo", /* 23 */
     69        NULL, NULL, NULL, NULL, NULL, NULL, NULL,
     70        "Virtual Coherency - data",
    6871};
    6972
    … …  
    175178/** @}
    176179 */
    177 

  • arch/mips32/src/start.S

    r7ee0e2f r2f40fe4  
    310310        add $sp, $k0, 0
    311311
    312         jal tlb_refill /* tlb_refill(register_space) */
     312        jal tlb_refill
    313313        add $a0, $sp, 0
    314314
    … …  
    325325
    326326        jal cache_error
    327         nop
     327        add $a0, $sp, 0
    328328
    329329        REGISTERS_LOAD $sp
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