Index: kernel/arch/mips32/include/arch/atomic.h
===================================================================
--- kernel/arch/mips32/include/arch/atomic.h	(revision 84239b1cd7c5ed286263ce4edb649da00b34b249)
+++ kernel/arch/mips32/include/arch/atomic.h	(revision 2f1c88e88f3d33245f94ca59d2b772d4dd5d1f56)
@@ -62,16 +62,16 @@
 
 	asm volatile (
-		"1:\n"
-		"	ll %0, %1\n"
-		"	addu %0, %0, %3\n"  /* same as addi, but never traps on overflow */
-		"	move %2, %0\n"
-		"	sc %0, %1\n"
-		"	beq %0, %4, 1b\n"   /* if the atomic operation failed, try again */
-		"	nop\n"
-		: "=&r" (tmp),
-		  "+m" (val->count),
-		  "=&r" (v)
-		: "r" (i),
-		  "i" (0)
+	    "1:\n"
+	    "	ll %0, %1\n"
+	    "	addu %0, %0, %3\n"  /* same as addi, but never traps on overflow */
+	    "	move %2, %0\n"
+	    "	sc %0, %1\n"
+	    "	beq %0, %4, 1b\n"   /* if the atomic operation failed, try again */
+	    "	nop\n"
+	    : "=&r" (tmp),
+	      "+m" (val->count),
+	      "=&r" (v)
+	    : "r" (i),
+	      "i" (0)
 	);
 
@@ -85,16 +85,16 @@
 
 	asm volatile (
-		"1:\n"
-		"	ll %2, %1\n"
-		"	bnez %2, 2f\n"
-		"	li %0, %3\n"
-		"	sc %0, %1\n"
-		"	beqz %0, 1b\n"
-		"	nop\n"
-		"2:\n"
-		: "=&r" (tmp),
-		  "+m" (val->count),
-		  "=&r" (v)
-		: "i" (1)
+	    "1:\n"
+	    "	ll %2, %1\n"
+	    "	bnez %2, 2f\n"
+	    "	li %0, %3\n"
+	    "	sc %0, %1\n"
+	    "	beqz %0, 1b\n"
+	    "	nop\n"
+	    "2:\n"
+	    : "=&r" (tmp),
+	      "+m" (val->count),
+	      "=&r" (v)
+	    : "i" (1)
 	);
 
@@ -105,5 +105,6 @@
 {
 	do {
-		while (val->count);
+		while (val->count)
+			;
 	} while (test_and_set(val));
 }
Index: kernel/arch/mips32/src/cpu/cpu.c
===================================================================
--- kernel/arch/mips32/src/cpu/cpu.c	(revision 84239b1cd7c5ed286263ce4edb649da00b34b249)
+++ kernel/arch/mips32/src/cpu/cpu.c	(revision 2f1c88e88f3d33245f94ca59d2b772d4dd5d1f56)
@@ -86,8 +86,8 @@
 static struct data_t imp_data80[] = {
 	{ "MIPS", "4Kc" },  /* 0x80 */
-	{"Invalid","Invalid"}, /* 0x81 */
-	{"Invalid","Invalid"}, /* 0x82 */
-	{"MIPS","4Km & 4Kp"}, /* 0x83 */
-	{ NULL, NULL}
+	{ "Invalid", "Invalid" }, /* 0x81 */
+	{ "Invalid", "Invalid" }, /* 0x82 */
+	{ "MIPS", "4Km & 4Kp" }, /* 0x83 */
+	{ NULL, NULL }
 };
 
@@ -129,6 +129,6 @@
 
 	printf("cpu%u: %s %s (rev=%d.%d, imp=%d)\n",
-		m->id, data->vendor, data->model, m->arch.rev_num >> 4,
-		m->arch.rev_num & 0x0f, m->arch.imp_num);
+	    m->id, data->vendor, data->model, m->arch.rev_num >> 4,
+	    m->arch.rev_num & 0x0f, m->arch.imp_num);
 }
 
Index: kernel/arch/mips32/src/mach/malta/malta.c
===================================================================
--- kernel/arch/mips32/src/mach/malta/malta.c	(revision 84239b1cd7c5ed286263ce4edb649da00b34b249)
+++ kernel/arch/mips32/src/mach/malta/malta.c	(revision 2f1c88e88f3d33245f94ca59d2b772d4dd5d1f56)
@@ -84,7 +84,7 @@
 {
 
-        const char ch = (char) wch;
+	const char ch = (char) wch;
 
-        (*yamon_print_count)(0, &ch, 1);
+	(*yamon_print_count)(0, &ch, 1);
 }
 
Index: kernel/arch/mips32/src/mips32.c
===================================================================
--- kernel/arch/mips32/src/mips32.c	(revision 84239b1cd7c5ed286263ce4edb649da00b34b249)
+++ kernel/arch/mips32/src/mips32.c	(revision 2f1c88e88f3d33245f94ca59d2b772d4dd5d1f56)
@@ -74,5 +74,5 @@
 
 /* Stack pointer saved when entering user mode */
-uintptr_t supervisor_sp __attribute__ ((section (".text")));
+uintptr_t supervisor_sp __attribute__((section(".text")));
 
 size_t cpu_count = 0;
@@ -172,5 +172,6 @@
 	    (uintptr_t) kernel_uarg->uspace_entry);
 
-	while (1);
+	while (1)
+		;
 }
 
@@ -194,5 +195,6 @@
 {
 	___halt();
-	while (1);
+	while (1)
+		;
 }
 
Index: kernel/arch/mips32/src/mm/frame.c
===================================================================
--- kernel/arch/mips32/src/mm/frame.c	(revision 84239b1cd7c5ed286263ce4edb649da00b34b249)
+++ kernel/arch/mips32/src/mm/frame.c	(revision 2f1c88e88f3d33245f94ca59d2b772d4dd5d1f56)
@@ -290,5 +290,5 @@
 	for (i = 0; i < phys_regions_count; i++) {
 		printf("%#010x %10u\n",
-			PFN2ADDR(phys_regions[i].start), PFN2ADDR(phys_regions[i].count));
+		    PFN2ADDR(phys_regions[i].start), PFN2ADDR(phys_regions[i].count));
 	}
 }