Index: kernel/arch/ia32/include/arch/atomic.h
===================================================================
--- kernel/arch/ia32/include/arch/atomic.h	(revision fd57745cd4811832fa23ba1cef7638038244f2b5)
+++ kernel/arch/ia32/include/arch/atomic.h	(revision 2f1c88e88f3d33245f94ca59d2b772d4dd5d1f56)
@@ -46,11 +46,11 @@
 #ifdef CONFIG_SMP
 	asm volatile (
-		"lock incl %[count]\n"
-		: [count] "+m" (val->count)
-	);
-#else
-	asm volatile (
-		"incl %[count]\n"
-		: [count] "+m" (val->count)
+	    "lock incl %[count]\n"
+	    : [count] "+m" (val->count)
+	);
+#else
+	asm volatile (
+	    "incl %[count]\n"
+	    : [count] "+m" (val->count)
 	);
 #endif /* CONFIG_SMP */
@@ -61,11 +61,11 @@
 #ifdef CONFIG_SMP
 	asm volatile (
-		"lock decl %[count]\n"
-		: [count] "+m" (val->count)
-	);
-#else
-	asm volatile (
-		"decl %[count]\n"
-		: [count] "+m" (val->count)
+	    "lock decl %[count]\n"
+	    : [count] "+m" (val->count)
+	);
+#else
+	asm volatile (
+	    "decl %[count]\n"
+	    : [count] "+m" (val->count)
 	);
 #endif /* CONFIG_SMP */
@@ -77,7 +77,7 @@
 
 	asm volatile (
-		"lock xaddl %[r], %[count]\n"
-		: [count] "+m" (val->count),
-		  [r] "+r" (r)
+	    "lock xaddl %[r], %[count]\n"
+	    : [count] "+m" (val->count),
+	      [r] "+r" (r)
 	);
 
@@ -90,7 +90,7 @@
 
 	asm volatile (
-		"lock xaddl %[r], %[count]\n"
-		: [count] "+m" (val->count),
-		  [r] "+r" (r)
+	    "lock xaddl %[r], %[count]\n"
+	    : [count] "+m" (val->count),
+	      [r] "+r" (r)
 	);
 
@@ -106,7 +106,7 @@
 
 	asm volatile (
-		"xchgl %[v], %[count]\n"
-		: [v] "+r" (v),
-		  [count] "+m" (val->count)
+	    "xchgl %[v], %[count]\n"
+	    : [v] "+r" (v),
+	      [count] "+m" (val->count)
 	);
 
@@ -122,18 +122,18 @@
 	preemption_disable();
 	asm volatile (
-		"0:\n"
+	    "0:\n"
 #ifndef PROCESSOR_i486
-		"pause\n"        /* Pentium 4's HT love this instruction */
-#endif
-		"mov %[count], %[tmp]\n"
-		"testl %[tmp], %[tmp]\n"
-		"jnz 0b\n"       /* lightweight looping on locked spinlock */
-
-		"incl %[tmp]\n"  /* now use the atomic operation */
-		"xchgl %[count], %[tmp]\n"
-		"testl %[tmp], %[tmp]\n"
-		"jnz 0b\n"
-		: [count] "+m" (val->count),
-		  [tmp] "=&r" (tmp)
+	    "pause\n"        /* Pentium 4's HT love this instruction */
+#endif
+	    "mov %[count], %[tmp]\n"
+	    "testl %[tmp], %[tmp]\n"
+	    "jnz 0b\n"       /* lightweight looping on locked spinlock */
+
+	    "incl %[tmp]\n"  /* now use the atomic operation */
+	    "xchgl %[count], %[tmp]\n"
+	    "testl %[tmp], %[tmp]\n"
+	    "jnz 0b\n"
+	    : [count] "+m" (val->count),
+	      [tmp] "=&r" (tmp)
 	);
 
Index: kernel/arch/ia32/include/arch/barrier.h
===================================================================
--- kernel/arch/ia32/include/arch/barrier.h	(revision fd57745cd4811832fa23ba1cef7638038244f2b5)
+++ kernel/arch/ia32/include/arch/barrier.h	(revision 2f1c88e88f3d33245f94ca59d2b772d4dd5d1f56)
@@ -56,16 +56,16 @@
 #ifndef __PIC__
 	asm volatile (
-		"xorl %%eax, %%eax\n"
-		"cpuid\n"
-		::: "eax", "ebx", "ecx", "edx", "memory"
+	    "xorl %%eax, %%eax\n"
+	    "cpuid\n"
+	    ::: "eax", "ebx", "ecx", "edx", "memory"
 	);
 #else
 	/* Must not clobber PIC register ebx */
 	asm volatile (
-		"movl %%ebx, %%esi\n"
-		"xorl %%eax, %%eax\n"
-		"cpuid\n"
-		"movl %%esi, %%ebx\n"
-		::: "eax", "ecx", "edx", "esi", "memory"
+	    "movl %%ebx, %%esi\n"
+	    "xorl %%eax, %%eax\n"
+	    "cpuid\n"
+	    "movl %%esi, %%ebx\n"
+	    ::: "eax", "ecx", "edx", "esi", "memory"
 	);
 #endif
@@ -73,27 +73,27 @@
 
 #if defined(CONFIG_FENCES_P4)
-	#define memory_barrier()  asm volatile ("mfence\n" ::: "memory")
-	#define read_barrier()    asm volatile ("lfence\n" ::: "memory")
-	#ifdef CONFIG_WEAK_MEMORY
-		#define write_barrier()  asm volatile ("sfence\n" ::: "memory")
-	#else
-		#define write_barrier()  asm volatile ("" ::: "memory");
-	#endif
+#define memory_barrier()  asm volatile ("mfence\n" ::: "memory")
+#define read_barrier()    asm volatile ("lfence\n" ::: "memory")
+#ifdef CONFIG_WEAK_MEMORY
+#define write_barrier()  asm volatile ("sfence\n" ::: "memory")
+#else
+#define write_barrier()  asm volatile ("" ::: "memory");
+#endif
 #elif defined(CONFIG_FENCES_P3)
-	#define memory_barrier()  cpuid_serialization()
-	#define read_barrier()    cpuid_serialization()
-	#ifdef CONFIG_WEAK_MEMORY
-		#define write_barrier()  asm volatile ("sfence\n" ::: "memory")
-	#else
-		#define write_barrier()  asm volatile ("" ::: "memory");
-	#endif
+#define memory_barrier()  cpuid_serialization()
+#define read_barrier()    cpuid_serialization()
+#ifdef CONFIG_WEAK_MEMORY
+#define write_barrier()  asm volatile ("sfence\n" ::: "memory")
 #else
-	#define memory_barrier()  cpuid_serialization()
-	#define read_barrier()    cpuid_serialization()
-	#ifdef CONFIG_WEAK_MEMORY
-		#define write_barrier()  cpuid_serialization()
-	#else
-		#define write_barrier()  asm volatile ("" ::: "memory");
-	#endif
+#define write_barrier()  asm volatile ("" ::: "memory");
+#endif
+#else
+#define memory_barrier()  cpuid_serialization()
+#define read_barrier()    cpuid_serialization()
+#ifdef CONFIG_WEAK_MEMORY
+#define write_barrier()  cpuid_serialization()
+#else
+#define write_barrier()  asm volatile ("" ::: "memory");
+#endif
 #endif
 
Index: kernel/arch/ia32/include/arch/cpuid.h
===================================================================
--- kernel/arch/ia32/include/arch/cpuid.h	(revision fd57745cd4811832fa23ba1cef7638038244f2b5)
+++ kernel/arch/ia32/include/arch/cpuid.h	(revision 2f1c88e88f3d33245f94ca59d2b772d4dd5d1f56)
@@ -85,20 +85,20 @@
 
 	asm volatile (
-		"pushf\n"                      /* read flags */
-		"popl %[ret]\n"
-		"movl %[ret], %[val]\n"
+	    "pushf\n"                      /* read flags */
+	    "popl %[ret]\n"
+	    "movl %[ret], %[val]\n"
 
-		"xorl %[eflags_id], %[val]\n"  /* swap the ID bit */
+	    "xorl %[eflags_id], %[val]\n"  /* swap the ID bit */
 
-		"pushl %[val]\n"               /* propagate the change into flags */
-		"popf\n"
-		"pushf\n"
-		"popl %[val]\n"
+	    "pushl %[val]\n"               /* propagate the change into flags */
+	    "popf\n"
+	    "pushf\n"
+	    "popl %[val]\n"
 
-		"andl %[eflags_id], %[ret]\n"  /* interrested only in ID bit */
-		"andl %[eflags_id], %[val]\n"
-		"xorl %[val], %[ret]\n"
-		: [ret] "=r" (ret), [val] "=r" (val)
-		: [eflags_id] "i" (EFLAGS_ID)
+	    "andl %[eflags_id], %[ret]\n"  /* interrested only in ID bit */
+	    "andl %[eflags_id], %[val]\n"
+	    "xorl %[val], %[ret]\n"
+	    : [ret] "=r" (ret), [val] "=r" (val)
+	    : [eflags_id] "i" (EFLAGS_ID)
 	);
 
@@ -109,8 +109,8 @@
 {
 	asm volatile (
-		"cpuid\n"
-		: "=a" (info->cpuid_eax), "=b" (info->cpuid_ebx),
-		  "=c" (info->cpuid_ecx), "=d" (info->cpuid_edx)
-		: "a" (cmd)
+	    "cpuid\n"
+	    : "=a" (info->cpuid_eax), "=b" (info->cpuid_ebx),
+	      "=c" (info->cpuid_ecx), "=d" (info->cpuid_edx)
+	    : "a" (cmd)
 	);
 }
Index: kernel/arch/ia32/include/arch/cycle.h
===================================================================
--- kernel/arch/ia32/include/arch/cycle.h	(revision fd57745cd4811832fa23ba1cef7638038244f2b5)
+++ kernel/arch/ia32/include/arch/cycle.h	(revision 2f1c88e88f3d33245f94ca59d2b772d4dd5d1f56)
@@ -45,7 +45,7 @@
 	uint64_t v;
 
-	asm volatile(
-		"rdtsc\n"
-		: "=A" (v)
+	asm volatile (
+	    "rdtsc\n"
+	    : "=A" (v)
 	);
 
Index: kernel/arch/ia32/include/arch/mm/page.h
===================================================================
--- kernel/arch/ia32/include/arch/mm/page.h	(revision fd57745cd4811832fa23ba1cef7638038244f2b5)
+++ kernel/arch/ia32/include/arch/mm/page.h	(revision 2f1c88e88f3d33245f94ca59d2b772d4dd5d1f56)
@@ -178,5 +178,5 @@
 	unsigned avl : 2;
 	unsigned frame_address : 20;
-} __attribute__ ((packed)) pte_t;
+} __attribute__((packed)) pte_t;
 
 NO_TRACE static inline unsigned int get_pt_flags(pte_t *pt, size_t i)
Index: kernel/arch/ia32/include/arch/pm.h
===================================================================
--- kernel/arch/ia32/include/arch/pm.h	(revision fd57745cd4811832fa23ba1cef7638038244f2b5)
+++ kernel/arch/ia32/include/arch/pm.h	(revision 2f1c88e88f3d33245f94ca59d2b772d4dd5d1f56)
@@ -89,26 +89,26 @@
 	uint16_t limit;
 	uint32_t base;
-} __attribute__ ((packed)) ptr_16_32_t;
+} __attribute__((packed)) ptr_16_32_t;
 
 typedef struct {
-	unsigned limit_0_15: 16;
-	unsigned base_0_15: 16;
-	unsigned base_16_23: 8;
-	unsigned access: 8;
-	unsigned limit_16_19: 4;
-	unsigned available: 1;
-	unsigned unused: 1;
-	unsigned special: 1;
+	unsigned limit_0_15 : 16;
+	unsigned base_0_15 : 16;
+	unsigned base_16_23 : 8;
+	unsigned access : 8;
+	unsigned limit_16_19 : 4;
+	unsigned available : 1;
+	unsigned unused : 1;
+	unsigned special : 1;
 	unsigned granularity : 1;
-	unsigned base_24_31: 8;
-} __attribute__ ((packed)) descriptor_t;
+	unsigned base_24_31 : 8;
+} __attribute__((packed)) descriptor_t;
 
 typedef struct {
-	unsigned offset_0_15: 16;
-	unsigned selector: 16;
-	unsigned unused: 8;
-	unsigned access: 8;
-	unsigned offset_16_31: 16;
-} __attribute__ ((packed)) idescriptor_t;
+	unsigned offset_0_15 : 16;
+	unsigned selector : 16;
+	unsigned unused : 8;
+	unsigned access : 8;
+	unsigned offset_16_31 : 16;
+} __attribute__((packed)) idescriptor_t;
 
 typedef struct {
@@ -152,5 +152,5 @@
 	uint16_t iomap_base;
 	uint8_t iomap[TSS_IOMAP_SIZE];
-} __attribute__ ((packed)) tss_t;
+} __attribute__((packed)) tss_t;
 
 extern ptr_16_32_t gdtr;
Index: kernel/arch/ia32/include/arch/smp/apic.h
===================================================================
--- kernel/arch/ia32/include/arch/smp/apic.h	(revision fd57745cd4811832fa23ba1cef7638038244f2b5)
+++ kernel/arch/ia32/include/arch/smp/apic.h	(revision 2f1c88e88f3d33245f94ca59d2b772d4dd5d1f56)
@@ -128,5 +128,5 @@
 			unsigned int shorthand : 2;     /**< Destination Shorthand. */
 			unsigned int : 12;              /**< Reserved. */
-		} __attribute__ ((packed));
+		} __attribute__((packed));
 	};
 	union {
@@ -135,7 +135,7 @@
 			unsigned int : 24;  /**< Reserved. */
 			uint8_t dest;       /**< Destination field. */
-		} __attribute__ ((packed));
+		} __attribute__((packed));
 	};
-} __attribute__ ((packed)) icr_t;
+} __attribute__((packed)) icr_t;
 
 /* End Of Interrupt. */
@@ -158,5 +158,5 @@
 		unsigned int illegal_register_address : 1;
 		unsigned int : 24;
-	} __attribute__ ((packed));
+	} __attribute__((packed));
 } esr_t;
 
@@ -169,5 +169,5 @@
 		unsigned int pri_sc : 4;  /**< Task Priority Sub-Class. */
 		unsigned int pri : 4;     /**< Task Priority. */
-	} __attribute__ ((packed));
+	} __attribute__((packed));
 } tpr_t;
 
@@ -182,5 +182,5 @@
 		unsigned int focus_checking : 1;  /**< Focus Processor Checking. */
 		unsigned int : 22;                /**< Reserved. */
-	} __attribute__ ((packed));
+	} __attribute__((packed));
 } svr_t;
 
@@ -193,5 +193,5 @@
 		unsigned int div_value : 4;  /**< Divide Value, bit 2 is always 0. */
 		unsigned int : 28;           /**< Reserved. */
-	} __attribute__ ((packed));
+	} __attribute__((packed));
 } tdcr_t;
 
@@ -215,5 +215,5 @@
 		unsigned int mode : 1;    /**< Timer Mode. */
 		unsigned int : 14;        /**< Reserved. */
-	} __attribute__ ((packed));
+	} __attribute__((packed));
 } lvt_tm_t;
 
@@ -234,5 +234,5 @@
 		unsigned int masked : 1;        /**< Interrupt Mask. */
 		unsigned int : 15;              /**< Reserved. */
-	} __attribute__ ((packed));
+	} __attribute__((packed));
 } lvt_lint_t;
 
@@ -249,5 +249,5 @@
 		unsigned int masked : 1;  /**< Interrupt Mask. */
 		unsigned int : 15;        /**< Reserved. */
-	} __attribute__ ((packed));
+	} __attribute__((packed));
 } lvt_error_t;
 
@@ -260,5 +260,5 @@
 		unsigned int : 24;  /**< Reserved. */
 		uint8_t apic_id;    /**< Local APIC ID. */
-	} __attribute__ ((packed));
+	} __attribute__((packed));
 } l_apic_id_t;
 
@@ -279,5 +279,5 @@
 		unsigned int : 24;  /**< Reserved. */
 		uint8_t id;         /**< Logical APIC ID. */
-	} __attribute__ ((packed));
+	} __attribute__((packed));
 } ldr_t;
 
@@ -290,5 +290,5 @@
 		unsigned int : 28;       /**< Reserved, all ones. */
 		unsigned int model : 4;  /**< Model. */
-	} __attribute__ ((packed));
+	} __attribute__((packed));
 } dfr_t;
 
@@ -308,5 +308,5 @@
 		uint8_t reg_addr;   /**< APIC Register Address. */
 		unsigned int : 24;  /**< Reserved. */
-	} __attribute__ ((packed));
+	} __attribute__((packed));
 } io_regsel_t;
 
@@ -325,5 +325,5 @@
 			unsigned int masked : 1;        /**< Interrupt Mask. */
 			unsigned int : 15;              /**< Reserved. */
-		} __attribute__ ((packed));
+		} __attribute__((packed));
 	};
 	union {
@@ -332,8 +332,8 @@
 			unsigned int : 24;  /**< Reserved. */
 			uint8_t dest : 8;   /**< Destination Field. */
-		} __attribute__ ((packed));
+		} __attribute__((packed));
 	};
 
-} __attribute__ ((packed)) io_redirection_reg_t;
+} __attribute__((packed)) io_redirection_reg_t;
 
 
@@ -345,5 +345,5 @@
 		unsigned int apic_id : 4;  /**< IO APIC ID. */
 		unsigned int : 4;          /**< Reserved. */
-	} __attribute__ ((packed));
+	} __attribute__((packed));
 } io_apic_id_t;
 
Index: kernel/arch/ia32/include/arch/smp/mps.h
===================================================================
--- kernel/arch/ia32/include/arch/smp/mps.h	(revision fd57745cd4811832fa23ba1cef7638038244f2b5)
+++ kernel/arch/ia32/include/arch/smp/mps.h	(revision 2f1c88e88f3d33245f94ca59d2b772d4dd5d1f56)
@@ -55,5 +55,5 @@
 	uint8_t mpfib4;
 	uint8_t mpfib5;
-} __attribute__ ((packed));
+} __attribute__((packed));
 
 struct mps_ct {
@@ -72,5 +72,5 @@
 	uint8_t reserved;
 	uint8_t base_table[0];
-} __attribute__ ((packed));
+} __attribute__((packed));
 
 struct __processor_entry {
@@ -82,5 +82,5 @@
 	uint32_t feature_flags;
 	uint32_t reserved[2];
-} __attribute__ ((packed));
+} __attribute__((packed));
 
 struct __bus_entry {
@@ -88,5 +88,5 @@
 	uint8_t bus_id;
 	uint8_t bus_type[6];
-} __attribute__ ((packed));
+} __attribute__((packed));
 
 struct __io_apic_entry {
@@ -96,5 +96,5 @@
 	uint8_t io_apic_flags;
 	uint32_t io_apic;
-} __attribute__ ((packed));
+} __attribute__((packed));
 
 struct __io_intr_entry {
@@ -107,5 +107,5 @@
 	uint8_t dst_io_apic_id;
 	uint8_t dst_io_apic_pin;
-} __attribute__ ((packed));
+} __attribute__((packed));
 
 struct __l_intr_entry {
@@ -118,5 +118,5 @@
 	uint8_t dst_l_apic_id;
 	uint8_t dst_l_apic_pin;
-} __attribute__ ((packed));
+} __attribute__((packed));
 
 extern struct smp_config_operations mps_config_operations;
Index: kernel/arch/ia32/src/fpu_context.c
===================================================================
--- kernel/arch/ia32/src/fpu_context.c	(revision fd57745cd4811832fa23ba1cef7638038244f2b5)
+++ kernel/arch/ia32/src/fpu_context.c	(revision 2f1c88e88f3d33245f94ca59d2b772d4dd5d1f56)
@@ -71,6 +71,6 @@
 {
 	asm volatile (
-		"fnsave %[fctx]"
-		: [fctx] "=m" (fctx->fpu)
+	    "fnsave %[fctx]"
+	    : [fctx] "=m" (fctx->fpu)
 	);
 }
@@ -79,6 +79,6 @@
 {
 	asm volatile (
-		"frstor %[fctx]"
-		: [fctx] "=m" (fctx->fpu)
+	    "frstor %[fctx]"
+	    : [fctx] "=m" (fctx->fpu)
 	);
 }
@@ -87,6 +87,6 @@
 {
 	asm volatile (
-		"fxsave %[fctx]"
-		: [fctx] "=m" (fctx->fpu)
+	    "fxsave %[fctx]"
+	    : [fctx] "=m" (fctx->fpu)
 	);
 }
@@ -95,6 +95,6 @@
 {
 	asm volatile (
-		"fxrstor %[fctx]"
-		: [fctx] "=m" (fctx->fpu)
+	    "fxrstor %[fctx]"
+	    : [fctx] "=m" (fctx->fpu)
 	);
 }
@@ -131,12 +131,12 @@
 
 	asm volatile (
-		"fninit\n"
-		"stmxcsr %[help0]\n"
-		"mov %[help0], %[help1]\n"
-		"or %[magic], %[help1]\n"
-		"mov %[help1], %[help0]\n"
-		"ldmxcsr %[help0]\n"
-		: [help0] "+m" (help0), [help1] "+r" (help1)
-		: [magic] "i" (X87_ALL_MASK)
+	    "fninit\n"
+	    "stmxcsr %[help0]\n"
+	    "mov %[help0], %[help1]\n"
+	    "or %[magic], %[help1]\n"
+	    "mov %[help1], %[help0]\n"
+	    "ldmxcsr %[help0]\n"
+	    : [help0] "+m" (help0), [help1] "+r" (help1)
+	    : [magic] "i" (X87_ALL_MASK)
 	);
 }
Index: kernel/arch/ia32/src/interrupt.c
===================================================================
--- kernel/arch/ia32/src/interrupt.c	(revision fd57745cd4811832fa23ba1cef7638038244f2b5)
+++ kernel/arch/ia32/src/interrupt.c	(revision 2f1c88e88f3d33245f94ca59d2b772d4dd5d1f56)
@@ -62,7 +62,7 @@
  */
 
-void (* disable_irqs_function)(uint16_t irqmask) = NULL;
-void (* enable_irqs_function)(uint16_t irqmask) = NULL;
-void (* eoi_function)(void) = NULL;
+void (*disable_irqs_function)(uint16_t irqmask) = NULL;
+void (*enable_irqs_function)(uint16_t irqmask) = NULL;
+void (*eoi_function)(void) = NULL;
 const char *irqs_info = NULL;
 
@@ -146,6 +146,6 @@
 	uint32_t mxcsr;
 	asm volatile (
-		"stmxcsr %[mxcsr]\n"
-		: [mxcsr] "=m" (mxcsr)
+	    "stmxcsr %[mxcsr]\n"
+	    : [mxcsr] "=m" (mxcsr)
 	);
 
Index: kernel/arch/ia32/src/mm/frame.c
===================================================================
--- kernel/arch/ia32/src/mm/frame.c	(revision fd57745cd4811832fa23ba1cef7638038244f2b5)
+++ kernel/arch/ia32/src/mm/frame.c	(revision 2f1c88e88f3d33245f94ca59d2b772d4dd5d1f56)
@@ -142,5 +142,5 @@
 			name = "invalid";
 
-		printf("%#018" PRIx64 " %#018" PRIx64" %s\n", e820table[i].base_address,
+		printf("%#018" PRIx64 " %#018" PRIx64 " %s\n", e820table[i].base_address,
 		    e820table[i].size, name);
 	}
Index: kernel/arch/ia32/src/smp/apic.c
===================================================================
--- kernel/arch/ia32/src/smp/apic.c	(revision fd57745cd4811832fa23ba1cef7638038244f2b5)
+++ kernel/arch/ia32/src/smp/apic.c	(revision 2f1c88e88f3d33245f94ca59d2b772d4dd5d1f56)
@@ -482,5 +482,6 @@
 	l_apic[ICRT] = 0xffffffff;
 
-	while (l_apic[CCRT] == t1);
+	while (l_apic[CCRT] == t1)
+		;
 
 	t1 = l_apic[CCRT];
Index: kernel/arch/ia32/src/smp/mps.c
===================================================================
--- kernel/arch/ia32/src/smp/mps.c	(revision fd57745cd4811832fa23ba1cef7638038244f2b5)
+++ kernel/arch/ia32/src/smp/mps.c	(revision 2f1c88e88f3d33245f94ca59d2b772d4dd5d1f56)
@@ -257,5 +257,5 @@
 	}
 
-	log_printf(", bus=%" PRIu8 " irq=%" PRIu8 " io_apic=%" PRIu8" pin=%"
+	log_printf(", bus=%" PRIu8 " irq=%" PRIu8 " io_apic=%" PRIu8 " pin=%"
 	    PRIu8, iointr->src_bus_id, iointr->src_bus_irq,
 	    iointr->dst_io_apic_id, iointr->dst_io_apic_pin);
@@ -320,5 +320,5 @@
 	}
 
-	log_printf(", bus=%" PRIu8 " irq=%" PRIu8 " l_apic=%" PRIu8" pin=%"
+	log_printf(", bus=%" PRIu8 " irq=%" PRIu8 " l_apic=%" PRIu8 " pin=%"
 	    PRIu8, lintr->src_bus_id, lintr->src_bus_irq,
 	    lintr->dst_l_apic_id, lintr->dst_l_apic_pin);