Index: boot/arch/arm32/src/mm.c
===================================================================
--- boot/arch/arm32/src/mm.c	(revision 1433ecda9b732f3f185f902feb26826ec2496e03)
+++ boot/arch/arm32/src/mm.c	(revision 2ee0e4a1310e3fe2e6e7d1f090bbe5a5e0aa5bb3)
@@ -43,5 +43,6 @@
 {
 	unsigned log = 0;
-	while (val >> log++);
+	while (val >> log++)
+		;
 	return log - 2;
 }
@@ -70,6 +71,5 @@
 	const uint32_t cinfo = CLIDR_read();
 	for (unsigned i = 0; i < 7; ++i) {
-		switch (CLIDR_CACHE(i, cinfo))
-		{
+		switch (CLIDR_CACHE(i, cinfo)) {
 		case CLIDR_DCACHE_ONLY:
 		case CLIDR_SEP_CACHE:
@@ -78,7 +78,7 @@
 		}
 	}
-	asm volatile ( "dsb\n" );
+	asm volatile ("dsb\n");
 	ICIALLU_write(0);
-	asm volatile ( "isb\n" );
+	asm volatile ("isb\n");
 }
 #endif
@@ -88,8 +88,8 @@
 {
 	asm volatile (
-		"mrc p15, 0, r0, c1, c0, 0\n"
-		"bic r0, r0, #1\n"
-		"mcr p15, 0, r0, c1, c0, 0\n"
-		::: "r0"
+	    "mrc p15, 0, r0, c1, c0, 0\n"
+	    "bic r0, r0, #1\n"
+	    "mcr p15, 0, r0, c1, c0, 0\n"
+	    ::: "r0"
 	);
 }
@@ -135,5 +135,5 @@
  *
  */
-static void init_ptl0_section(pte_level0_section_t* pte,
+static void init_ptl0_section(pte_level0_section_t *pte,
     pfn_t frame)
 {
@@ -204,9 +204,9 @@
 	asm volatile (
 		/* Behave as a client of domains */
-		"ldr r0, =0x55555555\n"
-		"mcr p15, 0, r0, c3, c0, 0\n"
+	    "ldr r0, =0x55555555\n"
+	    "mcr p15, 0, r0, c3, c0, 0\n"
 
 		/* Current settings */
-		"mrc p15, 0, r0, c1, c0, 0\n"
+	    "mrc p15, 0, r0, c1, c0, 0\n"
 
 		/* Enable ICache, DCache, BPredictors and MMU,
@@ -217,19 +217,19 @@
 		 */
 #ifdef PROCESSOR_ARCH_armv6
-		"ldr r1, =0x00801805\n"
+	    "ldr r1, =0x00801805\n"
 #else
-		"ldr r1, =0x00001805\n"
-#endif
-
-		"orr r0, r0, r1\n"
+	    "ldr r1, =0x00001805\n"
+#endif
+
+	    "orr r0, r0, r1\n"
 
 		/* Invalidate the TLB content before turning on the MMU.
 		 * ARMv7-A Reference manual, B3.10.3
 		 */
-		"mcr p15, 0, r0, c8, c7, 0\n"
+	    "mcr p15, 0, r0, c8, c7, 0\n"
 
 		/* Store settings, enable the MMU */
-		"mcr p15, 0, r0, c1, c0, 0\n"
-		::: "r0", "r1"
+	    "mcr p15, 0, r0, c1, c0, 0\n"
+	    ::: "r0", "r1"
 	);
 }
Index: boot/arch/ppc32/src/main.c
===================================================================
--- boot/arch/ppc32/src/main.c	(revision 1433ecda9b732f3f185f902feb26826ec2496e03)
+++ boot/arch/ppc32/src/main.c	(revision 2ee0e4a1310e3fe2e6e7d1f090bbe5a5e0aa5bb3)
@@ -122,6 +122,6 @@
 
 	uintptr_t balloc_start = ALIGN_UP(top, PAGE_SIZE);
-	size_t pages = (balloc_start + ALIGN_UP(BALLOC_MAX_SIZE, PAGE_SIZE))
-	    >> PAGE_WIDTH;
+	size_t pages = (balloc_start + ALIGN_UP(BALLOC_MAX_SIZE, PAGE_SIZE)) >>
+	    PAGE_WIDTH;
 	void *transtable;
 	void *transtable_pa;
Index: boot/arch/sparc64/src/ofw.c
===================================================================
--- boot/arch/sparc64/src/ofw.c	(revision 1433ecda9b732f3f185f902feb26826ec2496e03)
+++ boot/arch/sparc64/src/ofw.c	(revision 2ee0e4a1310e3fe2e6e7d1f090bbe5a5e0aa5bb3)
@@ -88,7 +88,7 @@
 				 * "cpuid" for US-IV
 				 */
-				if ((ofw_get_property(child, "upa-portid", &mid, sizeof(mid)) <= 0)
-				    && (ofw_get_property(child, "portid", &mid, sizeof(mid)) <= 0)
-				    && (ofw_get_property(child, "cpuid", &mid, sizeof(mid)) <= 0))
+				if ((ofw_get_property(child, "upa-portid", &mid, sizeof(mid)) <= 0) &&
+				    (ofw_get_property(child, "portid", &mid, sizeof(mid)) <= 0) &&
+				    (ofw_get_property(child, "cpuid", &mid, sizeof(mid)) <= 0))
 					continue;
 
@@ -117,8 +117,8 @@
 
 	asm volatile (
-		"ldxa [%[zero]] %[asi], %[current_mid]\n"
-		: [current_mid] "=r" (current_mid)
-		: [zero] "r" (0),
-		  [asi] "i" (ASI_ICBUS_CONFIG)
+	    "ldxa [%[zero]] %[asi], %[current_mid]\n"
+	    : [current_mid] "=r" (current_mid)
+	    : [zero] "r" (0),
+	      [asi] "i" (ASI_ICBUS_CONFIG)
 	);