Index: uspace/lib/libc/arch/arm32/src/syscall.c
===================================================================
--- uspace/lib/libc/arch/arm32/src/syscall.c	(revision fa23560fdd0e695738620af86112b84932e3b3e3)
+++ uspace/lib/libc/arch/arm32/src/syscall.c	(revision 2e51969e2c8c3905ceef1d73437f34d14c927dff)
@@ -51,5 +51,5 @@
  */
 sysarg_t __syscall(const sysarg_t p1, const sysarg_t p2, const sysarg_t p3,
-    const sysarg_t p4, const syscall_t id)
+    const sysarg_t p4, const sysarg_t p5, const sysarg_t p6, const syscall_t id)
 {
 	register sysarg_t __arm_reg_r0 asm("r0") = p1;
@@ -57,13 +57,17 @@
 	register sysarg_t __arm_reg_r2 asm("r2") = p3;
 	register sysarg_t __arm_reg_r3 asm("r3") = p4;
-	register sysarg_t __arm_reg_r4 asm("r4") = id;
+	register sysarg_t __arm_reg_r4 asm("r4") = p5;
+	register sysarg_t __arm_reg_r5 asm("r5") = p6;
+	register sysarg_t __arm_reg_r6 asm("r6") = id;
 
 	asm volatile ( "swi"
 		: "=r" (__arm_reg_r0)
-		: "r"  (__arm_reg_r0),
-		  "r"  (__arm_reg_r1),
-		  "r"  (__arm_reg_r2),
-		  "r"  (__arm_reg_r3),
-		  "r"  (__arm_reg_r4)
+		: "r" (__arm_reg_r0),
+		  "r" (__arm_reg_r1),
+		  "r" (__arm_reg_r2),
+		  "r" (__arm_reg_r3),
+		  "r" (__arm_reg_r4),
+		  "r" (__arm_reg_r5),
+		  "r" (__arm_reg_r6)
 	);