Changeset 2cf28b9 in mainline
- Timestamp:
- 2017-10-25T15:22:45Z (7 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- 62558202
- Parents:
- f668d60
- Location:
- uspace
- Files:
-
- 12 edited
Legend:
- Unmodified
- Added
- Removed
-
uspace/drv/bus/usb/xhci/bus.c
rf668d60 r2cf28b9 45 45 #include <stdbool.h> 46 46 47 #include "hc.h" 47 48 #include "bus.h" 48 49 #include "endpoint.h" … … 136 137 } 137 138 139 /* Calculate route string */ 140 xhci_device_t *xhci_hub = xhci_device_get(dev->hub); 141 xhci_dev->tier = xhci_hub->tier + 1; 142 xhci_dev->route_str = xhci_hub->route_str; 143 144 /* Roothub port is not part of the route string */ 145 if (xhci_dev->tier >= 2) { 146 const unsigned offset = 4 * (xhci_dev->tier - 2); 147 xhci_dev->route_str |= (dev->port & 0xf) << offset; 148 } 149 150 fibril_mutex_lock(&bus->base.guard); 138 151 /* Assign an address to the device */ 139 152 if ((err = address_device(hc, xhci_dev))) { … … 147 160 assert(bus->devices_by_slot[xhci_dev->slot_id] == NULL); 148 161 bus->devices_by_slot[xhci_dev->slot_id] = xhci_dev; 162 fibril_mutex_unlock(&bus->base.guard); 149 163 150 164 /* Read the device descriptor, derive the match ids */ … … 305 319 } 306 320 321 static int request_address(bus_t *bus_base, usb_address_t *addr, bool strict, usb_speed_t speed) 322 { 323 assert(addr); 324 325 if (*addr != USB_ADDRESS_DEFAULT) 326 /* xHCI does not allow software to assign addresses. */ 327 return ENOTSUP; 328 329 assert(strict); 330 331 xhci_bus_t *xhci_bus = bus_to_xhci_bus(bus_base); 332 333 if (xhci_bus->default_address_speed != USB_SPEED_MAX) 334 /* Already allocated */ 335 return ENOENT; 336 337 xhci_bus->default_address_speed = speed; 338 return EOK; 339 } 340 341 static int release_address(bus_t *bus_base, usb_address_t addr) 342 { 343 if (addr != USB_ADDRESS_DEFAULT) 344 return ENOTSUP; 345 346 xhci_bus_t *xhci_bus = bus_to_xhci_bus(bus_base); 347 348 xhci_bus->default_address_speed = USB_SPEED_MAX; 349 return EOK; 350 } 351 307 352 static usb_transfer_batch_t *create_batch(bus_t *bus, endpoint_t *ep) 308 353 { … … 327 372 .find_endpoint = find_endpoint, 328 373 329 .request_address = NULL,330 .release_address = NULL,374 .request_address = request_address, 375 .release_address = release_address, 331 376 .reset_toggle = reset_toggle, 332 377 … … 351 396 352 397 bus->base.ops = xhci_bus_ops; 398 bus->default_address_speed = USB_SPEED_MAX; 353 399 return EOK; 354 400 } -
uspace/drv/bus/usb/xhci/bus.h
rf668d60 r2cf28b9 49 49 50 50 xhci_device_t **devices_by_slot; /**< Devices by Slot ID */ 51 52 usb_speed_t default_address_speed; /**< Used to get speed from usb hubs */ 51 53 } xhci_bus_t; 52 54 -
uspace/drv/bus/usb/xhci/endpoint.c
rf668d60 r2cf28b9 39 39 40 40 #include <errno.h> 41 41 #include <macros.h> 42 43 #include "hc.h" 42 44 #include "bus.h" 43 45 #include "commands.h" -
uspace/drv/bus/usb/xhci/endpoint.h
rf668d60 r2cf28b9 43 43 #include <usb/host/hcd.h> 44 44 45 #include "hc.h" 45 #include "trb_ring.h" 46 46 47 #include "transfers.h" 47 48 … … 97 98 /** Slot ID assigned to the device by xHC. */ 98 99 uint32_t slot_id; 100 101 /** Corresponding port on RH */ 102 uint8_t rh_port; 103 104 /** USB Tier of the device */ 105 uint8_t tier; 106 107 /** Route string */ 108 uint32_t route_str; 99 109 100 110 /** Place to store virtual address for allocated context */ -
uspace/drv/bus/usb/xhci/hc.c
rf668d60 r2cf28b9 657 657 int err = ENOMEM; 658 658 659 /* Although we have the precise PSIV value on devices of tier 1, 660 * we have to rely on reverse mapping on others. */ 661 if (!hc->speed_to_psiv[dev->base.speed]) { 662 usb_log_error("Device reported an usb speed that cannot be mapped to HC port speed."); 663 return EINVAL; 664 } 665 659 666 /* Setup and register device context */ 660 667 dev->dev_ctx = malloc32(sizeof(xhci_device_ctx_t)); … … 672 679 673 680 /* Initialize slot_ctx according to section 4.3.3 point 3. */ 674 XHCI_SLOT_ROOT_HUB_PORT_SET(ictx->slot_ctx, dev-> base.port); // FIXME: This should be port at RH681 XHCI_SLOT_ROOT_HUB_PORT_SET(ictx->slot_ctx, dev->rh_port); 675 682 XHCI_SLOT_CTX_ENTRIES_SET(ictx->slot_ctx, 1); 676 677 /* Attaching to root hub port, root string equals to 0. */ 678 XHCI_SLOT_ROUTE_STRING_SET(ictx->slot_ctx, 0); // FIXME: This is apparently valid in limited cases 683 XHCI_SLOT_ROUTE_STRING_SET(ictx->slot_ctx, dev->route_str); 684 XHCI_SLOT_SPEED_SET(ictx->slot_ctx, hc->speed_to_psiv[dev->base.speed]); 685 686 /* In a very specific case, we have to set also these. But before that, 687 * we need to refactor how TT is handled in libusbhost. */ 688 XHCI_SLOT_TT_HUB_SLOT_ID_SET(ictx->slot_ctx, 0); 689 XHCI_SLOT_TT_HUB_PORT_SET(ictx->slot_ctx, 0); 690 XHCI_SLOT_MTT_SET(ictx->slot_ctx, 0); 679 691 680 692 /* Copy endpoint 0 context and set A1 flag. */ -
uspace/drv/bus/usb/xhci/hc.h
rf668d60 r2cf28b9 43 43 #include "scratchpad.h" 44 44 #include "trb_ring.h" 45 45 46 #include "rh.h" 46 47 #include "bus.h" -
uspace/drv/bus/usb/xhci/hw_struct/context.h
rf668d60 r2cf28b9 111 111 xhci_dword_t reserved [4]; 112 112 113 #define XHCI_SLOT_ROUTE_STRING_SET(ctx, val) \ 114 xhci_dword_set_bits(&(ctx).data[0], (val & 0xFFFFF), 19, 0) 115 #define XHCI_SLOT_SPEED_SET(ctx, val) \ 116 xhci_dword_set_bits(&(ctx).data[0], (val & 0xF), 23, 20) 117 #define XHCI_SLOT_MTT_SET(ctx, val) \ 118 xhci_dword_set_bits(&(ctx).data[0], !!val, 25, 25) 119 #define XHCI_SLOT_CTX_ENTRIES_SET(ctx, val) \ 120 xhci_dword_set_bits(&(ctx).data[0], val, 31, 27) 121 113 122 #define XHCI_SLOT_ROOT_HUB_PORT_SET(ctx, val) \ 114 123 xhci_dword_set_bits(&(ctx).data[1], val, 23, 16) 115 #define XHCI_SLOT_CTX_ENTRIES_SET(ctx, val) \ 116 xhci_dword_set_bits(&(ctx).data[0], val, 31, 27) 117 #define XHCI_SLOT_ROUTE_STRING_SET(ctx, val) \ 118 xhci_dword_set_bits(&(ctx).data[0], (val & 0xFFFFF), 19, 0) 124 125 #define XHCI_SLOT_TT_HUB_SLOT_ID_SET(ctx, val) \ 126 xhci_dword_set_bits(&(ctx).data[2], (val & 0xFF), 7, 0) 127 #define XHCI_SLOT_TT_HUB_PORT_SET(ctx, val) \ 128 xhci_dword_set_bits(&(ctx).data[2], (val & 0xFF), 15, 8) 119 129 120 130 #define XHCI_SLOT_ROUTE_STRING(ctx) XHCI_DWORD_EXTRACT((ctx).data[0], 19, 0) -
uspace/drv/bus/usb/xhci/rh.c
rf668d60 r2cf28b9 69 69 rh->max_ports = XHCI_REG_RD(hc->cap_regs, XHCI_CAP_MAX_PORTS); 70 70 rh->devices = (xhci_device_t **) calloc(rh->max_ports, sizeof(xhci_device_t *)); 71 hc->rh.hc_device = device; 72 73 return device_init(&hc->rh.device); 71 rh->hc_device = device; 72 73 const int err = device_init(&rh->device.base); 74 if (err) 75 return err; 76 77 /* Initialize route string */ 78 rh->device.route_str = 0; 79 rh->device.tier = 0; 80 81 return EOK; 74 82 } 75 83 … … 81 89 assert(rh); 82 90 assert(rh->hc_device); 91 92 assert(rh->devices[port_id - 1] == NULL); 83 93 84 94 xhci_bus_t *bus = &rh->hc->bus; … … 94 104 xhci_dev->hc = rh->hc; 95 105 xhci_dev->usb3 = port_speed->major == 3; 96 97 dev->hub = &rh->device; 106 xhci_dev->rh_port = port_id; 107 108 dev->hub = &rh->device.base; 98 109 dev->port = port_id; 99 110 dev->speed = port_speed->usb_speed; … … 113 124 } 114 125 115 fibril_mutex_lock(&rh->device.guard); 116 list_append(&dev->link, &rh->device.devices); 117 if (!rh->devices[port_id - 1]) { 118 /* Only save the device if it's the first one connected to this port. */ 119 rh->devices[port_id - 1] = xhci_dev; 120 } 121 fibril_mutex_unlock(&rh->device.guard); 126 fibril_mutex_lock(&rh->device.base.guard); 127 list_append(&dev->link, &rh->device.base.devices); 128 rh->devices[port_id - 1] = xhci_dev; 129 fibril_mutex_unlock(&rh->device.base.guard); 122 130 123 131 return EOK; … … 185 193 fibril_mutex_unlock(&dev->base.guard); 186 194 187 fibril_mutex_lock(&rh->device. guard);195 fibril_mutex_lock(&rh->device.base.guard); 188 196 list_remove(&dev->base.link); 189 fibril_mutex_unlock(&rh->device.guard);190 191 197 rh->devices[port_id - 1] = NULL; 198 fibril_mutex_unlock(&rh->device.base.guard); 199 192 200 usb_log_debug2("Aborting all active transfers to '%s'.", ddf_fun_get_name(dev->base.fun)); 193 201 -
uspace/drv/bus/usb/xhci/rh.h
rf668d60 r2cf28b9 39 39 #include <usb/host/usb_transfer_batch.h> 40 40 #include <usb/host/bus.h> 41 41 42 #include "hw_struct/regs.h" 43 #include "endpoint.h" 42 44 43 45 typedef struct xhci_hc xhci_hc_t; … … 56 58 typedef struct hcd_roothub hcd_roothub_t; 57 59 typedef struct xhci_bus xhci_bus_t; 58 typedef struct xhci_device xhci_device_t;59 60 60 61 /* XHCI root hub instance */ … … 64 65 65 66 /* Root for the device tree */ 66 device_t device;67 xhci_device_t device; 67 68 68 69 /* We need this to attach children to */ -
uspace/drv/bus/usb/xhci/transfers.h
rf668d60 r2cf28b9 39 39 #include <usb/host/usb_transfer_batch.h> 40 40 41 #include "h c.h"41 #include "hw_struct/context.h" 42 42 #include "trb_ring.h" 43 44 typedef struct xhci_hc xhci_hc_t; 43 45 44 46 typedef struct { -
uspace/lib/usbhost/include/usb/host/bus.h
rf668d60 r2cf28b9 82 82 int (*remove_device)(bus_t *, hcd_t *, device_t *); 83 83 84 /* The following operations are protected by a bus guard. */ 84 85 endpoint_t *(*create_endpoint)(bus_t *); 85 86 int (*register_endpoint)(bus_t *, endpoint_t *, const usb_endpoint_desc_t *); -
uspace/lib/usbhost/src/bus.c
rf668d60 r2cf28b9 87 87 return ENOTSUP; 88 88 89 fibril_mutex_lock(&bus->guard); 90 const int r = bus->ops.enumerate_device(bus, hcd, dev); 91 fibril_mutex_unlock(&bus->guard); 92 return r; 89 return bus->ops.enumerate_device(bus, hcd, dev); 93 90 } 94 91 … … 101 98 return ENOTSUP; 102 99 103 fibril_mutex_lock(&bus->guard); 104 const int r = bus->ops.remove_device(bus, hcd, dev); 105 fibril_mutex_unlock(&bus->guard); 106 return r; 100 return bus->ops.remove_device(bus, hcd, dev); 107 101 } 108 102
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