Changeset 2a77eaa2 in mainline

Timestamp:

2013-01-01T18:17:05Z (12 years ago)

Author:

Jan Vesely <jano.vesely@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

f65b8e0c

Parents:

e55fcd2

Message:

arm32, boot: Drop l2 cache enabling. Add armv7 cache invalidate.

L2 Cache on CortexA8 is enabled by default, we can control it together with L1 data cache using C bit in sctlr.

File:

• boot/arch/arm32/src/mm.c (modified) (1 diff)

boot/arch/arm32/src/mm.c

@@ -134 +134 @@
                 
 #ifdef PROCESSOR_ARCH_armv7_a
-                /* Read Auxiliary control register */
-                "mrc p15, 0, r0, c1, c0, 1\n"
-                /* Mask to enable L2 cache */
-                "ldr r1, =0x00000002\n"
-                "orr r0, r0, r1\n"
-                /* Store Auxiliary control register */
-                "mrc p15, 0, r0, c1, c0, 1\n"
+                /* armv7 no longer requires cache entries to be invalid
+                 * upon reset, do this manually */
+                /* Invalidate ICache */
+                "mcr p15, 0, r0, c7, c5, 6\n"
+                //TODO: Invalidate data cache
 #endif
+
                 /* Current settings */
                 "mrc p15, 0, r0, c1, c0, 0\n"