Index: uspace/drv/platform/amdm37x/Makefile =================================================================== --- uspace/drv/platform/amdm37x/Makefile (revision 2a37b9f1eb93bba78ec231d42ef29f30dff550a0) +++ uspace/drv/platform/amdm37x/Makefile (revision 2a37b9f1eb93bba78ec231d42ef29f30dff550a0) @@ -0,0 +1,38 @@ +# +# Copyright (c) 2012 Jan Vesely +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# - Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# - Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# - The name of the author may not be used to endorse or promote products +# derived from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR +# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# + +USPACE_PREFIX = ../../.. +LIBS = $(LIBDRV_PREFIX)/libdrv.a +EXTRA_CFLAGS += -I$(LIBDRV_PREFIX)/include +BINARY = amdm37x + +SOURCES = \ + amdm37x.c \ + main.c + +include $(USPACE_PREFIX)/Makefile.common Index: uspace/drv/platform/amdm37x/amdm37x.c =================================================================== --- uspace/drv/platform/amdm37x/amdm37x.c (revision 2a37b9f1eb93bba78ec231d42ef29f30dff550a0) +++ uspace/drv/platform/amdm37x/amdm37x.c (revision 2a37b9f1eb93bba78ec231d42ef29f30dff550a0) @@ -0,0 +1,404 @@ +/* + * Copyright (c) 2012 Jan Vesely + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** + * @defgroup root_amdm37x TI AM/DM37x platform driver. + * @brief HelenOS TI AM/DM37x platform driver. + * @{ + */ + +/** @file + */ + +#include "amdm37x.h" + +#include +#include +#include +#include +#include + +static void log(const volatile void *place, uint32_t val, volatile void* base, size_t size, void *data, bool write) +{ + printf("PIO %s: %p(%p) %#"PRIx32"\n", write ? "WRITE" : "READ", + (place - base) + data, place, val); +} + + +int amdm37x_init(amdm37x_t *device, bool trace) +{ + assert(device); + int ret = EOK; + + ret = pio_enable((void*)USBHOST_CM_BASE_ADDRESS, USBHOST_CM_SIZE, + (void**)&device->cm.usbhost); + if (ret != EOK) + return ret; + + ret = pio_enable((void*)CORE_CM_BASE_ADDRESS, CORE_CM_SIZE, + (void**)&device->cm.core); + if (ret != EOK) + return ret; + + ret = pio_enable((void*)CLOCK_CONTROL_CM_BASE_ADDRESS, + CLOCK_CONTROL_CM_SIZE, (void**)&device->cm.clocks); + if (ret != EOK) + return ret; + + ret = pio_enable((void*)MPU_CM_BASE_ADDRESS, + MPU_CM_SIZE, (void**)&device->cm.mpu); + if (ret != EOK) + return ret; + + ret = pio_enable((void*)IVA2_CM_BASE_ADDRESS, + IVA2_CM_SIZE, (void**)&device->cm.iva2); + if (ret != EOK) + return ret; + + ret = pio_enable((void*)CLOCK_CONTROL_PRM_BASE_ADDRESS, + CLOCK_CONTROL_PRM_SIZE, (void**)&device->prm.clocks); + if (ret != EOK) + return ret; + + ret = pio_enable((void*)GLOBAL_REG_PRM_BASE_ADDRESS, + GLOBAL_REG_PRM_SIZE, (void**)&device->prm.global); + if (ret != EOK) + return ret; + + ret = pio_enable((void*)AMDM37x_USBTLL_BASE_ADDRESS, + AMDM37x_USBTLL_SIZE, (void**)&device->tll); + if (ret != EOK) + return ret; + + ret = pio_enable((void*)AMDM37x_UHH_BASE_ADDRESS, + AMDM37x_UHH_SIZE, (void**)&device->uhh); + if (ret != EOK) + return ret; + + if (trace) { + pio_trace_enable(device->tll, AMDM37x_USBTLL_SIZE, log, (void*)AMDM37x_USBTLL_BASE_ADDRESS); + pio_trace_enable(device->cm.clocks, CLOCK_CONTROL_CM_SIZE, log, (void*)CLOCK_CONTROL_CM_BASE_ADDRESS); + pio_trace_enable(device->cm.core, CORE_CM_SIZE, log, (void*)CORE_CM_BASE_ADDRESS); + pio_trace_enable(device->cm.mpu, MPU_CM_SIZE, log, (void*)MPU_CM_BASE_ADDRESS); + pio_trace_enable(device->cm.iva2, IVA2_CM_SIZE, log, (void*)IVA2_CM_BASE_ADDRESS); + pio_trace_enable(device->cm.usbhost, USBHOST_CM_SIZE, log, (void*)USBHOST_CM_BASE_ADDRESS); + pio_trace_enable(device->uhh, AMDM37x_UHH_SIZE, log, (void*)AMDM37x_UHH_BASE_ADDRESS); + pio_trace_enable(device->prm.clocks, CLOCK_CONTROL_PRM_SIZE, log, (void*)CLOCK_CONTROL_PRM_BASE_ADDRESS); + pio_trace_enable(device->prm.global, GLOBAL_REG_PRM_SIZE, log, (void*)GLOBAL_REG_PRM_BASE_ADDRESS); + } + return EOK; +} + + +/** Set DPLLs 1,2,3,4,5 to ON (locked) and autoidle. + * @param device Register map. + * + * The idea is to get all DPLLs running and make hw control their power mode, + * based on the module requirements (module ICLKs and FCLKs). + */ +void amdm37x_setup_dpll_on_autoidle(amdm37x_t *device) +{ + assert(device); + /* Get SYS_CLK value, it is used as reference clock by all DPLLs, + * NFI who sets this or why it is set to specific value. */ + const unsigned osc_clk = pio_read_32(&device->prm.clocks->clksel) + & CLOCK_CONTROL_PRM_CLKSEL_SYS_CLKIN_MASK; + const unsigned clk_reg = pio_read_32(&device->prm.global->clksrc_ctrl); + const unsigned base_freq = sys_clk_freq_kHz(osc_clk) + / GLOBAL_REG_PRM_CLKSRC_CTRL_SYSCLKDIV_GET(clk_reg); + ddf_msg(LVL_NOTE, "Base frequency: %d.%dMhz", + base_freq / 1000, base_freq % 1000); + + + /* DPLL1 provides MPU(CPU) clock. + * It uses SYS_CLK as reference clock and core clock (DPLL3) as + * high frequency bypass (MPU then runs on L3 interconnect freq). + * It should be setup by fw or u-boot.*/ + mpu_cm_regs_t *mpu = device->cm.mpu; + + /* Current MPU frequency. */ + if (pio_read_32(&mpu->clkstst) & MPU_CM_CLKSTST_CLKACTIVITY_MPU_ACTIVE_FLAG) { + if (pio_read_32(&mpu->idlest_pll) & MPU_CM_IDLEST_PLL_ST_MPU_CLK_LOCKED_FLAG) { + /* DPLL active and locked */ + const uint32_t reg = pio_read_32(&mpu->clksel1_pll); + const unsigned multiplier = + (reg & MPU_CM_CLKSEL1_PLL_MPU_DPLL_MULT_MASK) + >> MPU_CM_CLKSEL1_PLL_MPU_DPLL_MULT_SHIFT; + const unsigned divisor = + (reg & MPU_CM_CLKSEL1_PLL_MPU_DPLL_DIV_MASK) + >> MPU_CM_CLKSEL1_PLL_MPU_DPLL_DIV_SHIFT; + const unsigned divisor2 = + (pio_read_32(&mpu->clksel2_pll) + & MPU_CM_CLKSEL2_PLL_MPU_DPLL_CLKOUT_DIV_MASK); + if (multiplier && divisor && divisor2) { + /** See AMDM37x TRM p. 300 for the formula */ + const unsigned freq = + ((base_freq * multiplier) / (divisor + 1)) + / divisor2; + ddf_msg(LVL_NOTE, "MPU running at %d.%d MHz", + freq / 1000, freq % 1000); + } else { + ddf_msg(LVL_WARN, "Frequency divisor and/or " + "multiplier value invalid: %d %d %d", + multiplier, divisor, divisor2); + } + } else { + /* DPLL in LP bypass mode */ + const unsigned divisor = + MPU_CM_CLKSEL1_PLL_MPU_CLK_SRC_VAL( + pio_read_32(&mpu->clksel1_pll)); + ddf_msg(LVL_NOTE, "MPU DPLL in bypass mode, running at" + " CORE CLK / %d MHz", divisor); + } + } else { + ddf_msg(LVL_WARN, "MPU clock domain is not active, we should not be running..."); + } + // TODO: Enable this (automatic MPU downclocking): +#if 0 + /* Enable low power bypass mode, this will take effect the next lock or + * relock sequence. */ + //TODO: We might need to force re-lock after enabling this + pio_set_32(&mpu->clken_pll, MPU_CM_CLKEN_PLL_EN_MPU_DPLL_LP_MODE_FLAG, 5); + /* Enable automatic relocking */ + pio_change_32(&mpu->autoidle_pll, MPU_CM_AUTOIDLE_PLL_AUTO_MPU_DPLL_ENABLED, MPU_CM_AUTOIDLE_PLL_AUTO_MPU_DPLL_MASK, 5); +#endif + + /* DPLL2 provides IVA(video acceleration) clock. + * It uses SYS_CLK as reference clokc and core clock (DPLL3) as + * high frequency bypass (IVA runs on L3 freq). + */ + // TODO: We can probably turn this off entirely. IVA is left unused. + /* Enable low power bypass mode, this will take effect the next lock or + * relock sequence. */ + //TODO: We might need to force re-lock after enabling this + pio_set_32(&device->cm.iva2->clken_pll, MPU_CM_CLKEN_PLL_EN_MPU_DPLL_LP_MODE_FLAG, 5); + /* Enable automatic relocking */ + pio_change_32(&device->cm.iva2->autoidle_pll, MPU_CM_AUTOIDLE_PLL_AUTO_MPU_DPLL_ENABLED, MPU_CM_AUTOIDLE_PLL_AUTO_MPU_DPLL_MASK, 5); + + /* DPLL3 provides tons of clocks: + * CORE_CLK, COREX2_CLK, DSS_TV_CLK, 12M_CLK, 48M_CLK, 96M_CLK, L3_ICLK, + * and L4_ICLK. It uses SYS_CLK as reference clock and low frequency + * bypass. It should be setup by fw or u-boot as it controls critical + * interconnects. + */ + if (pio_read_32(&device->cm.clocks->idlest_ckgen) & CLOCK_CONTROL_CM_IDLEST_CKGEN_ST_CORE_CLK_FLAG) { + /* DPLL active and locked */ + const uint32_t reg = + pio_read_32(&device->cm.clocks->clksel1_pll); + const unsigned multiplier = + CLOCK_CONTROL_CM_CLKSEL1_PLL_CORE_DPLL_MULT_GET(reg); + const unsigned divisor = + CLOCK_CONTROL_CM_CLKSEL1_PLL_CORE_DPLL_DIV_GET(reg); + const unsigned divisor2 = + CLOCK_CONTROL_CM_CLKSEL1_PLL_CORE_DPLL_CLKOUT_DIV_GET(reg); + if (multiplier && divisor && divisor2) { + /** See AMDM37x TRM p. 300 for the formula */ + const unsigned freq = + ((base_freq * multiplier) / (divisor + 1)) / divisor2; + ddf_msg(LVL_NOTE, "CORE CLK running at %d.%d MHz", + freq / 1000, freq % 1000); + const unsigned l3_div = + pio_read_32(&device->cm.core->clksel) + & CORE_CM_CLKSEL_CLKSEL_L3_MASK; + if (l3_div == CORE_CM_CLKSEL_CLKSEL_L3_DIVIDED1 || + l3_div == CORE_CM_CLKSEL_CLKSEL_L3_DIVIDED2) { + ddf_msg(LVL_NOTE, "L3 interface at %d.%d MHz", + (freq / l3_div) / 1000, + (freq / l3_div) % 1000); + } else { + ddf_msg(LVL_WARN,"L3 interface clock divisor is" + " invalid: %d", l3_div); + } + } else { + ddf_msg(LVL_WARN, "DPLL3 frequency divisor and/or " + "multiplier value invalid: %d %d %d", + multiplier, divisor, divisor2); + } + } else { + ddf_msg(LVL_WARN, "CORE CLK in bypass mode, fruunig at SYS_CLK" + " frreq of %d.%d MHz", base_freq / 1000, base_freq % 1000); + } + + /* Set DPLL3 to automatic to save power */ + pio_change_32(&device->cm.clocks->autoidle_pll, + CLOCK_CONTROL_CM_AUTOIDLE_PLL_AUTO_CORE_DPLL_AUTOMATIC, + CLOCK_CONTROL_CM_AUTOIDLE_PLL_AUTO_CORE_DPLL_MASK, 5); + + /* DPLL4 provides peripheral domain clocks: + * CAM_MCLK, EMU_PER_ALWON_CLK, DSS1_ALWON_FCLK, and 96M_ALWON_FCLK. + * It uses SYS_CLK as reference clock and low frequency bypass. + * 96M clock is used by McBSP[1,5], MMC[1,2,3], I2C[1,2,3], so + * we can probably turn this off entirely (DSS is still non-functional). + */ + /* Set DPLL4 to automatic to save power */ + pio_change_32(&device->cm.clocks->autoidle_pll, + CLOCK_CONTROL_CM_AUTOIDLE_PLL_AUTO_PERIPH_DPLL_AUTOMATIC, + CLOCK_CONTROL_CM_AUTOIDLE_PLL_AUTO_PERIPH_DPLL_MASK, 5); + + /* DPLL5 provide peripheral domain clocks: 120M_FCLK. + * It uses SYS_CLK as reference clock and low frequency bypass. + * 120M clock is used by HS USB and USB TLL. + */ + // TODO setup DPLL5 + if ((pio_read_32(&device->cm.clocks->clken2_pll) + & CLOCK_CONTROL_CM_CLKEN2_PLL_EN_PERIPH2_DPLL_MASK) + != CLOCK_CONTROL_CM_CLKEN2_PLL_EN_PERIPH2_DPLL_LOCK) { + /* Compute divisors and multiplier + * See AMDM37x TRM p. 300 for the formula */ + // TODO: base_freq does not have to be rounded to Mhz + // (that's why I used KHz as unit). + const unsigned mult = 120; + const unsigned div = (base_freq / 1000) - 1; + const unsigned div2 = 1; + if ( ((base_freq % 1000) != 0) || (div > 127)) { + ddf_msg(LVL_ERROR, "Rounding error, or divisor to big " + "freq: %d, div: %d", base_freq, div); + return; + }; + assert(div <= 127); + + /* Set multiplier */ + pio_change_32(&device->cm.clocks->clksel4_pll, + CLOCK_CONTROL_CM_CLKSEL4_PLL_PERIPH2_DPLL_MULT_CREATE(mult), + CLOCK_CONTROL_CM_CLKSEL4_PLL_PERIPH2_DPLL_MULT_MASK, 10); + + /* Set DPLL divisor */ + pio_change_32(&device->cm.clocks->clksel4_pll, + CLOCK_CONTROL_CM_CLKSEL4_PLL_PERIPH2_DPLL_DIV_CREATE(div), + CLOCK_CONTROL_CM_CLKSEL4_PLL_PERIPH2_DPLL_DIV_MASK, 10); + + /* Set output clock divisor */ + pio_change_32(&device->cm.clocks->clksel5_pll, + CLOCK_CONTROL_CM_CLKSEL5_PLL_DIV120M_CREATE(div2), + CLOCK_CONTROL_CM_CLKSEL5_PLL_DIV120M_MASK, 10); + + /* Start DPLL5 */ + pio_change_32(&device->cm.clocks->clken2_pll, + CLOCK_CONTROL_CM_CLKEN2_PLL_EN_PERIPH2_DPLL_LOCK, + CLOCK_CONTROL_CM_CLKEN2_PLL_EN_PERIPH2_DPLL_MASK, 10); + + } + /* Set DPLL5 to automatic to save power */ + pio_change_32(&device->cm.clocks->autoidle2_pll, + CLOCK_CONTROL_CM_AUTOIDLE2_PLL_AUTO_PERIPH2_DPLL_AUTOMATIC, + CLOCK_CONTROL_CM_AUTOIDLE2_PLL_AUTO_PERIPH2_DPLL_MASK, 5); +} + +/** Enable/disable function and interface clocks for USBTLL and USBHOST. + * @param device Register map. + * @param on True to switch clocks on. + */ +void amdm37x_usb_clocks_set(amdm37x_t *device, bool enabled) +{ + if (enabled) { + /* Enable interface and function clock for USB TLL */ + pio_set_32(&device->cm.core->fclken3, + CORE_CM_FCLKEN3_EN_USBTLL_FLAG, 5); + pio_set_32(&device->cm.core->iclken3, + CORE_CM_ICLKEN3_EN_USBTLL_FLAG, 5); + + /* Enable interface and function clock for USB hosts */ + pio_set_32(&device->cm.usbhost->fclken, + USBHOST_CM_FCLKEN_EN_USBHOST1_FLAG | + USBHOST_CM_FCLKEN_EN_USBHOST2_FLAG, 5); + pio_set_32(&device->cm.usbhost->iclken, + USBHOST_CM_ICLKEN_EN_USBHOST, 5); +#if 0 + printf("DPLL5 (and everything else) should be on: %" + PRIx32" %"PRIx32".\n", + pio_read_32(&device->cm.clocks->idlest_ckgen), + pio_read_32(&device->cm.clocks->idlest2_ckgen)); +#endif + } else { + /* Disable interface and function clock for USB hosts */ + pio_clear_32(&device->cm.usbhost->iclken, + USBHOST_CM_ICLKEN_EN_USBHOST, 5); + pio_clear_32(&device->cm.usbhost->fclken, + USBHOST_CM_FCLKEN_EN_USBHOST1_FLAG | + USBHOST_CM_FCLKEN_EN_USBHOST2_FLAG, 5); + + /* Disable interface and function clock for USB TLL */ + pio_clear_32(&device->cm.core->iclken3, + CORE_CM_ICLKEN3_EN_USBTLL_FLAG, 5); + pio_clear_32(&device->cm.core->fclken3, + CORE_CM_FCLKEN3_EN_USBTLL_FLAG, 5); + } +} + +/** Initialize USB TLL port connections. + * + * Different modes are on page 3312 of the Manual Figure 22-34. + * Select mode than can operate in FS/LS. + */ +int amdm37x_usb_tll_init(amdm37x_t *device) +{ + /* Check access */ + if (pio_read_32(&device->cm.core->idlest3) & CORE_CM_IDLEST3_ST_USBTLL_FLAG) { + ddf_msg(LVL_ERROR, "USB TLL is not accessible"); + return EIO; + } + + /* Reset USB TLL */ + pio_set_32(&device->tll->sysconfig, TLL_SYSCONFIG_SOFTRESET_FLAG, 5); + ddf_msg(LVL_DEBUG2, "Waiting for USB TLL reset"); + while (!(pio_read_32(&device->tll->sysstatus) & TLL_SYSSTATUS_RESET_DONE_FLAG)); + ddf_msg(LVL_DEBUG, "USB TLL Reset done."); + + /* Setup idle mode (smart idle) */ + pio_change_32(&device->tll->sysconfig, + TLL_SYSCONFIG_CLOCKACTIVITY_FLAG | TLL_SYSCONFIG_AUTOIDLE_FLAG | + TLL_SYSCONFIG_SIDLE_MODE_SMART, TLL_SYSCONFIG_SIDLE_MODE_MASK, 5); + + /* Smart idle for UHH */ + pio_change_32(&device->uhh->sysconfig, + UHH_SYSCONFIG_CLOCKACTIVITY_FLAG | UHH_SYSCONFIG_AUTOIDLE_FLAG | + UHH_SYSCONFIG_SIDLE_MODE_SMART, UHH_SYSCONFIG_SIDLE_MODE_MASK, 5); + + /* Set all ports to go through TLL(UTMI) + * Direct connection can only work in HS mode */ + pio_set_32(&device->uhh->hostconfig, + UHH_HOSTCONFIG_P1_ULPI_BYPASS_FLAG | + UHH_HOSTCONFIG_P2_ULPI_BYPASS_FLAG | + UHH_HOSTCONFIG_P3_ULPI_BYPASS_FLAG, 5); + + /* What is this? */ + pio_set_32(&device->tll->shared_conf, TLL_SHARED_CONF_FCLK_IS_ON_FLAG, 5); + + for (unsigned i = 0; i < 3; ++i) { + /* Serial mode is the only one capable of FS/LS operation. + * Select FS/LS mode, no idea what the difference is + * one of bidirectional modes might be good choice + * 2 = 3pin bidi phy. */ + pio_change_32(&device->tll->channel_conf[i], + TLL_CHANNEL_CONF_CHANMODE_UTMI_SERIAL_MODE | + TLL_CHANNEL_CONF_FSLSMODE_3PIN_BIDI_PHY, + TLL_CHANNEL_CONF_CHANMODE_MASK | + TLL_CHANNEL_CONF_FSLSMODE_MASK, 5); + } + return EOK; +} Index: uspace/drv/platform/amdm37x/amdm37x.h =================================================================== --- uspace/drv/platform/amdm37x/amdm37x.h (revision 2a37b9f1eb93bba78ec231d42ef29f30dff550a0) +++ uspace/drv/platform/amdm37x/amdm37x.h (revision 2a37b9f1eb93bba78ec231d42ef29f30dff550a0) @@ -0,0 +1,76 @@ +/* + * Copyright (c) 2012 Jan Vesely + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup amdm37xdrv + * @{ + */ +/** @file + * @brief AM/DM 37x device. + */ +#ifndef AMDM37x_H +#define AMDM37x_H + +#include "uhh.h" +#include "usbtll.h" + +#include "cm/core.h" +#include "cm/clock_control.h" +#include "cm/usbhost.h" +#include "cm/mpu.h" +#include "cm/iva2.h" + +#include "prm/clock_control.h" +#include "prm/global_reg.h" + +#include + +typedef struct { + uhh_regs_t *uhh; + tll_regs_t *tll; + struct { + mpu_cm_regs_t *mpu; + iva2_cm_regs_t *iva2; + core_cm_regs_t *core; + clock_control_cm_regs_t *clocks; + usbhost_cm_regs_t *usbhost; + } cm; + struct { + clock_control_prm_regs_t *clocks; + global_reg_prm_regs_t *global; + } prm; +} amdm37x_t; + +int amdm37x_init(amdm37x_t *device, bool trace_io); +int amdm37x_usb_tll_init(amdm37x_t *device); +void amdm37x_setup_dpll_on_autoidle(amdm37x_t *device); +void amdm37x_usb_clocks_set(amdm37x_t *device, bool enabled); + +#endif +/** + * @} + */ Index: uspace/drv/platform/amdm37x/amdm37x.ma =================================================================== --- uspace/drv/platform/amdm37x/amdm37x.ma (revision 2a37b9f1eb93bba78ec231d42ef29f30dff550a0) +++ uspace/drv/platform/amdm37x/amdm37x.ma (revision 2a37b9f1eb93bba78ec231d42ef29f30dff550a0) @@ -0,0 +1,1 @@ +10 platform/beagleboardxm Index: uspace/drv/platform/amdm37x/cm/clock_control.h =================================================================== --- uspace/drv/platform/amdm37x/cm/clock_control.h (revision 2a37b9f1eb93bba78ec231d42ef29f30dff550a0) +++ uspace/drv/platform/amdm37x/cm/clock_control.h (revision 2a37b9f1eb93bba78ec231d42ef29f30dff550a0) @@ -0,0 +1,161 @@ +/* + * Copyright (c) 2012 Jan Vesely + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup amdm37xdrvclockcontrolcm + * @{ + */ +/** @file + * @brief Clock Control Clock Management IO register structure. + */ +#ifndef AMDM37x_CLOCK_CONTROL_CM_H +#define AMDM37x_CLOCK_CONTROL_CM_H +#include +#include + +/* AM/DM37x TRM p.485 */ +#define CLOCK_CONTROL_CM_BASE_ADDRESS 0x48004d00 +#define CLOCK_CONTROL_CM_SIZE 8192 + +/** Clock control register map + * + * Periph DPLL == DPLL4 + * Core DPLL == DPLL3 + */ +typedef struct { + ioport32_t clken_pll; +#define CLOCK_CONTROL_CM_CLKEN_PLL_PWRDN_EMU_PERIPH_FLAG (1 << 31) +#define CLOCK_CONTROL_CM_CLKEN_PLL_PWRDN_CAM_FLAG (1 << 30) +#define CLOCK_CONTROL_CM_CLKEN_PLL_PWRDN_DSS1_FLAG (1 << 29) +#define CLOCK_CONTROL_CM_CLKEN_PLL_PWRDN_TV_FLAG (1 << 28) +#define CLOCK_CONTROL_CM_CLKEN_PLL_PWRDN_96M_FLAG (1 << 27) +#define CLOCK_CONTROL_CM_CLKEN_PLL_EN_PERIPH_DPLL_DRIFTGUARD_FLAG (1 << 19) +#define CLOCK_CONTROL_CM_CLKEN_PLL_EN_PERIPH_DPLL_MASK (0x7 << 16) +#define CLOCK_CONTROL_CM_CLKEN_PLL_EN_PERIPH_DPLL_LP_STOP (0x1 << 16) +#define CLOCK_CONTROL_CM_CLKEN_PLL_EN_PERIPH_DPLL_LOCK (0x7 << 16) +#define CLOCK_CONTROL_CM_CLKEN_PLL_PWRDN_EMU_CORE_FLAG (1 << 12) +#define CLOCK_CONTROL_CM_CLKEN_PLL_EN_CORE_DPLL_LPMODE_FLAG (1 << 10) +#define CLOCK_CONTROL_CM_CLKEN_PLL_EN_CORE_DPLL_DRIFTGUARD_FLAG (1 << 3) +#define CLOCK_CONTROL_CM_CLKEN_PLL_EN_CORE_DPLL_MASK (0x7) +#define CLOCK_CONTROL_CM_CLKEN_PLL_EN_CORE_DPLL_LP_BYPASS (0x5) +#define CLOCK_CONTROL_CM_CLKEN_PLL_EN_CORE_DPLL_FAST_RELOCK (0x6) +#define CLOCK_CONTROL_CM_CLKEN_PLL_EN_CORE_DPLL_LOCK (0x7) + + ioport32_t clken2_pll; +#define CLOCK_CONTROL_CM_CLKEN2_PLL_EN_PERIPH2_DPLL_LPMODE_FLAG (1 << 10) +#define CLOCK_CONTROL_CM_CLKEN2_PLL_EN_PERIPH2_DPLL_DRIFTGUARD_FLAG (1 << 3) +#define CLOCK_CONTROL_CM_CLKEN2_PLL_EN_PERIPH2_DPLL_MASK (0x7) +#define CLOCK_CONTROL_CM_CLKEN2_PLL_EN_PERIPH2_DPLL_LP_STOP (0x1) +#define CLOCK_CONTROL_CM_CLKEN2_PLL_EN_PERIPH2_DPLL_LOCK (0x7) + + PADD32[6]; + + const ioport32_t idlest_ckgen; +#define CLOCK_CONTROL_CM_IDLEST_CKGEN_ST_EMU_PERIPH_CLK_FLAG (1 << 13) +#define CLOCK_CONTROL_CM_IDLEST_CKGEN_ST_CAM_CLK_FLAG (1 << 12) +#define CLOCK_CONTROL_CM_IDLEST_CKGEN_ST_DSS1_CLK_FLAG (1 << 11) +#define CLOCK_CONTROL_CM_IDLEST_CKGEN_ST_TV_CLK_FLAG (1 << 10) +#define CLOCK_CONTROL_CM_IDLEST_CKGEN_ST_FUNC96M_CLK_FLAG (1 << 9) +#define CLOCK_CONTROL_CM_IDLEST_CKGEN_ST_EMU_CORE_CLK_FLAG (1 << 8) +#define CLOCK_CONTROL_CM_IDLEST_CKGEN_ST_54M_CLK_FLAG (1 << 5) +#define CLOCK_CONTROL_CM_IDLEST_CKGEN_ST_12M_CLK_FLAG (1 << 4) +#define CLOCK_CONTROL_CM_IDLEST_CKGEN_ST_48M_CLK_FLAG (1 << 3) +#define CLOCK_CONTROL_CM_IDLEST_CKGEN_ST_96M_CLK_FLAG (1 << 2) +#define CLOCK_CONTROL_CM_IDLEST_CKGEN_ST_PERIPH_CLK_FLAG (1 << 1) +#define CLOCK_CONTROL_CM_IDLEST_CKGEN_ST_CORE_CLK_FLAG (1 << 0) + + const ioport32_t idlest2_ckgen; +#define CLOCK_CONTROL_CM_IDLEST2_CKGEN_ST_FUNC120M_CLK_FLAG (1 << 3) +#define CLOCK_CONTROL_CM_IDLEST2_CKGEN_ST_120M_CLK_FLAG (1 << 1) +#define CLOCK_CONTROL_CM_IDLEST2_CKGEN_ST_PERIPH2_CLK_FLAG (1 << 0) + + PADD32[2]; + + ioport32_t autoidle_pll; +#define CLOCK_CONTROL_CM_AUTOIDLE_PLL_AUTO_PERIPH_DPLL_MASK (0x7 << 3) +#define CLOCK_CONTROL_CM_AUTOIDLE_PLL_AUTO_PERIPH_DPLL_DISABLED (0x0 << 3) +#define CLOCK_CONTROL_CM_AUTOIDLE_PLL_AUTO_PERIPH_DPLL_AUTOMATIC (0x1 << 3) +#define CLOCK_CONTROL_CM_AUTOIDLE_PLL_AUTO_CORE_DPLL_MASK (0x7) +#define CLOCK_CONTROL_CM_AUTOIDLE_PLL_AUTO_CORE_DPLL_DISABLED (0x0) +#define CLOCK_CONTROL_CM_AUTOIDLE_PLL_AUTO_CORE_DPLL_AUTOMATIC (0x1) +#define CLOCK_CONTROL_CM_AUTOIDLE_PLL_AUTO_CORE_DPLL_AUTOMATIC_BYPASS (0x5) + + ioport32_t autoidle2_pll; +#define CLOCK_CONTROL_CM_AUTOIDLE2_PLL_AUTO_PERIPH2_DPLL_MASK (0x7) +#define CLOCK_CONTROL_CM_AUTOIDLE2_PLL_AUTO_PERIPH2_DPLL_DISABLED (0x0) +#define CLOCK_CONTROL_CM_AUTOIDLE2_PLL_AUTO_PERIPH2_DPLL_AUTOMATIC (0x1) + + PADD32[2]; + + ioport32_t clksel1_pll; +#define CLOCK_CONTROL_CM_CLKSEL1_PLL_CORE_DPLL_CLKOUT_DIV_MASK (0x1f << 27) +#define CLOCK_CONTROL_CM_CLKSEL1_PLL_CORE_DPLL_CLKOUT_DIV_CREATE(x) (((x) & 0x1f) << 27) +#define CLOCK_CONTROL_CM_CLKSEL1_PLL_CORE_DPLL_CLKOUT_DIV_GET(x) (((x) >> 27) & 0x1f) +#define CLOCK_CONTROL_CM_CLKSEL1_PLL_CORE_DPLL_MULT_MASK (0x7ff << 16) +#define CLOCK_CONTROL_CM_CLKSEL1_PLL_CORE_DPLL_MULT_CREATE(x) (((x) & 0x7ff) << 16) +#define CLOCK_CONTROL_CM_CLKSEL1_PLL_CORE_DPLL_MULT_GET(x) (((x) >> 16) & 0x7ff) +#define CLOCK_CONTROL_CM_CLKSEL1_PLL_CORE_DPLL_DIV_MASK (0x7f << 8) +#define CLOCK_CONTROL_CM_CLKSEL1_PLL_CORE_DPLL_DIV_CREATE(x) (((x) & 0x7f) << 8) +#define CLOCK_CONTROL_CM_CLKSEL1_PLL_CORE_DPLL_DIV_GET(x) (((x) >> 8) & 0x7f) +#define CLOCK_CONTROL_CM_CLKSEL1_PLL_SOURCE_96M_FLAG (1 << 6) +#define CLOCK_CONTROL_CM_CLKSEL1_PLL_SOURCE_54M_FLAG (1 << 5) +#define CLOCK_CONTROL_CM_CLKSEL1_PLL_SOURCE_48M_FLAG (1 << 3) + + ioport32_t clksel2_pll; +#define CLOCK_CONTROL_CM_CLKSEL2_PLL_SD_DIV_MASK (0xff << 24) +#define CLOCK_CONTROL_CM_CLKSEL2_PLL_SD_DIV_(x) (((x) & 0xff) << 24) +#define CLOCK_CONTROL_CM_CLKSEL2_PLL_DCO_SEL_MASK (0x7 << 21) +#define CLOCK_CONTROL_CM_CLKSEL2_PLL_DCO_SEL_500 (0x2 << 21) +#define CLOCK_CONTROL_CM_CLKSEL2_PLL_DCO_SEL_1000 (0x4 << 21) +#define CLOCK_CONTROL_CM_CLKSEL2_PLL_PERIPH_DPLL_MULT_MASK (0xfff << 8) +#define CLOCK_CONTROL_CM_CLKSEL2_PLL_PERIPH_DPLL_MULT(x) (((x) & 0xfff) << 8) +#define CLOCK_CONTROL_CM_CLKSEL2_PLL_PERIPH_DPLL_DIV_MASK (0x7f) +#define CLOCK_CONTROL_CM_CLKSEL2_PLL_PERIPH_DPLL_DIV(x) ((x) & 0x7f) + + ioport32_t clksel3_pll; +#define CLOCK_CONTROL_CM_CLKSEL3_PLL_DIV_96M_MASK (0xf) +#define CLOCK_CONTROL_CM_CLKSEL3_PLL_DIV_96M(x) ((x) & 0xf) + + ioport32_t clksel4_pll; +#define CLOCK_CONTROL_CM_CLKSEL4_PLL_PERIPH2_DPLL_MULT_MASK (0x7ff << 8) +#define CLOCK_CONTROL_CM_CLKSEL4_PLL_PERIPH2_DPLL_MULT_CREATE(x) (((x) & 0x7ff) << 8) +#define CLOCK_CONTROL_CM_CLKSEL4_PLL_PERIPH2_DPLL_MULT_GET(x) (((x) >> 8) & 0x7ff) +#define CLOCK_CONTROL_CM_CLKSEL4_PLL_PERIPH2_DPLL_DIV_MASK (0x7f) +#define CLOCK_CONTROL_CM_CLKSEL4_PLL_PERIPH2_DPLL_DIV_CREATE(x) ((x) & 0x7f) +#define CLOCK_CONTROL_CM_CLKSEL4_PLL_PERIPH2_DPLL_DIV_GET(x) ((x) & 0x7f) + + ioport32_t clksel5_pll; +#define CLOCK_CONTROL_CM_CLKSEL5_PLL_DIV120M_MASK (0x1f) +#define CLOCK_CONTROL_CM_CLKSEL5_PLL_DIV120M_CREATE(x) ((x) & 0x1f) +#define CLOCK_CONTROL_CM_CLKSEL5_PLL_DIV120M_GET(x) ((x) & 0x1f) +} clock_control_cm_regs_t; + +#endif +/** + * @} + */ + Index: uspace/drv/platform/amdm37x/cm/core.h =================================================================== --- uspace/drv/platform/amdm37x/cm/core.h (revision 2a37b9f1eb93bba78ec231d42ef29f30dff550a0) +++ uspace/drv/platform/amdm37x/cm/core.h (revision 2a37b9f1eb93bba78ec231d42ef29f30dff550a0) @@ -0,0 +1,188 @@ +/* + * Copyright (c) 2012 Jan Vesely + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup amdm37xdrvcorecm + * @{ + */ +/** @file + * @brief CORE Clock Management IO register structure. + */ +#ifndef AMDM37x_CORE_CM_H +#define AMDM37x_CORE_CM_H +#include +#include + +/* AM/DM37x TRM p.447 */ +#define CORE_CM_BASE_ADDRESS 0x48004a00 +#define CORE_CM_SIZE 8192 + +typedef struct { + ioport32_t fclken1; +#define CORE_CM_FCLKEN1_EN_MCBSP1_FLAG (1 << 9) +#define CORE_CM_FCLKEN1_EN_MCBSP5_FLAG (1 << 10) +#define CORE_CM_FCLKEN1_EN_GPT10_FLAG (1 << 11) +#define CORE_CM_FCLKEN1_EN_GPT11_FLAG (1 << 12) +#define CORE_CM_FCLKEN1_EN_UART1_FLAG (1 << 13) +#define CORE_CM_FCLKEN1_EN_UART2_FLAG (1 << 14) +#define CORE_CM_FCLKEN1_EN_I2C1_FLAG (1 << 15) +#define CORE_CM_FCLKEN1_EN_I2C2_FLAG (1 << 16) +#define CORE_CM_FCLKEN1_EN_I2C3_FLAG (1 << 17) +#define CORE_CM_FCLKEN1_EN_MCSPI1_FLAG (1 << 18) +#define CORE_CM_FCLKEN1_EN_MCSPI2_FLAG (1 << 19) +#define CORE_CM_FCLKEN1_EN_MCSPI3_FLAG (1 << 20) +#define CORE_CM_FCLKEN1_EN_MCSPI4_FLAG (1 << 21) +#define CORE_CM_FCLKEN1_EN_HDQ_FLAG (1 << 22) +#define CORE_CM_FCLKEN1_EN_MMC1_FLAG (1 << 24) +#define CORE_CM_FCLKEN1_EN_MMC2_FLAG (1 << 25) +#define CORE_CM_FCLKEN1_EN_MMC3_FLAG (1 << 30) + + PADD32; + ioport32_t fclken3; +#define CORE_CM_FCLKEN3_EN_TS_FLAG (1 << 1) +#define CORE_CM_FCLKEN3_EN_USBTLL_FLAG (1 << 2) + + PADD32; + ioport32_t iclken1; +#define CORE_CM_ICLKEN1_EN_SDRC_FLAG (1 << 1) +#define CORE_CM_ICLKEN1_EN_HSOTGUSB_FLAG (1 << 4) +#define CORE_CM_ICLKEN1_EN_SCMCTRL_FLAG (1 << 6) +#define CORE_CM_ICLKEN1_EN_MAILBOXES_FLAG (1 << 7) +#define CORE_CM_ICLKEN1_EN_MCBSP1_FLAG (1 << 9) +#define CORE_CM_ICLKEN1_EN_MCBSP5_FLAG (1 << 10) +#define CORE_CM_ICLKEN1_EN_GPT10_FLAG (1 << 11) +#define CORE_CM_ICLKEN1_EN_GPT11_FLAG (1 << 12) +#define CORE_CM_ICLKEN1_EN_UART1_FLAG (1 << 13) +#define CORE_CM_ICLKEN1_EN_UART2_FLAG (1 << 14) +#define CORE_CM_ICLKEN1_EN_I2C1_FLAG (1 << 15) +#define CORE_CM_ICLKEN1_EN_I2C2_FLAG (1 << 16) +#define CORE_CM_ICLKEN1_EN_I2C3_FLAG (1 << 17) +#define CORE_CM_ICLKEN1_EN_MCSPI1_FLAG (1 << 18) +#define CORE_CM_ICLKEN1_EN_MCSPI2_FLAG (1 << 19) +#define CORE_CM_ICLKEN1_EN_MCSPI3_FLAG (1 << 20) +#define CORE_CM_ICLKEN1_EN_MCSPI4_FLAG (1 << 21) +#define CORE_CM_ICLKEN1_EN_HDQ_FLAG (1 << 22) +#define CORE_CM_ICLKEN1_EN_MMC1_FLAG (1 << 24) +#define CORE_CM_ICLKEN1_EN_MMC2_FLAG (1 << 25) +#define CORE_CM_ICLKEN1_EN_ICR_FLAG (1 << 29) +#define CORE_CM_ICLKEN1_EN_MMC3_FLAG (1 << 30) + + ioport32_t reserved1; + ioport32_t iclken3; +#define CORE_CM_ICLKEN3_EN_USBTLL_FLAG (1 << 2) + + PADD32; + const ioport32_t idlest1; +#define CORE_CM_IDLEST1_ST_SDRC_FLAG (1 << 1) +#define CORE_CM_IDLEST1_ST_SDMA_FLAG (1 << 2) +#define CORE_CM_IDLEST1_ST_HSOTGUSB_STBY_FLAG (1 << 4) +#define CORE_CM_IDLEST1_ST_HSOTGUSB_IDLE_FLAG (1 << 5) +#define CORE_CM_IDLEST1_ST_SCMCTRL_FLAG (1 << 6) +#define CORE_CM_IDLEST1_ST_MAILBOXES_FLAG (1 << 7) +#define CORE_CM_IDLEST1_ST_MCBSP1_FLAG (1 << 9) +#define CORE_CM_IDLEST1_ST_MCBSP5_FLAG (1 << 10) +#define CORE_CM_IDLEST1_ST_GPT10_FLAG (1 << 11) +#define CORE_CM_IDLEST1_ST_GPT11_FLAG (1 << 12) +#define CORE_CM_IDLEST1_ST_UART1_FLAG (1 << 13) +#define CORE_CM_IDLEST1_ST_UART2_FLAG (1 << 14) +#define CORE_CM_IDLEST1_ST_I2C1_FLAG (1 << 15) +#define CORE_CM_IDLEST1_ST_I2C2_FLAG (1 << 16) +#define CORE_CM_IDLEST1_ST_I2C3_FLAG (1 << 17) +#define CORE_CM_IDLEST1_ST_MCSPI1_FLAG (1 << 18) +#define CORE_CM_IDLEST1_ST_MCSPI2_FLAG (1 << 19) +#define CORE_CM_IDLEST1_ST_MCSPI3_FLAG (1 << 20) +#define CORE_CM_IDLEST1_ST_MCSPI4_FLAG (1 << 21) +#define CORE_CM_IDLEST1_ST_HDQ_FLAG (1 << 22) +#define CORE_CM_IDLEST1_ST_MMC1_FLAG (1 << 24) +#define CORE_CM_IDLEST1_ST_MMC2_FLAG (1 << 25) +#define CORE_CM_IDLEST1_ST_ICR_FLAG (1 << 29) +#define CORE_CM_IDLEST1_ST_MMC3_FLAG (1 << 30) + + const ioport32_t reserved2; + const ioport32_t idlest3; +#define CORE_CM_IDLEST3_ST_USBTLL_FLAG (1 << 2) + + PADD32; + ioport32_t autoidle1; +#define CORE_CM_AUTOIDLE1_AUTO_HSOTGUSB_FLAG (1 << 4) +#define CORE_CM_AUTOIDLE1_AUTO_SCMCTRL_FLAG (1 << 6) +#define CORE_CM_AUTOIDLE1_AUTO_MAILBOXES_FLAG (1 << 7) +#define CORE_CM_AUTOIDLE1_AUTO_MCBSP1_FLAG (1 << 9) +#define CORE_CM_AUTOIDLE1_AUTO_MCBSP5_FLAG (1 << 10) +#define CORE_CM_AUTOIDLE1_AUTO_GPT10_FLAG (1 << 11) +#define CORE_CM_AUTOIDLE1_AUTO_GPT11_FLAG (1 << 12) +#define CORE_CM_AUTOIDLE1_AUTO_UART1_FLAG (1 << 13) +#define CORE_CM_AUTOIDLE1_AUTO_UART2_FLAG (1 << 14) +#define CORE_CM_AUTOIDLE1_AUTO_I2C1_FLAG (1 << 15) +#define CORE_CM_AUTOIDLE1_AUTO_I2C2_FLAG (1 << 16) +#define CORE_CM_AUTOIDLE1_AUTO_I2C3_FLAG (1 << 17) +#define CORE_CM_AUTOIDLE1_AUTO_MCSPI1_FLAG (1 << 18) +#define CORE_CM_AUTOIDLE1_AUTO_MCSPI2_FLAG (1 << 19) +#define CORE_CM_AUTOIDLE1_AUTO_MCSPI3_FLAG (1 << 20) +#define CORE_CM_AUTOIDLE1_AUTO_MCSPI4_FLAG (1 << 21) +#define CORE_CM_AUTOIDLE1_AUTO_HDQ_FLAG (1 << 22) +#define CORE_CM_AUTOIDLE1_AUTO_MMC1_FLAG (1 << 24) +#define CORE_CM_AUTOIDLE1_AUTO_MMC2_FLAG (1 << 25) +#define CORE_CM_AUTOIDLE1_AUTO_ICR_FLAG (1 << 29) +#define CORE_CM_AUTOIDLE1_AUTO_MMC3_FLAG (1 << 30) + + ioport32_t reserved3; + ioport32_t autoidle3; +#define CORE_CM_AUTOIDLE3_AUTO_USBTLL_FLAG (1 << 2) + + PADD32; + ioport32_t clksel; +#define CORE_CM_CLKSEL_CLKSEL_L3_MASK (0x3 << 0) +#define CORE_CM_CLKSEL_CLKSEL_L3_DIVIDED1 (0x1 << 0) +#define CORE_CM_CLKSEL_CLKSEL_L3_DIVIDED2 (0x2 << 0) +#define CORE_CM_CLKSEL_CLKSEL_L4_MASK (0x3 << 2) +#define CORE_CM_CLKSEL_CLKSEL_L4_DIVIDED1 (0x1 << 2) +#define CORE_CM_CLKSEL_CLKSEL_L4_DIVIDED2 (0x2 << 2) +#define CORE_CM_CLKSEL_CLKSEL_96M_MASK (0x3 << 12) +#define CORE_CM_CLKSEL_CLKSEL_96M_DIVIDED1 (0x1 << 12) +#define CORE_CM_CLKSEL_CLKSEL_96M_DIVIDED2 (0x2 << 12) +#define CORE_CM_CLKSEL_CLKSEL_GPT10_FLAG (1 << 6) +#define CORE_CM_CLKSEL_CLKSEL_GPT11_FLAG (1 << 7) + + PADD32; + ioport32_t clkstctrl; +#define CORE_CM_CLKCTRL_CLKCTRL_L3_MASK (0x3 << 0) +#define CORE_CM_CLKCTRL_CLKCTRL_L3_AUTO_EN (0x0 << 0) +#define CORE_CM_CLKCTRL_CLKCTRL_L3_AUTO_DIS (0x3 << 0) +#define CORE_CM_CLKCTRL_CLKCTRL_L4_MASK (0x3 << 2) +#define CORE_CM_CLKCTRL_CLKCTRL_L4_AUTO_EN (0x0 << 2) +#define CORE_CM_CLKCTRL_CLKCTRL_L4_AUTO_DIS (0x3 << 2) + + const ioport32_t clkstst; +#define CORE_CM_CLKSTST_CLKACTIVITY_L3_FLAG (1 << 0) +#define CORE_CM_CLKSTST_CLKACTIVITY_L4_FLAG (1 << 1) +} core_cm_regs_t; + +#endif +/** + * @} + */ Index: uspace/drv/platform/amdm37x/cm/iva2.h =================================================================== --- uspace/drv/platform/amdm37x/cm/iva2.h (revision 2a37b9f1eb93bba78ec231d42ef29f30dff550a0) +++ uspace/drv/platform/amdm37x/cm/iva2.h (revision 2a37b9f1eb93bba78ec231d42ef29f30dff550a0) @@ -0,0 +1,101 @@ +/* + * Copyright (c) 2012 Jan Vesely + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup amdm37xdrvcm + * @{ + */ +/** @file + * @brief MPU Clock Management IO register structure. + */ +#ifndef AMDM37x_IVA2_CM_H +#define AMDM37x_IVA2_CM_H +#include +#include + +/* AM/DM37x TRM p.446 */ +#define IVA2_CM_BASE_ADDRESS 0x48004000 +#define IVA2_CM_SIZE 8192 + +typedef struct { + ioport32_t fclken; +#define IVA2_CM_FCLKEN_EN_IVA2_FLAG (1 << 0) + + ioport32_t clken_pll; +#define IVA2_CM_CLKEN_PLL_EN_IVA2_DPLL_LP_MODE_FLAG (1 << 10) +#define IVA2_CM_CLKEN_PLL_EN_IVA2_DPLL_DRIFTGUARD (1 << 3) +#define IVA2_CM_CLKEN_PLL_EN_IVA2_DPLL_EN_IVA2_DPLL_MASK (0x7) +#define IVA2_CM_CLKEN_PLL_EN_IVA2_DPLL_EN_IVA2_DPLL_LP_STOP (0x1) +#define IVA2_CM_CLKEN_PLL_EN_IVA2_DPLL_EN_IVA2_DPLL_LP_BYPASS (0x5) +#define IVA2_CM_CLKEN_PLL_EN_IVA2_DPLL_EN_IVA2_DPLL_LOCKED (0x7) + + PADD32[6]; + const ioport32_t idlest; +#define IVA2_CM_IDLEST_ST_IVA2_STANDBY_FLAG (1 << 0) + + const ioport32_t idlest_pll; +#define IVA2_CM_IDLEST_PLL_ST_IVA2_CLK_LOCKED_FLAG (1 << 0) + + PADD32[3]; + ioport32_t autoidle_pll; +#define IVA2_CM_AUTOIDLE_PLL_AUTO_IVA2_DPLL_MASK (0x7) +#define IVA2_CM_AUTOIDLE_PLL_AUTO_IVA2_DPLL_DISABLED (0x0) +#define IVA2_CM_AUTOIDLE_PLL_AUTO_IVA2_DPLL_ENABLED (0x1) + + PADD32[2]; + ioport32_t clksel1_pll; +#define IVA2_CM_CLKSEL1_PLL_IVA2_CLK_SRC_MASK (0x7 << 19) +#define IVA2_CM_CLKSEL1_PLL_IVA2_CLK_SRC_SHIFT (19) +#define IVA2_CM_CLKSEL1_PLL_IVA2_CLK_SRC_VAL(x) ((x >> 19) & 0x7) +#define IVA2_CM_CLKSEL1_PLL_IVA2_CLK_SRC_CORE_DIV_1 (0x1 << 19) +#define IVA2_CM_CLKSEL1_PLL_IVA2_CLK_SRC_CORE_DIV_2 (0x2 << 19) +#define IVA2_CM_CLKSEL1_PLL_IVA2_CLK_SRC_CORE_DIV_4 (0x4 << 19) +#define IVA2_CM_CLKSEL1_PLL_IVA2_DPLL_MULT_MASK (0x7ff << 8) +#define IVA2_CM_CLKSEL1_PLL_IVA2_DPLL_MULT_SHIFT (8) +#define IVA2_CM_CLKSEL1_PLL_IVA2_DPLL_DIV_MASK (0x7f << 0) +#define IVA2_CM_CLKSEL1_PLL_IVA2_DPLL_DIV_SHIFT (0) + + ioport32_t clksel2_pll; +#define IVA2_CM_CLKSEL2_PLL_IVA2_DPLL_CLKOUT_DIV_MASK (0x1f) + + ioport32_t clkstctrl; +#define IVA2_CM_CLKSCTRL_CLKTRCTRL_IVA2_MASK (0x3) +#define IVA2_CM_CLKSCTRL_CLKTRCTRL_IVA2_DISABLED (0x0) +#define IVA2_CM_CLKSCTRL_CLKTRCTRL_IVA2_START_SLEEP (0x2) +#define IVA2_CM_CLKSCTRL_CLKTRCTRL_IVA2_START_WAKEUP (0x2) +#define IVA2_CM_CLKSCTRL_CLKTRCTRL_IVA2_AUTOMATIC (0x3) + + const ioport32_t clkstst; +#define IVA2_CM_CLKSTST_CLKACTIVITY_IVA2_ACTIVE_FLAG (1 << 0) + +} iva2_cm_regs_t; + +#endif +/** + * @} + */ + Index: uspace/drv/platform/amdm37x/cm/mpu.h =================================================================== --- uspace/drv/platform/amdm37x/cm/mpu.h (revision 2a37b9f1eb93bba78ec231d42ef29f30dff550a0) +++ uspace/drv/platform/amdm37x/cm/mpu.h (revision 2a37b9f1eb93bba78ec231d42ef29f30dff550a0) @@ -0,0 +1,97 @@ +/* + * Copyright (c) 2012 Jan Vesely + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup amdm37xdrvcm + * @{ + */ +/** @file + * @brief MPU Clock Management IO register structure. + */ +#ifndef AMDM37x_MPU_CM_H +#define AMDM37x_MPU_CM_H +#include +#include + +/* AM/DM37x TRM p.455 */ +#define MPU_CM_BASE_ADDRESS 0x48004900 +#define MPU_CM_SIZE 8192 + +typedef struct { + PADD32; + ioport32_t clken_pll; +#define MPU_CM_CLKEN_PLL_EN_MPU_DPLL_LP_MODE_FLAG (1 << 10) +#define MPU_CM_CLKEN_PLL_EN_MPU_DPLL_DRIFTGUARD (1 << 3) +#define MPU_CM_CLKEN_PLL_EN_MPU_DPLL_EN_MPU_DPLL_MASK (0x7) +#define MPU_CM_CLKEN_PLL_EN_MPU_DPLL_EN_MPU_DPLL_LP_BYPASS (0x5) +#define MPU_CM_CLKEN_PLL_EN_MPU_DPLL_EN_MPU_DPLL_LOCKED (0x7) + + PADD32[6]; + const ioport32_t idlest; +#define MPU_CM_IDLEST_ST_MPU_STANDBY_FLAG (1 << 0) + + const ioport32_t idlest_pll; +#define MPU_CM_IDLEST_PLL_ST_MPU_CLK_LOCKED_FLAG (1 << 0) + + PADD32[3]; + ioport32_t autoidle_pll; +#define MPU_CM_AUTOIDLE_PLL_AUTO_MPU_DPLL_MASK (0x7) +#define MPU_CM_AUTOIDLE_PLL_AUTO_MPU_DPLL_DISABLED (0x0) +#define MPU_CM_AUTOIDLE_PLL_AUTO_MPU_DPLL_ENABLED (0x1) + + PADD32[2]; + ioport32_t clksel1_pll; +#define MPU_CM_CLKSEL1_PLL_MPU_CLK_SRC_MASK (0x7 << 19) +#define MPU_CM_CLKSEL1_PLL_MPU_CLK_SRC_SHIFT (19) +#define MPU_CM_CLKSEL1_PLL_MPU_CLK_SRC_VAL(x) ((x >> 19) & 0x7) +#define MPU_CM_CLKSEL1_PLL_MPU_CLK_SRC_CORE_DIV_1 (0x1 << 19) +#define MPU_CM_CLKSEL1_PLL_MPU_CLK_SRC_CORE_DIV_2 (0x2 << 19) +#define MPU_CM_CLKSEL1_PLL_MPU_CLK_SRC_CORE_DIV_4 (0x4 << 19) +#define MPU_CM_CLKSEL1_PLL_MPU_DPLL_MULT_MASK (0x7ff << 8) +#define MPU_CM_CLKSEL1_PLL_MPU_DPLL_MULT_SHIFT (8) +#define MPU_CM_CLKSEL1_PLL_MPU_DPLL_DIV_MASK (0x7f << 0) +#define MPU_CM_CLKSEL1_PLL_MPU_DPLL_DIV_SHIFT (0) + + ioport32_t clksel2_pll; +#define MPU_CM_CLKSEL2_PLL_MPU_DPLL_CLKOUT_DIV_MASK (0x1f) + + ioport32_t clkstctrl; +#define MPU_CM_CLKSCTRL_CLKTRCTRL_MPU_MASK (0x3) +#define MPU_CM_CLKSCTRL_CLKTRCTRL_MPU_DISABLED (0x0) +#define MPU_CM_CLKSCTRL_CLKTRCTRL_MPU_START_WAKEUP (0x2) +#define MPU_CM_CLKSCTRL_CLKTRCTRL_MPU_AUTOMATIC (0x3) + + const ioport32_t clkstst; +#define MPU_CM_CLKSTST_CLKACTIVITY_MPU_ACTIVE_FLAG (1 << 0) + +} mpu_cm_regs_t; + +#endif +/** + * @} + */ + Index: uspace/drv/platform/amdm37x/cm/usbhost.h =================================================================== --- uspace/drv/platform/amdm37x/cm/usbhost.h (revision 2a37b9f1eb93bba78ec231d42ef29f30dff550a0) +++ uspace/drv/platform/amdm37x/cm/usbhost.h (revision 2a37b9f1eb93bba78ec231d42ef29f30dff550a0) @@ -0,0 +1,82 @@ +/* + * Copyright (c) 2012 Jan Vesely + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup amdm37xdrvusbhostcm + * @{ + */ +/** @file + * @brief USBHOST Clock Management IO register structure. + */ +#ifndef AMDM37x_USBHOST_CM_H +#define AMDM37x_USBHOST_CM_H +#include +#include + +/* AM/DM37x TRM p.447 */ +#define USBHOST_CM_BASE_ADDRESS 0x48005400 +#define USBHOST_CM_SIZE 8192 + +typedef struct { + ioport32_t fclken; +#define USBHOST_CM_FCLKEN_EN_USBHOST1_FLAG (1 << 0) +#define USBHOST_CM_FCLKEN_EN_USBHOST2_FLAG (1 << 1) + + PADD32[3]; + ioport32_t iclken; +#define USBHOST_CM_ICLKEN_EN_USBHOST (1 << 0) + + PADD32[3]; + const ioport32_t idlest; +#define USBHOST_CM_IDLEST_ST_USBHOST_STDBY_FLAG (1 << 0) +#define USBHOST_CM_IDLEST_ST_USBHOST_IDLE_FLAG (1 << 1) + + PADD32[3]; + ioport32_t autoidle; +#define USBHOST_CM_AUTOIDLE_AUTO_USBHOST_FLAG (1 << 0) + + PADD32[4]; + ioport32_t sleepdep; +#define USBHOST_CM_SLEEPDEP_EN_MPU_FLAG (1 << 1) +#define USBHOST_CM_SLEEPDEP_EN_IVA2_FLAG (1 << 2) + + ioport32_t clkstctrl; +#define USBHOST_CM_CLKSTCTRL_CLKSTCTRL_USBHOST_MASK (0x3 << 0) +#define USBHOST_CM_CLKSTCTRL_CLKSTCTRL_USBHOST_AUTO_DIS (0x0 << 0) +#define USBHOST_CM_CLKSTCTRL_CLKSTCTRL_USBHOST_SUPERVISED_SLEEP (0x1 << 0) +#define USBHOST_CM_CLKSTCTRL_CLKSTCTRL_USBHOST_SUPERVISED_WAKEUP (0x2 << 0) +#define USBHOST_CM_CLKSTCTRL_CLKSTCTRL_USBHOST_AUTO_EN (0x3 << 0) + + ioport32_t clkstst; +#define USBHOST_CM_CLKSTCTRL_CLKSTST_CLKACTIVITY_USBHOST (1 << 0) +} usbhost_cm_regs_t; + +#endif +/** + * @} + */ + Index: uspace/drv/platform/amdm37x/main.c =================================================================== --- uspace/drv/platform/amdm37x/main.c (revision 2a37b9f1eb93bba78ec231d42ef29f30dff550a0) +++ uspace/drv/platform/amdm37x/main.c (revision 2a37b9f1eb93bba78ec231d42ef29f30dff550a0) @@ -0,0 +1,282 @@ +/* + * Copyright (c) 2012 Jan Vesely + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** + * @defgroup root_amdm37x TI AM/DM37x platform driver. + * @brief HelenOS TI AM/DM37x platform driver. + * @{ + */ + +/** @file + */ + +#define DEBUG_CM 0 + +#include +#include +#include +#include + +#include "amdm37x.h" + +#define NAME "amdm37x" + +typedef struct { + const char *name; + match_id_t match_id; + hw_resource_list_t hw_resources; +} amdm37x_fun_t; + +/* See amdm37x TRM page 3316 for these values */ +#define OHCI_BASE_ADDRESS 0x48064400 +#define OHCI_SIZE 1024 +#define EHCI_BASE_ADDRESS 0x48064800 +#define EHCI_SIZE 1024 + +/* See amdm37x TRM page 1813 for these values */ +#define DSS_BASE_ADDRESS 0x48050000 +#define DSS_SIZE 512 +#define DISPC_BASE_ADDRESS 0x48050400 +#define DISPC_SIZE 1024 +#define VIDEO_ENC_BASE_ADDRESS 0x48050C00 +#define VIDEO_ENC_SIZE 256 + + +static hw_resource_t ohci_res[] = { + { + .type = MEM_RANGE, + .res.io_range = { + .address = OHCI_BASE_ADDRESS, + .size = OHCI_SIZE, + .endianness = LITTLE_ENDIAN + }, + }, + { + .type = INTERRUPT, + .res.interrupt = { .irq = 76 }, + }, +}; + +static hw_resource_t ehci_res[] = { + { + .type = MEM_RANGE, + /* See amdm37x TRM page. 3316 for these values */ + .res.io_range = { + .address = EHCI_BASE_ADDRESS, + .size = EHCI_SIZE, + .endianness = LITTLE_ENDIAN + }, + }, + { + .type = INTERRUPT, + .res.interrupt = { .irq = 77 }, + }, +}; + +static hw_resource_t disp_res[] = { + { + .type = MEM_RANGE, + .res.io_range = { + .address = DSS_BASE_ADDRESS, + .size = DSS_SIZE, + .endianness = LITTLE_ENDIAN + }, + }, + { + .type = MEM_RANGE, + .res.io_range = { + .address = DISPC_BASE_ADDRESS, + .size = DISPC_SIZE, + .endianness = LITTLE_ENDIAN + }, + }, + { + .type = MEM_RANGE, + .res.io_range = { + .address = VIDEO_ENC_BASE_ADDRESS, + .size = VIDEO_ENC_SIZE, + .endianness = LITTLE_ENDIAN + }, + }, + { + .type = INTERRUPT, + .res.interrupt = { .irq = 25 }, + }, +}; + +static const amdm37x_fun_t amdm37x_funcs[] = { +{ + .name = "ohci", + .match_id = { .id = "usb/host=ohci", .score = 90 }, + .hw_resources = { .resources = ohci_res, .count = ARRAY_SIZE(ohci_res) } +}, +{ + .name = "ehci", + .match_id = { .id = "usb/host=ehci", .score = 90 }, + .hw_resources = { .resources = ehci_res, .count = ARRAY_SIZE(ehci_res) } +}, +{ + .name = "fb", + .match_id = { .id = "amdm37x&dispc", .score = 90 }, + .hw_resources = { .resources = disp_res, .count = ARRAY_SIZE(disp_res) } +}, +}; + + +static hw_resource_list_t *amdm37x_get_resources(ddf_fun_t *fnode); +static bool amdm37x_enable_interrupt(ddf_fun_t *fun); + +static hw_res_ops_t fun_hw_res_ops = { + .get_resource_list = &amdm37x_get_resources, + .enable_interrupt = &amdm37x_enable_interrupt, +}; + +static ddf_dev_ops_t amdm37x_fun_ops = { + .interfaces[HW_RES_DEV_IFACE] = &fun_hw_res_ops +}; + +static int amdm37x_add_fun(ddf_dev_t *dev, const amdm37x_fun_t *fun) +{ + assert(dev); + assert(fun); + + ddf_msg(LVL_DEBUG, "Adding new function '%s'.", fun->name); + + /* Create new device function. */ + ddf_fun_t *fnode = ddf_fun_create(dev, fun_inner, fun->name); + if (fnode == NULL) + return ENOMEM; + + /* Add match id */ + int ret = ddf_fun_add_match_id(fnode, + fun->match_id.id, fun->match_id.score); + if (ret != EOK) { + ddf_fun_destroy(fnode); + return ret; + } + + /* Alloc needed data */ + amdm37x_fun_t *rf = + ddf_fun_data_alloc(fnode, sizeof(amdm37x_fun_t)); + if (!rf) { + ddf_fun_destroy(fnode); + return ENOMEM; + } + *rf = *fun; + + /* Set provided operations to the device. */ + ddf_fun_set_ops(fnode, &amdm37x_fun_ops); + + /* Register function. */ + ret = ddf_fun_bind(fnode); + if (ret != EOK) { + ddf_msg(LVL_ERROR, "Failed binding function %s.", fun->name); + ddf_fun_destroy(fnode); + return ret; + } + + return EOK; +} + +/** Add the root device. + * + * @param dev Device which is root of the whole device tree + * (both of HW and pseudo devices). + * + * @return Zero on success, negative error number otherwise. + * + */ +static int amdm37x_dev_add(ddf_dev_t *dev) +{ + assert(dev); + amdm37x_t *device = ddf_dev_data_alloc(dev, sizeof(amdm37x_t)); + if (!device) + return ENOMEM; + int ret = amdm37x_init(device, DEBUG_CM); + if (ret != EOK) { + ddf_msg(LVL_FATAL, "Failed to setup hw access!.\n"); + return ret; + } + + /* Set dplls to ON and automatic */ + amdm37x_setup_dpll_on_autoidle(device); + + /* Enable function and interface clocks */ + amdm37x_usb_clocks_set(device, true); + + /* Init TLL */ + ret = amdm37x_usb_tll_init(device); + if (ret != EOK) { + ddf_msg(LVL_FATAL, "Failed to init USB TLL!.\n"); + amdm37x_usb_clocks_set(device, false); + return ret; + } + + /* Register functions */ + for (unsigned i = 0; i < ARRAY_SIZE(amdm37x_funcs); ++i) { + if (amdm37x_add_fun(dev, &amdm37x_funcs[i]) != EOK) + ddf_msg(LVL_ERROR, "Failed to add %s function for " + "BeagleBoard-xM platform.", amdm37x_funcs[i].name); + } + return EOK; +} + +/** The root device driver's standard operations. */ +static driver_ops_t amdm37x_ops = { + .dev_add = &amdm37x_dev_add +}; + +/** The root device driver structure. */ +static driver_t amdm37x_driver = { + .name = NAME, + .driver_ops = &amdm37x_ops +}; + +static hw_resource_list_t * amdm37x_get_resources(ddf_fun_t *fnode) +{ + amdm37x_fun_t *fun = ddf_fun_data_get(fnode); + assert(fun != NULL); + return &fun->hw_resources; +} + +static bool amdm37x_enable_interrupt(ddf_fun_t *fun) +{ + //TODO: Implement + return false; +} + +int main(int argc, char *argv[]) +{ + printf("%s: HelenOS AM/DM37x(OMAP37x) platform driver\n", NAME); + ddf_log_init(NAME); + return ddf_driver_main(&amdm37x_driver); +} + +/** + * @} + */ Index: uspace/drv/platform/amdm37x/prm/clock_control.h =================================================================== --- uspace/drv/platform/amdm37x/prm/clock_control.h (revision 2a37b9f1eb93bba78ec231d42ef29f30dff550a0) +++ uspace/drv/platform/amdm37x/prm/clock_control.h (revision 2a37b9f1eb93bba78ec231d42ef29f30dff550a0) @@ -0,0 +1,81 @@ +/* + * Copyright (c) 2012 Jan Vesely + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup amdm37xdrvprm + * @{ + */ +/** @file + * @brief Clock Control Clock Management IO register structure. + */ +#ifndef AMDM37X_PRM_CLOCK_CONTROL_H +#define AMDM37X_PRM_CLOCK_CONTROL_H +#include +#include + +/* AM/DM37x TRM p.536 and p.589 */ +#define CLOCK_CONTROL_PRM_BASE_ADDRESS 0x48306d00 +#define CLOCK_CONTROL_PRM_SIZE 8192 + +/** Clock control PRM register map + */ +typedef struct { + PADD32[16]; + ioport32_t clksel; +#define CLOCK_CONTROL_PRM_CLKSEL_SYS_CLKIN_MASK (0x7) +#define CLOCK_CONTROL_PRM_CLKSEL_SYS_CLKIN_12M (0x0) +#define CLOCK_CONTROL_PRM_CLKSEL_SYS_CLKIN_13M (0x1) +#define CLOCK_CONTROL_PRM_CLKSEL_SYS_CLKIN_19_2M (0x2) +#define CLOCK_CONTROL_PRM_CLKSEL_SYS_CLKIN_26M (0x3) +#define CLOCK_CONTROL_PRM_CLKSEL_SYS_CLKIN_38_4M (0x4) +#define CLOCK_CONTROL_PRM_CLKSEL_SYS_CLKIN_16_8M (0x5) + + PADD32[12]; + ioport32_t clkout_ctrl; +#define CLOCK_CONTROL_PRM_CLKOUT_CTRL_CLKOUOUT_EN_FLAG (1 << 7) + +} clock_control_prm_regs_t; + +static inline unsigned sys_clk_freq_kHz(unsigned reg_val) +{ + switch(reg_val) + { + case CLOCK_CONTROL_PRM_CLKSEL_SYS_CLKIN_12M: return 12000; + case CLOCK_CONTROL_PRM_CLKSEL_SYS_CLKIN_13M: return 13000; + case CLOCK_CONTROL_PRM_CLKSEL_SYS_CLKIN_19_2M: return 19200; + case CLOCK_CONTROL_PRM_CLKSEL_SYS_CLKIN_26M: return 26000; + case CLOCK_CONTROL_PRM_CLKSEL_SYS_CLKIN_38_4M: return 38400; + case CLOCK_CONTROL_PRM_CLKSEL_SYS_CLKIN_16_8M: return 16800; + } + return 0; +} + + +#endif +/** + * @} + */ Index: uspace/drv/platform/amdm37x/prm/global_reg.h =================================================================== --- uspace/drv/platform/amdm37x/prm/global_reg.h (revision 2a37b9f1eb93bba78ec231d42ef29f30dff550a0) +++ uspace/drv/platform/amdm37x/prm/global_reg.h (revision 2a37b9f1eb93bba78ec231d42ef29f30dff550a0) @@ -0,0 +1,300 @@ +/* + * Copyright (c) 2012 Jan Vesely + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup amdm37xdrvprm + * @{ + */ +/** @file + * @brief Clock Control Clock Management IO register structure. + */ +#ifndef AMDM37X_PRM_GLOBAL_REG_H +#define AMDM37X_PRM_GLOBAL_REG_H +#include +#include + +/* AM/DM37x TRM p.536 and p.615 */ +#define GLOBAL_REG_PRM_BASE_ADDRESS 0x48307200 +#define GLOBAL_REG_PRM_SIZE 65536 + +/** Global Reg PRM register map + */ +typedef struct { + PADD32[8]; + struct { + ioport32_t smps_sa; +#define GLOBAL_REG_PRM_VC_SMPS_SA_SA0_MASK (0x7f << 0) +#define GLOBAL_REG_PRM_VC_SMPS_SA_SA0_CREATE(x) (((x) & 0x7f) << 0) +#define GLOBAL_REG_PRM_VC_SMPS_SA_SA0_GET(r) (r & 0x7f) +#define GLOBAL_REG_PRM_VC_SMPS_SA_SA1_MASK (0x7f << 16) +#define GLOBAL_REG_PRM_VC_SMPS_SA_SA1_CREATE(x) (((x) & 0x7f) << 16) +#define GLOBAL_REG_PRM_VC_SMPS_SA_SA1_GET(r) (((r) >> 16 ) & 0x7f) + + ioport32_t smps_vol_ra; +#define GLOBAL_REG_PRM_VC_SMPS_VOL_RA_VOLRA0_MASK (0xff << 0) +#define GLOBAL_REG_PRM_VC_SMPS_VOL_RA_VOLRA0_CREATE(x) (((x) & 0xff) << 0) +#define GLOBAL_REG_PRM_VC_SMPS_VOL_RA_VOLRA0_GET(r) (r & 0xff) +#define GLOBAL_REG_PRM_VC_SMPS_VOL_RA_VOLRA1_MASK (0xff << 16) +#define GLOBAL_REG_PRM_VC_SMPS_VOL_RA_VOLRA1_CREATE(x) (((x) & 0xff) << 16) +#define GLOBAL_REG_PRM_VC_SMPS_VOL_RA_VOLRA1_GET(r) (((r) >> 16 ) & 0xff) + + ioport32_t smps_cmd_ra; +#define GLOBAL_REG_PRM_VC_SMPS_CMD_RA_CMDRA0_MASK (0xff << 0) +#define GLOBAL_REG_PRM_VC_SMPS_CMD_RA_CMDRA0_CREATE(x) (((x) & 0xff) << 0) +#define GLOBAL_REG_PRM_VC_SMPS_CMD_RA_CMDRA0_GET(r) (r & 0xff) +#define GLOBAL_REG_PRM_VC_SMPS_CMD_RA_CMDRA1_MASK (0xff << 16) +#define GLOBAL_REG_PRM_VC_SMPS_CMD_RA_CMDRA1_CREATE(x) (((x) & 0xff) << 16) +#define GLOBAL_REG_PRM_VC_SMPS_CMD_RA_CMDRA1_GET(r) (((r) >> 16 ) & 0xff) + + ioport32_t cmd_val_0; +#define GLOBAL_REG_PRM_VC_CMD_VAL_0_ON_MASK (0xff << 24) +#define GLOBAL_REG_PRM_VC_CMD_VAL_0_ON_CREATE(x) (((x) & 0xff) << 24) +#define GLOBAL_REG_PRM_VC_CMD_VAL_0_ON_GET(r) (((x) >> 24) & 0xff) +#define GLOBAL_REG_PRM_VC_CMD_VAL_0_ONLP_MASK (0xff << 24) +#define GLOBAL_REG_PRM_VC_CMD_VAL_0_ONLP_CREATE(x) (((x) & 0xff) << 24) +#define GLOBAL_REG_PRM_VC_CMD_VAL_0_ONLP_GET(r) (((x) >> 24) & 0xff) +#define GLOBAL_REG_PRM_VC_CMD_VAL_0_RET_MASK (0xff << 24) +#define GLOBAL_REG_PRM_VC_CMD_VAL_0_RET_CREATE(x) (((x) & 0xff) << 24) +#define GLOBAL_REG_PRM_VC_CMD_VAL_0_RET_GET(r) (((x) >> 24) & 0xff) +#define GLOBAL_REG_PRM_VC_CMD_VAL_0_OFF_MASK (0xff << 24) +#define GLOBAL_REG_PRM_VC_CMD_VAL_0_OFF_CREATE(x) (((x) & 0xff) << 24) +#define GLOBAL_REG_PRM_VC_CMD_VAL_0_OFF_GET(r) (((x) >> 24) & 0xff) + + ioport32_t cmd_val_1; +#define GLOBAL_REG_PRM_VC_CMD_VAL_1_ON_MASK (0xff << 24) +#define GLOBAL_REG_PRM_VC_CMD_VAL_1_ON_CREATE(x) (((x) & 0xff) << 24) +#define GLOBAL_REG_PRM_VC_CMD_VAL_1_ON_GET(r) (((x) >> 24) & 0xff) +#define GLOBAL_REG_PRM_VC_CMD_VAL_1_ONLP_MASK (0xff << 24) +#define GLOBAL_REG_PRM_VC_CMD_VAL_1_ONLP_CREATE(x) (((x) & 0xff) << 24) +#define GLOBAL_REG_PRM_VC_CMD_VAL_1_ONLP_GET(r) (((x) >> 24) & 0xff) +#define GLOBAL_REG_PRM_VC_CMD_VAL_1_RET_MASK (0xff << 24) +#define GLOBAL_REG_PRM_VC_CMD_VAL_1_RET_CREATE(x) (((x) & 0xff) << 24) +#define GLOBAL_REG_PRM_VC_CMD_VAL_1_RET_GET(r) (((x) >> 24) & 0xff) +#define GLOBAL_REG_PRM_VC_CMD_VAL_1_OFF_MASK (0xff << 24) +#define GLOBAL_REG_PRM_VC_CMD_VAL_1_OFF_CREATE(x) (((x) & 0xff) << 24) +#define GLOBAL_REG_PRM_VC_CMD_VAL_1_OFF_GET(r) (((x) >> 24) & 0xff) + + ioport32_t ch_conf; +#define GLOBAL_REG_PRM_VC_CH_CONF_CMD1_FLAG (1 << 20) +#define GLOBAL_REG_PRM_VC_CH_CONF_RACEN1_FLAG (1 << 19) +#define GLOBAL_REG_PRM_VC_CH_CONF_RAC1_FLAG (1 << 18) +#define GLOBAL_REG_PRM_VC_CH_CONF_RAV1_FLAG (1 << 17) +#define GLOBAL_REG_PRM_VC_CH_CONF_SA1_FLAG (1 << 16) +#define GLOBAL_REG_PRM_VC_CH_CONF_CMD0_FLAG (1 << 4) +#define GLOBAL_REG_PRM_VC_CH_CONF_RACEN0_FLAG (1 << 3) +#define GLOBAL_REG_PRM_VC_CH_CONF_RAC0_FLAG (1 << 2) +#define GLOBAL_REG_PRM_VC_CH_CONF_RAV0_FLAG (1 << 1) +#define GLOBAL_REG_PRM_VC_CH_CONF_SA0_FLAG (1 << 0) + + ioport32_t i2c_cfg; +#define GLOBAL_REG_PRM_VC_I2C_CFG_HSMASTER_FLAG (1 << 5) +#define GLOBAL_REG_PRM_VC_I2C_CFG_SREN_FLAG (1 << 4) +#define GLOBAL_REG_PRM_VC_I2C_CFG_HSEN_FLAG (1 << 3) +#define GLOBAL_REG_PRM_VC_I2C_CFG_MCODE_MASK (0x3 << 0) +#define GLOBAL_REG_PRM_VC_I2C_CFG_MCODE_CREATE(x) ((x) & 0x3) +#define GLOBAL_REG_PRM_VC_I2C_CFG_MCODE_GET(r) ((r) & 0x3) + + ioport32_t bypass_val; +#define GLOBAL_REG_PRM_VC_BYPASS_VAL_VALID_FLAG (1 << 24) +#define GLOBAL_REG_PRM_VC_BYPASS_VAL_DATA_MASK (0xff << 16) +#define GLOBAL_REG_PRM_VC_BYPASS_VAL_DATA_CREATE(x) (((x) & 0xff) << 16) +#define GLOBAL_REG_PRM_VC_BYPASS_VAL_DATA_GET(r) (((r) >> 16) & 0xff) +#define GLOBAL_REG_PRM_VC_BYPASS_VAL_REGADDR_MASK (0xff << 8) +#define GLOBAL_REG_PRM_VC_BYPASS_VAL_REGADDR_CREATE(x) (((x) & 0xff) << 8) +#define GLOBAL_REG_PRM_VC_BYPASS_VAL_REGADDR_GET(r) (((r) >> 8) & 0xff) +#define GLOBAL_REG_PRM_VC_BYPASS_VAL_SLAVEADDR_MASK (0x7f << 0) +#define GLOBAL_REG_PRM_VC_BYPASS_VAL_SLAVEADDR_CREATE(x) (((x) & 0x7f) << 0) +#define GLOBAL_REG_PRM_VC_BYPASS_VAL_SLAVEADDR_GET(r) (((r) >> 0) & 0x7f) + } vc; + + PADD32[4]; + ioport32_t rstctrl; +#define GLOBAL_REG_PRM_RSTCTRL_RST_DPLL3_FLAG (1 << 2) +#define GLOBAL_REG_PRM_RSTCTRL_RST_GS_FLAG (1 << 1) + + ioport32_t rsttime; +#define GLOBAL_REG_PRM_RSTTIME_RSTTIME2_MASK (0x1f << 8) +#define GLOBAL_REG_PRM_RSTTIME_RSTTIME2_CREATE(x) (((x) & 0x1f) << 8) +#define GLOBAL_REG_PRM_RSTTIME_RSTTIME2_GET(r) (((r) >> 8) & 0x1f) +#define GLOBAL_REG_PRM_RSTTIME_RSTTIME1_MASK (0xff << 0) +#define GLOBAL_REG_PRM_RSTTIME_RSTTIME1_CREATE(x) (((x) & 0xff) << 0) +#define GLOBAL_REG_PRM_RSTTIME_RSTTIME1_GET(r) (((r) >> 0) & 0xff) + + ioport32_t rstst; +#define GLOBAL_REG_PRM_RSTST_ICECRUSHER_RST_FLAG (1 << 10) +#define GLOBAL_REG_PRM_RSTST_ICEPICK_RST_FLAG (1 << 9) +#define GLOBAL_REG_PRM_RSTST_VDD2_VOLTAGE_MGR_RST_FLAG (1 << 8) +#define GLOBAL_REG_PRM_RSTST_VDD1_VOLTAGE_MGR_RST_FLAG (1 << 7) +#define GLOBAL_REG_PRM_RSTST_EXTERNAL_WARM_REST_FLAG (1 << 6) +#define GLOBAL_REG_PRM_RSTST_MPU_WD_RST_FLAG (1 << 4) +#define GLOBAL_REG_PRM_RSTST_GLOBAL_SW_RST_FLAG (1 << 1) +#define GLOBAL_REG_PRM_RSTST_GLOABL_COLD_RST_FLAG (1 << 0) + + PADD32; + ioport32_t volctrl; +#define GLOBAL_REG_PRM_VOLCTRL_SEL_VMODE_FLAG (1 << 4) +#define GLOBAL_REG_PRM_VOLCTRL_SEL_OFF_FLAG (1 << 3) +#define GLOBAL_REG_PRM_VOLCTRL_AUTO_OFF_FLAG (1 << 2) +#define GLOBAL_REG_PRM_VOLCTRL_AUTO_RET_FLAG (1 << 1) +#define GLOBAL_REG_PRM_VOLCTRL_AUTO_SLEEP_FLAG (1 << 0) + + ioport32_t sram_pcharge; +#define GLOBAL_REG_PRM_SRAM_PCHARGE_PCHARGE_TIME_MASK (0xff) +#define GLOBAL_REG_PRM_SRAM_PCHARGE_PCHARGE_TIME_CREATE(x) ((x) & 0xff) +#define GLOBAL_REG_PRM_SRAM_PCHARGE_PCHARGE_TIME_GET(r) ((r) & 0xff) + + PADD32[2]; + ioport32_t clksrc_ctrl; +#define GLOBAL_REG_PRM_CLKSRC_CTRL_DPLL4_CLKINP_DIV_65_FLAG (1 << 8) +#define GLOBAL_REG_PRM_CLKSRC_CTRL_SYSCLKDIV_MASK (0x3 << 6) +#define GLOBAL_REG_PRM_CLKSRC_CTRL_SYSCLKDIV_1 (0x1 << 6) +#define GLOBAL_REG_PRM_CLKSRC_CTRL_SYSCLKDIV_2 (0x2 << 6) +#define GLOBAL_REG_PRM_CLKSRC_CTRL_SYSCLKDIV_GET(r) (((r) >> 6) & 0x3) +#define GLOBAL_REG_PRM_CLKSRC_CTRL_AUTOEXTCLKMODE_MASK (0x3 << 3) +#define GLOBAL_REG_PRM_CLKSRC_CTRL_AUTOEXTCLKMODE_ON (0x0 << 3) +#define GLOBAL_REG_PRM_CLKSRC_CTRL_AUTOEXTCLKMODE_SLEEP (0x1 << 3) +#define GLOBAL_REG_PRM_CLKSRC_CTRL_AUTOEXTCLKMODE_RET (0x2 << 3) +#define GLOBAL_REG_PRM_CLKSRC_CTRL_AUTOEXTCLKMODE_OFF (0x3 << 3) +#define GLOBAL_REG_PRM_CLKSRC_CTRL_AUTOEXTCLKMODE_GET(r) (((r) >> 3) & 0x3) +#define GLOBAL_REG_PRM_CLKSRC_CTRL_SYSCLKSEL_MASK (0x3 << 0) +#define GLOBAL_REG_PRM_CLKSRC_CTRL_SYSCLKSEL_BYPASS (0x0 << 0) +#define GLOBAL_REG_PRM_CLKSRC_CTRL_SYSCLKSEL_OSCILLATOR (0x1 << 0) +#define GLOBAL_REG_PRM_CLKSRC_CTRL_SYSCLKSEL_UNKNOWN (0x3 << 0) +#define GLOBAL_REG_PRM_CLKSRC_CTRL_SYSCLKSEL_GET(r) (((r) >> 0) & 0x3) + + PADD32[3]; + const ioport32_t obs; +#define GLOBAL_REG_PRM_OBS_OBS_BUS_MASK (0x3ff) + + PADD32[3]; + ioport32_t voltsetup1; +#define GLOBAL_REG_PRM_VOLTSETUP1_SETUPTIME2_MASK (0xff << 16) +#define GLOBAL_REG_PRM_VOLTSETUP1_SETUPTIME2_CREATE(x) (((x) & 0xff) << 16) +#define GLOBAL_REG_PRM_VOLTSETUP1_SETUPTIME2_GET(r) (((r) >> 16) & 0xff) +#define GLOBAL_REG_PRM_VOLTSETUP1_SETUPTIME1_MASK (0xff << 0) +#define GLOBAL_REG_PRM_VOLTSETUP1_SETUPTIME1_CREATE(x) (((x) & 0xff) << 0) +#define GLOBAL_REG_PRM_VOLTSETUP1_SETUPTIME1_GET(r) (((r) >> 0) & 0xff) + + ioport32_t voltoffset; +#define GLOBAL_REG_PRM_VOLTOFFSET_OFFSET_TIME_MASK (0xffff << 0) +#define GLOBAL_REG_PRM_VOLTOFFSET_OFFSET_TIME_CREATE(x) (((x) & 0xffff) << 0) +#define GLOBAL_REG_PRM_VOLTOFFSET_OFFSET_TIME_GET(r) (((r) >> 0) & 0xffff) + + ioport32_t clksetup; +#define GLOBAL_REG_PRM_CLKSETUP_SETUP_TIME_MASK (0xffff << 0) +#define GLOBAL_REG_PRM_CLKSETUP_SETUP_TIME_CREATE(x) (((x) & 0xffff) << 0) +#define GLOBAL_REG_PRM_CLKSETUP_SETUP_TIME_GET(r) (((r) >> 0) & 0xffff) + + ioport32_t polctrl; +#define GLOBAL_REG_PRM_POLCTRL_OFFMODE_POL_FLAG (1 << 3) +#define GLOBAL_REG_PRM_POLCTRL_CLKOUT_POL_FLAG (1 << 2) +#define GLOBAL_REG_PRM_POLCTRL_CLKREG_POL_FLAG (1 << 1) +#define GLOBAL_REG_PRM_POLCTRL_EXTVOL_POL_FLAG (1 << 0) + + ioport32_t voltsetup2; +#define GLOBAL_REG_PRM_VOLTSETUP2_OFFMODESETUPTIME_MASK (0xffff << 0) +#define GLOBAL_REG_PRM_VOLTSETUP2_OFFMODESETUPTIME_CREATE(x) (((x) & 0xffff) << 0) +#define GLOBAL_REG_PRM_VOLTSETUP2_OFFMODESETUPTIME_GET(r) (((r) >> 0) & 0xffff) + + PADD32[3]; + struct { + ioport32_t config; +#define GLOBAL_REG_PRM_VP_CONFIG_ERROROFFSET_MASK (0xff << 24) +#define GLOBAL_REG_PRM_VP_CONFIG_ERROROFFSET_CREATE(x) (((x) & 0xff) << 24) +#define GLOBAL_REG_PRM_VP_CONFIG_ERROROFFSET_GET(r) (((r) >> 0xff << 24) +#define GLOBAL_REG_PRM_VP_CONFIG_ERRORGAIN_MASK (0xff << 16) +#define GLOBAL_REG_PRM_VP_CONFIG_ERRORGAIN_CREATE(x) (((x) & 0xff) << 16) +#define GLOBAL_REG_PRM_VP_CONFIG_ERRORGAIN_GET(r) (((r) >> 0xff << 16) +#define GLOBAL_REG_PRM_VP_CONFIG_INITVOLTAGE_MASK (0xff << 8) +#define GLOBAL_REG_PRM_VP_CONFIG_INITVOLTAGE_CREATE(x) (((x) & 0xff) << 8) +#define GLOBAL_REG_PRM_VP_CONFIG_INITVOLTAGE_GET(r) (((r) >> 0xff << 8) +#define GLOBAL_REG_PRM_VP_CONFIG_TIMEOUTEN_FLAG (1 << 3) +#define GLOBAL_REG_PRM_VP_CONFIG_INITVDD_FLAG (1 << 2) +#define GLOBAL_REG_PRM_VP_CONFIG_FORCEUPDATE_FLAG (1 << 1) +#define GLOBAL_REG_PRM_VP_CONFIG_VPENABLE_FLAG (1 << 0) + + ioport32_t vstepmin; +#define GLOBAL_REG_PRM_VP_VSTEPMIN_SMPSWAITTIMEMIN_MASK (0xffff << 8) +#define GLOBAL_REG_PRM_VP_VSTEPMIN_SMPSWAITTIMEMIN_CREATE(x) (((x)0xffff << 8) +#define GLOBAL_REG_PRM_VP_VSTEPMIN_SMPSWAITTIMEMIN_GET(r) (((r) >> 8) & 0xffff) +#define GLOBAL_REG_PRM_VP_VSTEPMIN_VSTEPMIN_MASK (0xff << 0) +#define GLOBAL_REG_PRM_VP_VSTEPMIN_VSTEPMIN_CREATE(x) (((x)0xff << 0) +#define GLOBAL_REG_PRM_VP_VSTEPMIN_VSTEPMIN_GET(r) (((r) >> 0) & 0xff) + + ioport32_t vstepmax; +#define GLOBAL_REG_PRM_VP_VSTEPMAX_SMPSWAITTIMEMIN_MASK (0xffff << 8) +#define GLOBAL_REG_PRM_VP_VSTEPMAX_SMPSWAITTIMEMIN_CREATE(x) (((x)0xffff << 8) +#define GLOBAL_REG_PRM_VP_VSTEPMAX_SMPSWAITTIMEMIN_GET(r) (((r) >> 8) & 0xffff) +#define GLOBAL_REG_PRM_VP_VSTEPMAX_VSTEPMIN_MASK (0xff << 0) +#define GLOBAL_REG_PRM_VP_VSTEPMAX_VSTEPMIN_CREATE(x) (((x)0xff << 0) +#define GLOBAL_REG_PRM_VP_VSTEPMAX_VSTEPMIN_GET(r) (((r) >> 0) & 0xff) + + ioport32_t vlimitto; +#define GLOBAL_REG_PRM_VP_VLIMITTO_VDDMAX_MASK (0xff << 24) +#define GLOBAL_REG_PRM_VP_VLIMITTO_VDDMAX_CREATE(x) (((x)0xff << 24) +#define GLOBAL_REG_PRM_VP_VLIMITTO_VDDMAX_GET(r) (((r) >> 24) & 0xff) +#define GLOBAL_REG_PRM_VP_VLIMITTO_VDDMIN_MASK (0xff << 16) +#define GLOBAL_REG_PRM_VP_VLIMITTO_VDDMIN_CREATE(x) (((x)0xff << 16) +#define GLOBAL_REG_PRM_VP_VLIMITTO_VDDMIN_GET(r) (((r) >> 16) & 0xff) +#define GLOBAL_REG_PRM_VP_VLIMITTO_TIMEOUT_MASK (0xffff << 0) +#define GLOBAL_REG_PRM_VP_VLIMITTO_TIMEOUT_CREATE(x) (((x)0xffff << 0) +#define GLOBAL_REG_PRM_VP_VLIMITTO_TIMEOUT_GET(r) (((r) >> 0) & 0xffff) + + const ioport32_t voltage; +#define GLOBAL_REG_PRM_VP_VOLTAGE_VPVOLTAGE_MASK (0xff) +#define GLOBAL_REG_PRM_VP_VOLTAGE_VPVOLTAGE_GET(r) ((r) & 0xff) + + const ioport32_t status; +#define GLOBAL_REG_PRM_VP_STATUS_VPINIDLE_FLAG (1 << 0) + + PADD32[2]; + } vp[2]; + + ioport32_t ldo_abb_setup; +#define GLOBAL_REG_PRM_LDO_ABB_SETUP_SR2_IN_TRANSITION (1 << 6) +#define GLOBAL_REG_PRM_LDO_ABB_SETUP_SR2_STATUS_MASK (0x3 << 3) +#define GLOBAL_REG_PRM_LDO_ABB_SETUP_SR2_STATUS_BYPASS (0x0 << 3) +#define GLOBAL_REG_PRM_LDO_ABB_SETUP_SR2_STATUS_FBB (0x2 << 3) +#define GLOBAL_REG_PRM_LDO_ABB_SETUP_SR2_OPP_CHANGE_FLAG (1 << 2) +#define GLOBAL_REG_PRM_LDO_ABB_SETUP_OPP_SEL_MASK (0x3 << 0) +#define GLOBAL_REG_PRM_LDO_ABB_SETUP_OPP_SEL_DEFAULT (0x0 << 0) +#define GLOBAL_REG_PRM_LDO_ABB_SETUP_OPP_SEL_FAST (0x1 << 0) +#define GLOBAL_REG_PRM_LDO_ABB_SETUP_OPP_SEL_NOMINAL (0x2 << 0) +#define GLOBAL_REG_PRM_LDO_ABB_SETUP_OPP_SEL_SLOW (0x3 << 0) + + ioport32_t ldo_abb_ctrl; +#define GLOBAL_REG_PRM_LDO_ABB_CTRL_SR2_WTCNT_VALUE_MASK (0xff << 8) +#define GLOBAL_REG_PRM_LDO_ABB_CTRL_SR2_WTCNT_VALUE_CREATE(x) (((x) & 0xff) << 8) +#define GLOBAL_REG_PRM_LDO_ABB_CTRL_SR2_WTCNT_VALUE_GET(r) (((r) >> 8) & 0xff) +#define GLOBAL_REG_PRM_LDO_ABB_CTRL_ACTIVE_FBB_SEL_FLAG (1 << 2) +#define GLOBAL_REG_PRM_LDO_ABB_CTRL_SR2EN (1 << 0) +} global_reg_prm_regs_t; + +#endif +/** + * @} + */ Index: uspace/drv/platform/amdm37x/prm/usbhost.h =================================================================== --- uspace/drv/platform/amdm37x/prm/usbhost.h (revision 2a37b9f1eb93bba78ec231d42ef29f30dff550a0) +++ uspace/drv/platform/amdm37x/prm/usbhost.h (revision 2a37b9f1eb93bba78ec231d42ef29f30dff550a0) @@ -0,0 +1,111 @@ +/* + * Copyright (c) 2012 Jan Vesely + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup amdm37xdrvprm + * @{ + */ +/** @file + * @brief Clock Control Clock Management IO register structure. + */ +#ifndef AMDM37X_PRM_CLOCK_CONTROL_H +#define AMDM37X_PRM_CLOCK_CONTROL_H +#include +#include + +/* AM/DM37x TRM p.536 and p.589 */ +#define CLOCK_CONTROL_CM_BASE_ADDRESS 0x48307400 +#define CLOCK_CONTROL_CM_SIZE 8192 + +/** Clock control PRM register map + * + * Periph DPLL == DPLL4 + * Core DPLL == DPLL3 + */ +typedef struct { + PADD32[22]; + ioport32_t rm_rstst; +#define USBHOST_PRM_RM_RSTST_COREDOMAINWKUP_RST_FLAG (1 << 3) +#define USBHOST_PRM_RM_RSTST_DOMAINWKUP_RST_FLAG (1 << 2) +#define USBHOST_PRM_RM_RSTST_GLOBALWARM_RST_FLAG (1 << 1) +#define USBHOST_PRM_RM_RSTST_GLOBALCOLD_RST_FLAG (1 << 0) + + PADD32[18]; + ioport32_t pm_wken; +#define USBHOST_PRM_PM_WKEN_EN_USBHOST_FLAG (1 << 0) + + ioport32_t pm_mpugrpsel; +#define USBHOST_PRM_PM_MPUGRPSEL_GRPSEL_USBHOST_FLAG (1 << 0) + + ioport32_t pm_iva2grpsel; +#define USBHOST_PRM_PM_IVA2GRPSEL_GRPSEL_USBHOST_FLAG (1 << 0) + + PADD32; + ioport32_t pm_wkst; +#define USBHOST_PRM_PM_WKST_ST_USBHOST_FLAG (1 << 0) + + PADD32[5]; + ioport32_t pm_wkdep; +#define USBHOST_PRM_PM_WKDEP_EN_WKUP_FLAG (1 << 4) +#define USBHOST_PRM_PM_WKDEP_EN_IVA2_FLAG (1 << 2) +#define USBHOST_PRM_PM_WKDEP_EN_MPU_FLAG (1 << 1) +#define USBHOST_PRM_PM_WKDEP_EN_CORE_FLAG (1 << 0) + + PADD32[5]; + ioport32_t pm_pwstctrl; +#define USBHOST_PRM_PM_PWSTCTRL_MEMONSTATE_MASK (0x3 << 16) +#define USBHOST_PRM_PM_PWSTCTRL_MEMONSTATE_ALWAYS_ON (0x3 << 16) +#define USBHOST_PRM_PM_PWSTCTRL_MEMRETSTATE_FLAG (1 << 8) +#define USBHOST_PRM_PM_PWSTCTRL_SAVEANDRESTORE_FLAG (1 << 4) +#define USBHOST_PRM_PM_PWSTCTRL_LOGICRESTATE_FLAG (1 << 2) +#define USBHOST_PRM_PM_PWSTCTRL_POWERSTATE_MASK (0x3 << 0) +#define USBHOST_PRM_PM_PWSTCTRL_POWERSTATE_OFF (0x0 << 0) +#define USBHOST_PRM_PM_PWSTCTRL_POWERSTATE_RETENTION (0x1 << 0) +#define USBHOST_PRM_PM_PWSTCTRL_POWERSTATE_ON (0x3 << 0) + + const ioport32_t pm_pwstst; +#define USBHOST_PRM_PM_PWSTST_INTRANSITION_FLAG (1 << 20) +#define USBHOST_PRM_PM_PWSTST_POWERSTATEST_MASK (0x3 << 0) +#define USBHOST_PRM_PM_PWSTST_POWERSTATEST_OFF (0x0 << 0) +#define USBHOST_PRM_PM_PWSTST_POWERSTATEST_RETENTION (0x1 << 0) +#define USBHOST_PRM_PM_PWSTST_POWERSTATEST_INACTIVE (0x2 << 0) +#define USBHOST_PRM_PM_PWSTST_POWERSTATEST_ON (0x3 << 0) + + ioport32_t pm_prepwstst; +#define USBHOST_PRM_PM_PREPWSTST_LASTPOWERSTATEENTERED_MASK (0x3 << 0) +#define USBHOST_PRM_PM_PREPWSTST_LASTPOWERSTATEENTERED_OFF (0x0 << 0) +#define USBHOST_PRM_PM_PREPWSTST_LASTPOWERSTATEENTERED_RETENTION (0x1 << 0) +#define USBHOST_PRM_PM_PREPWSTST_LASTPOWERSTATEENTERED_INACTIVE (0x2 << 0) +#define USBHOST_PRM_PM_PREPWSTST_LASTPOWERSTATEENTERED_ON (0x3 << 0) + +} usbhost_prm_regs_t; + +#endif +/** + * @} + */ + Index: uspace/drv/platform/amdm37x/uhh.h =================================================================== --- uspace/drv/platform/amdm37x/uhh.h (revision 2a37b9f1eb93bba78ec231d42ef29f30dff550a0) +++ uspace/drv/platform/amdm37x/uhh.h (revision 2a37b9f1eb93bba78ec231d42ef29f30dff550a0) @@ -0,0 +1,97 @@ +/* + * Copyright (c) 2012 Jan Vesely + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup amdm37xdrvuhh + * @{ + */ +/** @file + * @brief UHH IO register structure. + */ +#ifndef AMDM37x_UHH_H +#define AMDM37x_UHH_H +#include +#include + +#define AMDM37x_UHH_BASE_ADDRESS 0x48064000 +#define AMDM37x_UHH_SIZE 1024 + +typedef struct { + const ioport32_t revision; +#define UHH_REVISION_MINOR_MASK 0x0f +#define UHH_REVISION_MAJOR_MASK 0xf0 + + PADD32[3]; + ioport32_t sysconfig; +#define UHH_SYSCONFIG_AUTOIDLE_FLAG (1 << 0) +#define UHH_SYSCONFIG_SOFTRESET_FLAG (1 << 1) +#define UHH_SYSCONFIG_ENWAKEUP_FLAG (1 << 2) +#define UHH_SYSCONFIG_SIDLE_MODE_MASK (0x3 << 3) +#define UHH_SYSCONFIG_SIDLE_MODE_FORCE (0x0 << 3) +#define UHH_SYSCONFIG_SIDLE_MODE_NO (0x1 << 3) +#define UHH_SYSCONFIG_SIDLE_MODE_SMART (0x2 << 3) +#define UHH_SYSCONFIG_CLOCKACTIVITY_FLAG (1 << 8) +#define UHH_SYSCONFIG_MIDLE_MODE_MASK (0x3 << 12) +#define UHH_SYSCONFIG_MIDLE_MODE_FORCE (0x0 << 12) +#define UHH_SYSCONFIG_MIDLE_MODE_NO (0x1 << 12) +#define UHH_SYSCONFIG_MIDLE_MODE_SMART (0x2 << 12) + + const ioport32_t sysstatus; +#define UHH_SYSSTATUS_RESETDONE_FLAG (1 << 0) +#define UHH_SYSSTATUS_OHCI_RESETDONE_FLAG (1 << 1) +#define UHH_SYSSTATUS_EHCI_RESETDONE_FLAG (1 << 2) + + PADD32[10]; + ioport32_t hostconfig; +#define UHH_HOSTCONFIG_P1_ULPI_BYPASS_FLAG (1 << 0) +#define UHH_HOSTCONFIG_AUTOPPD_ON_OVERCUR_EN_FLAG (1 << 1) +#define UHH_HOSTCONFIG_ENA_INCR4_FLAG (1 << 2) +#define UHH_HOSTCONFIG_ENA_INCR8_FLAG (1 << 3) +#define UHH_HOSTCONFIG_ENA_INCR16_FLA (1 << 4) +#define UHH_HOSTCONFIG_ENA_INCR_ALIGN_FLAG (1 << 5) +#define UHH_HOSTCONFIG_P1_CONNECT_STATUS_FLAG (1 << 8) +#define UHH_HOSTCONFIG_P2_CONNECT_STATUS_FLAG (1 << 9) +#define UHH_HOSTCONFIG_P3_CONNECT_STATUS_FLAG (1 << 10) +#define UHH_HOSTCONFIG_P2_ULPI_BYPASS_FLAG (1 << 11) +#define UHH_HOSTCONFIG_P3_ULPI_BYPASS_FLAG (1 << 12) + + ioport32_t debug_csr; +#define UHH_DEBUG_CSR_EHCI_FLADJ_MASK (0x3f << 0) +#define UHH_DEBUG_CSR_EHCI_FLADJ(x) ((x) & 0x3f) +#define UHH_DEBUG_CSR_EHCI_SIMULATION_MODE_FLAG (1 << 6) +#define UHH_DEBUG_CSR_OHCI_CNTSEL_FLAG (1 << 7) +#define UHH_DEBUG_CSR_OHCI_GLOBAL_SUSPEND_FLAG (1 << 16) +#define UHH_DEBUG_CSR_OHCI_CCS1_FLAG (1 << 17) +#define UHH_DEBUG_CSR_OHCI_CCS2_FLAG (1 << 18) +#define UHH_DEBUG_CSR_OHCI_CCS3_FLAG (1 << 19) + +} uhh_regs_t; + +#endif +/** + * @} + */ Index: uspace/drv/platform/amdm37x/usbtll.h =================================================================== --- uspace/drv/platform/amdm37x/usbtll.h (revision 2a37b9f1eb93bba78ec231d42ef29f30dff550a0) +++ uspace/drv/platform/amdm37x/usbtll.h (revision 2a37b9f1eb93bba78ec231d42ef29f30dff550a0) @@ -0,0 +1,129 @@ +/* + * Copyright (c) 2012 Jan Vesely + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup amdm37xdrvusbtll + * @{ + */ +/** @file + * @brief USBTLL IO register structure. + */ +#ifndef AMDM37x_USBTLL_H +#define AMDM37x_USBTLL_H +#include +#include + +#define AMDM37x_USBTLL_BASE_ADDRESS 0x48062000 +#define AMDM37x_USBTLL_SIZE 4096 + +typedef struct { + const ioport32_t revision; +#define TLL_REVISION_MINOR_MASK 0x0f +#define TLL_REVISION_MAJOR_MASK 0xf0 + + PADD32[3]; + ioport32_t sysconfig; +#define TLL_SYSCONFIG_AUTOIDLE_FLAG (1 << 0) +#define TLL_SYSCONFIG_SOFTRESET_FLAG (1 << 1) +#define TLL_SYSCONFIG_ENWAKEUP_FLAG (1 << 2) +#define TLL_SYSCONFIG_SIDLE_MODE_MASK (0x3 << 3) +#define TLL_SYSCONFIG_SIDLE_MODE_FORCE (0x0 << 3) +#define TLL_SYSCONFIG_SIDLE_MODE_NO (0x1 << 3) +#define TLL_SYSCONFIG_SIDLE_MODE_SMART (0x2 << 3) +#define TLL_SYSCONFIG_CLOCKACTIVITY_FLAG (1 << 8) + + const ioport32_t sysstatus; +#define TLL_SYSSTATUS_RESET_DONE_FLAG (1 << 0) + + const ioport32_t irqstatus; +#define TLL_IRQSTATUS_FCLK_START_FLAG (1 << 0) +#define TLL_IRQSTATUS_FCLK_END_FLAG (1 << 1) +#define TLL_IRQSTATUS_ACCESS_ERROR_FLAG (1 << 2) + + ioport32_t irqenable; +#define TLL_IRQSTATUS_FCLK_START_EN_FLAG (1 << 0) +#define TLL_IRQSTATUS_FCLK_END_EN_FLAG (1 << 1) +#define TLL_IRQSTATUS_ACCESS_ERROR_EN_FLAG (1 << 2) + + PADD32[4]; + ioport32_t shared_conf; +#define TLL_SHARED_CONF_FCLK_IS_ON_FLAG (1 << 0) +#define TLL_SHARED_CONF_FCLK_REQ_FLAG (1 << 1) +#define TLL_SHARED_CONF_USB_DIVRATIO_MASK (0x7 << 2) +#define TLL_SHARED_CONF_USB_DIVRATIO(x) (((x) & 0x7) << 2) +#define TLL_SHARED_CONF_USB_180D_SDR_EN_FLAG (1 << 5) +#define TLL_SHARED_CONF_USB_90D_DDR_EN_FLAG (1 << 6) + + PADD32[3]; + ioport32_t channel_conf[3]; +#define TLL_CHANNEL_CONF_CHANEN_FLAG (1 << 0) +#define TLL_CHANNEL_CONF_CHANMODE_MASK (0x3 << 1) +#define TLL_CHANNEL_CONF_CHANMODE_UTMI_ULPI_MODE (0x0 << 1) +#define TLL_CHANNEL_CONF_CHANMODE_UTMI_SERIAL_MODE (0x1 << 1) +#define TLL_CHANNEL_CONF_CHANMODE_UTMI_TRANS_MODE (0x2 << 1) +#define TLL_CHANNEL_CONF_CHANMODE_NO_MODE (0x3 << 1) +#define TLL_CHANNEL_CONF_UTMIISADEV_FLAG (1 << 3) +#define TLL_CHANNEL_CONF_TLLATTACH_FLAG (1 << 4) +#define TLL_CHANNEL_CONF_TLLCONNECT_FLAG (1 << 5) +#define TLL_CHANNEL_CONF_TLLFULLSPEED_FLAG (1 << 6) +#define TLL_CHANNEL_CONF_ULPIOUTCLKMODE_FLAG (1 << 7) +#define TLL_CHANNEL_CONF_ULPIDDRMODE_FLAG (1 << 8) +#define TLL_CHANNEL_CONF_UTMIAUTOIDLE_FLAG (1 << 9) +#define TLL_CHANNEL_CONF_ULPIAUTOIDLE_FLAG (1 << 10) +#define TLL_CHANNEL_CONF_ULPINOBITSTUFF_FLAG (1 << 11) +#define TLL_CHANNEL_CONF_CHRGVBUS_FLAG (1 << 15) +#define TLL_CHANNEL_CONF_DRVVBUS_FLAG (1 << 16) +#define TLL_CHANNEL_CONF_TESTEN_FLAG (1 << 17) +#define TLL_CHANNEL_CONF_TESTTXEN_FLAG (1 << 18) +#define TLL_CHANNEL_CONF_TESTTXDAT_FLAG (1 << 19) +#define TLL_CHANNEL_CONF_TESTTXSE0_FLAG (1 << 20) +#define TLL_CHANNEL_CONF_FSLSMODE_MASK (0xf << 24) +#define TLL_CHANNEL_CONF_FSLSMODE_6PIN_UNI_PHY_TX_DATSE0 (0x0 << 24) +#define TLL_CHANNEL_CONF_FSLSMODE_6PIN_UNI_PHY_TX_DPDM (0x1 << 24) +#define TLL_CHANNEL_CONF_FSLSMODE_3PIN_BIDI_PHY (0x2 << 24) +#define TLL_CHANNEL_CONF_FSLSMODE_4PIN_BIDI_PHY (0x3 << 24) +#define TLL_CHANNEL_CONF_FSLSMODE_6PIN_UNI_TLL_TX_DATSE0 (0x4 << 24) +#define TLL_CHANNEL_CONF_FSLSMODE_6PIN_UNI_TLL_TX_DPDM (0x5 << 24) +#define TLL_CHANNEL_CONF_FSLSMODE_3PIN_BIDI_TLL (0x6 << 24) +#define TLL_CHANNEL_CONF_FSLSMODE_4PIN_BIDI_TLL (0x7 << 24) +#define TLL_CHANNEL_CONF_FSLSMODE_2PIN_BIDI_TLL_DATSE0 (0xa << 24) +#define TLL_CHANNEL_CONF_FSLSMODE_2PIN_BIDI_TLL_DPDM (0xb << 24) + +#define TLL_CHANNEL_CONF_FSLSLINESTATE_MASK (0x3 << 28) +#define TLL_CHANNEL_CONF_FSLSLINESTATE_SE0 (0x0 << 28) +#define TLL_CHANNEL_CONF_FSLSLINESTATE_FS_J (0x1 << 28) +#define TLL_CHANNEL_CONF_FSLSLINESTATE_FS_K (0x2 << 28) +#define TLL_CHANNEL_CONF_FSLSLINESTATE_SE1 (0x3 << 28) + + /* The rest are 8bit ULPI registers */ +} tll_regs_t; + +#endif +/** + * @} + */ + Index: uspace/drv/platform/leon3/Makefile =================================================================== --- uspace/drv/platform/leon3/Makefile (revision 2a37b9f1eb93bba78ec231d42ef29f30dff550a0) +++ uspace/drv/platform/leon3/Makefile (revision 2a37b9f1eb93bba78ec231d42ef29f30dff550a0) @@ -0,0 +1,37 @@ +# +# Copyright (c) 2012 Jan Vesely +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# - Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# - Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# - The name of the author may not be used to endorse or promote products +# derived from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR +# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# + +USPACE_PREFIX = ../../.. +LIBS = $(LIBDRV_PREFIX)/libdrv.a +EXTRA_CFLAGS += -I$(LIBDRV_PREFIX)/include +BINARY = leon3 + +SOURCES = \ + leon3.c + +include $(USPACE_PREFIX)/Makefile.common Index: uspace/drv/platform/leon3/leon3.c =================================================================== --- uspace/drv/platform/leon3/leon3.c (revision 2a37b9f1eb93bba78ec231d42ef29f30dff550a0) +++ uspace/drv/platform/leon3/leon3.c (revision 2a37b9f1eb93bba78ec231d42ef29f30dff550a0) @@ -0,0 +1,195 @@ +/* + * Copyright (c) 2012 Jan Vesely + * Copyright (c) 2013 Jakub Klama + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** + * @defgroup root_leon3 SPARC LEON3 platform driver. + * @brief HelenOS SPARC LEON3 platform driver. + * @{ + */ +/** @file + */ + +#include +#include +#include +#include +#include "leon3.h" + +#define NAME "leon3" + +typedef struct { + const char *name; + match_id_t match_id; + hw_resource_list_t hw_resources; +} leon3_fun_t; + +static hw_resource_t amba_res[] = { + { + .type = MEM_RANGE, + .res.mem_range = { + .address = AMBAPP_MASTER_AREA, + .size = AMBAPP_MASTER_SIZE, + .endianness = BIG_ENDIAN + } + }, + { + .type = MEM_RANGE, + .res.mem_range = { + .address = AMBAPP_SLAVE_AREA, + .size = AMBAPP_SLAVE_SIZE, + .endianness = BIG_ENDIAN, + } + } +}; + +static const leon3_fun_t leon3_func = { + .name = "leon_amba", + .match_id = { + .id = "leon_amba", + .score = 90 + }, + .hw_resources = { + .count = 2, + .resources = amba_res + } +}; + +static hw_resource_list_t *leon3_get_resources(ddf_fun_t *); +static bool leon3_enable_interrupt(ddf_fun_t *); + +static hw_res_ops_t fun_hw_res_ops = { + .get_resource_list = &leon3_get_resources, + .enable_interrupt = &leon3_enable_interrupt +}; + +static ddf_dev_ops_t leon3_fun_ops = { + .interfaces[HW_RES_DEV_IFACE] = &fun_hw_res_ops +}; + +static int leon3_add_fun(ddf_dev_t *dev, const leon3_fun_t *fun) +{ + assert(dev); + assert(fun); + + ddf_msg(LVL_DEBUG, "Adding new function '%s'.", fun->name); + + /* Create new device function. */ + ddf_fun_t *fnode = ddf_fun_create(dev, fun_inner, fun->name); + if (fnode == NULL) + return ENOMEM; + + /* Add match id */ + int ret = ddf_fun_add_match_id(fnode, fun->match_id.id, + fun->match_id.score); + if (ret != EOK) { + ddf_fun_destroy(fnode); + return ret; + } + + /* Allocate needed data */ + leon3_fun_t *rf = + ddf_fun_data_alloc(fnode, sizeof(leon3_fun_t)); + if (!rf) { + ddf_fun_destroy(fnode); + return ENOMEM; + } + *rf = *fun; + + /* Set provided operations to the device. */ + ddf_fun_set_ops(fnode, &leon3_fun_ops); + + /* Register function. */ + ret = ddf_fun_bind(fnode); + if (ret != EOK) { + ddf_msg(LVL_ERROR, "Failed binding function %s.", fun->name); + ddf_fun_destroy(fnode); + return ret; + } + + return EOK; +} + +/** Add the root device. + * + * @param dev Device which is root of the whole device tree + * (both of HW and pseudo devices). + * + * @return Zero on success, negative error number otherwise. + * + */ +static int leon3_dev_add(ddf_dev_t *dev) +{ + assert(dev); + + /* Register functions */ + if (leon3_add_fun(dev, &leon3_func) != EOK) { + ddf_msg(LVL_ERROR, "Failed to add %s function for " + "LEON3 platform.", leon3_func.name); + } + + return EOK; +} + +/** The root device driver's standard operations. */ +static driver_ops_t leon3_ops = { + .dev_add = &leon3_dev_add +}; + +/** The root device driver structure. */ +static driver_t leon3_driver = { + .name = NAME, + .driver_ops = &leon3_ops +}; + +static hw_resource_list_t *leon3_get_resources(ddf_fun_t *fnode) +{ + leon3_fun_t *fun = ddf_fun_data_get(fnode); + assert(fun != NULL); + + printf("leon3_get_resources() called\n"); + + return &fun->hw_resources; +} + +static bool leon3_enable_interrupt(ddf_fun_t *fun) +{ + // FIXME TODO + return false; +} + +int main(int argc, char *argv[]) +{ + printf("%s: HelenOS SPARC LEON3 platform driver\n", NAME); + ddf_log_init(NAME); + return ddf_driver_main(&leon3_driver); +} + +/** + * @} + */ Index: uspace/drv/platform/leon3/leon3.h =================================================================== --- uspace/drv/platform/leon3/leon3.h (revision 2a37b9f1eb93bba78ec231d42ef29f30dff550a0) +++ uspace/drv/platform/leon3/leon3.h (revision 2a37b9f1eb93bba78ec231d42ef29f30dff550a0) @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2013 Jakub Klama + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup leon3drv + * @{ + */ +/** @file + * @brief LEON3 root device. + */ + +#ifndef LEON3_H +#define LEON3_H + +#define AMBAPP_MASTER_AREA 0xfffff000 +#define AMBAPP_SLAVE_AREA 0xfffff800 +#define AMBAPP_MASTER_SIZE 0x800 +#define AMBAPP_SLAVE_SIZE 0x800 + +#endif + +/** + * @} + */ Index: uspace/drv/platform/leon3/leon3.ma =================================================================== --- uspace/drv/platform/leon3/leon3.ma (revision 2a37b9f1eb93bba78ec231d42ef29f30dff550a0) +++ uspace/drv/platform/leon3/leon3.ma (revision 2a37b9f1eb93bba78ec231d42ef29f30dff550a0) @@ -0,0 +1,1 @@ +100 platform/leon3 Index: uspace/drv/platform/mac/Makefile =================================================================== --- uspace/drv/platform/mac/Makefile (revision 2a37b9f1eb93bba78ec231d42ef29f30dff550a0) +++ uspace/drv/platform/mac/Makefile (revision 2a37b9f1eb93bba78ec231d42ef29f30dff550a0) @@ -0,0 +1,37 @@ +# +# Copyright (c) 2010 Lenka Trochtova +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# - Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# - Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# - The name of the author may not be used to endorse or promote products +# derived from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR +# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# + +USPACE_PREFIX = ../../.. +LIBS = $(LIBDRV_PREFIX)/libdrv.a +EXTRA_CFLAGS += -I$(LIBDRV_PREFIX)/include +BINARY = mac + +SOURCES = \ + mac.c + +include $(USPACE_PREFIX)/Makefile.common Index: uspace/drv/platform/mac/mac.c =================================================================== --- uspace/drv/platform/mac/mac.c (revision 2a37b9f1eb93bba78ec231d42ef29f30dff550a0) +++ uspace/drv/platform/mac/mac.c (revision 2a37b9f1eb93bba78ec231d42ef29f30dff550a0) @@ -0,0 +1,190 @@ +/* + * Copyright (c) 2011 Martin Decky + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** + * @defgroup root_mac Mac platform driver. + * @brief HelenOS Mac platform driver. + * @{ + */ + +/** @file + */ + +#include +#include +#include +#include +#include + +#define NAME "mac" + +typedef struct { + hw_resource_list_t hw_resources; +} mac_fun_t; + +static hw_resource_t pci_conf_regs[] = { + { + .type = IO_RANGE, + .res.io_range = { + .address = 0xfec00000, + .size = 4, + .relative = false, + .endianness = LITTLE_ENDIAN + } + }, + { + .type = IO_RANGE, + .res.io_range = { + .address = 0xfee00000, + .size = 4, + .relative = false, + .endianness = LITTLE_ENDIAN + } + } +}; + +static mac_fun_t pci_data = { + .hw_resources = { + 2, + pci_conf_regs + } +}; + +static ddf_dev_ops_t mac_fun_ops; + +/** Obtain function soft-state from DDF function node */ +static mac_fun_t *mac_fun(ddf_fun_t *fnode) +{ + return ddf_fun_data_get(fnode); +} + +static bool mac_add_fun(ddf_dev_t *dev, const char *name, + const char *str_match_id, mac_fun_t *fun_proto) +{ + ddf_msg(LVL_DEBUG, "Adding new function '%s'.", name); + + ddf_fun_t *fnode = NULL; + int rc; + + /* Create new device. */ + fnode = ddf_fun_create(dev, fun_inner, name); + if (fnode == NULL) + goto failure; + + mac_fun_t *fun = ddf_fun_data_alloc(fnode, sizeof(mac_fun_t)); + *fun = *fun_proto; + + /* Add match ID */ + rc = ddf_fun_add_match_id(fnode, str_match_id, 100); + if (rc != EOK) + goto failure; + + /* Set provided operations to the device. */ + ddf_fun_set_ops(fnode, &mac_fun_ops); + + /* Register function. */ + if (ddf_fun_bind(fnode) != EOK) { + ddf_msg(LVL_ERROR, "Failed binding function %s.", name); + goto failure; + } + + return true; + +failure: + if (fnode != NULL) + ddf_fun_destroy(fnode); + + ddf_msg(LVL_ERROR, "Failed adding function '%s'.", name); + + return false; +} + +/** Get the root device. + * + * @param dev Device which is root of the whole device tree + * (both of HW and pseudo devices). + * + * @return Zero on success, negative error number otherwise. + * + */ +static int mac_dev_add(ddf_dev_t *dev) +{ +#if 0 + /* Register functions */ + if (!mac_add_fun(dev, "pci0", "intel_pci", &pci_data)) + ddf_msg(LVL_ERROR, "Failed to add functions for Mac platform."); +#else + (void)pci_data; + (void)mac_add_fun; +#endif + + return EOK; +} + +/** The root device driver's standard operations. */ +static driver_ops_t mac_ops = { + .dev_add = &mac_dev_add +}; + +/** The root device driver structure. */ +static driver_t mac_driver = { + .name = NAME, + .driver_ops = &mac_ops +}; + +static hw_resource_list_t *mac_get_resources(ddf_fun_t *fnode) +{ + mac_fun_t *fun = mac_fun(fnode); + assert(fun != NULL); + + return &fun->hw_resources; +} + +static bool mac_enable_interrupt(ddf_fun_t *fun) +{ + /* TODO */ + + return false; +} + +static hw_res_ops_t fun_hw_res_ops = { + .get_resource_list = &mac_get_resources, + .enable_interrupt = &mac_enable_interrupt +}; + +int main(int argc, char *argv[]) +{ + printf("%s: HelenOS Mac platform driver\n", NAME); + ddf_log_init(NAME); + mac_fun_ops.interfaces[HW_RES_DEV_IFACE] = &fun_hw_res_ops; + return ddf_driver_main(&mac_driver); +} + +/** + * @} + */ Index: uspace/drv/platform/mac/mac.ma =================================================================== --- uspace/drv/platform/mac/mac.ma (revision 2a37b9f1eb93bba78ec231d42ef29f30dff550a0) +++ uspace/drv/platform/mac/mac.ma (revision 2a37b9f1eb93bba78ec231d42ef29f30dff550a0) @@ -0,0 +1,1 @@ +10 platform/mac Index: uspace/drv/platform/malta/Makefile =================================================================== --- uspace/drv/platform/malta/Makefile (revision 2a37b9f1eb93bba78ec231d42ef29f30dff550a0) +++ uspace/drv/platform/malta/Makefile (revision 2a37b9f1eb93bba78ec231d42ef29f30dff550a0) @@ -0,0 +1,37 @@ +# +# Copyright (c) 2010 Lenka Trochtova +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# - Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# - Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# - The name of the author may not be used to endorse or promote products +# derived from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR +# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# + +USPACE_PREFIX = ../../.. +LIBS = $(LIBDRV_PREFIX)/libdrv.a +EXTRA_CFLAGS += -I$(LIBDRV_PREFIX)/include +BINARY = malta + +SOURCES = \ + malta.c + +include $(USPACE_PREFIX)/Makefile.common Index: uspace/drv/platform/malta/malta.c =================================================================== --- uspace/drv/platform/malta/malta.c (revision 2a37b9f1eb93bba78ec231d42ef29f30dff550a0) +++ uspace/drv/platform/malta/malta.c (revision 2a37b9f1eb93bba78ec231d42ef29f30dff550a0) @@ -0,0 +1,273 @@ +/* + * Copyright (c) 2010 Lenka Trochtova + * Copyright (c) 2013 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** + * @defgroup root_malta Malta board platform driver. + * @brief HelenOS Malta board platform driver. + * @{ + */ + +/** @file + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#define NAME "malta" + +#define GT_BASE UINT32_C(0x1be00000) +#define GT_SIZE (2 * 1024 * 1024) + +#define GT_PCI_CMD 0xc00 +#define GT_PCI_CONFADDR 0xcf8 +#define GT_PCI_CONFDATA 0xcfc + +#define GT_PCI_CMD_MBYTESWAP 0x1 + +#define GT_PCI_MEMBASE UINT32_C(0x10000000) +#define GT_PCI_MEMSIZE UINT32_C(0x08000000) + +#define GT_PCI_IOBASE UINT32_C(0x18000000) +#define GT_PCI_IOSIZE UINT32_C(0x00200000) + +typedef struct malta_fun { + hw_resource_list_t hw_resources; + pio_window_t pio_window; +} malta_fun_t; + +static int malta_dev_add(ddf_dev_t *dev); +static void root_malta_init(void); + +/** The root device driver's standard operations. */ +static driver_ops_t malta_ops = { + .dev_add = &malta_dev_add +}; + +/** The root device driver structure. */ +static driver_t malta_driver = { + .name = NAME, + .driver_ops = &malta_ops +}; + +static hw_resource_t pci_conf_regs[] = { + { + .type = IO_RANGE, + .res.io_range = { + .address = GT_BASE + GT_PCI_CONFADDR, + .size = 4, + .relative = false, + .endianness = LITTLE_ENDIAN + } + }, + { + .type = IO_RANGE, + .res.io_range = { + .address = GT_BASE + GT_PCI_CONFDATA, + .size = 4, + .relative = false, + .endianness = LITTLE_ENDIAN + } + } +}; + +static malta_fun_t pci_data = { + .hw_resources = { + sizeof(pci_conf_regs) / sizeof(pci_conf_regs[0]), + pci_conf_regs + }, + .pio_window = { + .mem = { + .base = GT_PCI_MEMBASE, + .size = GT_PCI_MEMSIZE + }, + .io = { + .base = GT_PCI_IOBASE, + .size = GT_PCI_IOSIZE + } + } +}; + +/** Obtain function soft-state from DDF function node */ +static malta_fun_t *malta_fun(ddf_fun_t *fnode) +{ + return ddf_fun_data_get(fnode); +} + +static hw_resource_list_t *malta_get_resources(ddf_fun_t *fnode) +{ + malta_fun_t *fun = malta_fun(fnode); + + assert(fun != NULL); + return &fun->hw_resources; +} + +static bool malta_enable_interrupt(ddf_fun_t *fun) +{ + /* TODO */ + + return false; +} + +static pio_window_t *malta_get_pio_window(ddf_fun_t *fnode) +{ + malta_fun_t *fun = malta_fun(fnode); + + assert(fun != NULL); + return &fun->pio_window; +} + +static hw_res_ops_t fun_hw_res_ops = { + .get_resource_list = &malta_get_resources, + .enable_interrupt = &malta_enable_interrupt, +}; + +static pio_window_ops_t fun_pio_window_ops = { + .get_pio_window = &malta_get_pio_window +}; + +/* Initialized in root_malta_init() function. */ +static ddf_dev_ops_t malta_fun_ops; + +static bool +malta_add_fun(ddf_dev_t *dev, const char *name, const char *str_match_id, + malta_fun_t *fun_proto) +{ + ddf_msg(LVL_DEBUG, "Adding new function '%s'.", name); + + ddf_fun_t *fnode = NULL; + int rc; + + /* Create new device. */ + fnode = ddf_fun_create(dev, fun_inner, name); + if (fnode == NULL) + goto failure; + + malta_fun_t *fun = ddf_fun_data_alloc(fnode, sizeof(malta_fun_t)); + *fun = *fun_proto; + + /* Add match ID */ + rc = ddf_fun_add_match_id(fnode, str_match_id, 100); + if (rc != EOK) + goto failure; + + /* Set provided operations to the device. */ + ddf_fun_set_ops(fnode, &malta_fun_ops); + + /* Register function. */ + if (ddf_fun_bind(fnode) != EOK) { + ddf_msg(LVL_ERROR, "Failed binding function %s.", name); + goto failure; + } + + return true; + +failure: + if (fnode != NULL) + ddf_fun_destroy(fnode); + + ddf_msg(LVL_ERROR, "Failed adding function '%s'.", name); + + return false; +} + +static bool malta_add_functions(ddf_dev_t *dev) +{ + return malta_add_fun(dev, "pci0", "intel_pci", &pci_data); +} + +/** Get the root device. + * + * @param dev The device which is root of the whole device tree (both + * of HW and pseudo devices). + * @return Zero on success, negative error number otherwise. + */ +static int malta_dev_add(ddf_dev_t *dev) +{ + ioport32_t *gt; + uint32_t val; + int ret; + + ddf_msg(LVL_DEBUG, "malta_dev_add, device handle = %d", + (int)ddf_dev_get_handle(dev)); + + /* + * We need to disable byte swapping of the outgoing and incoming + * PCI data, because the PCI driver assumes no byte swapping behind + * the scenes and takes care of it itself. + */ + ret = pio_enable((void *) GT_BASE, GT_SIZE, (void **) >); + if (ret != EOK) + return ret; + val = uint32_t_le2host(pio_read_32( + >[GT_PCI_CMD / sizeof(ioport32_t)])); + val |= GT_PCI_CMD_MBYTESWAP; + pio_write_32( + >[GT_PCI_CMD / sizeof(ioport32_t)], host2uint32_t_le(val)); + + + /* Register functions. */ + if (!malta_add_functions(dev)) { + ddf_msg(LVL_ERROR, "Failed to add functions for the Malta platform."); + } + + return EOK; +} + +static void root_malta_init(void) +{ + ddf_log_init(NAME); + malta_fun_ops.interfaces[HW_RES_DEV_IFACE] = &fun_hw_res_ops; + malta_fun_ops.interfaces[PIO_WINDOW_DEV_IFACE] = &fun_pio_window_ops; +} + +int main(int argc, char *argv[]) +{ + printf(NAME ": HelenOS Malta platform driver\n"); + root_malta_init(); + return ddf_driver_main(&malta_driver); +} + +/** + * @} + */ Index: uspace/drv/platform/malta/malta.ma =================================================================== --- uspace/drv/platform/malta/malta.ma (revision 2a37b9f1eb93bba78ec231d42ef29f30dff550a0) +++ uspace/drv/platform/malta/malta.ma (revision 2a37b9f1eb93bba78ec231d42ef29f30dff550a0) @@ -0,0 +1,1 @@ +10 platform/malta Index: uspace/drv/platform/pc/Makefile =================================================================== --- uspace/drv/platform/pc/Makefile (revision 2a37b9f1eb93bba78ec231d42ef29f30dff550a0) +++ uspace/drv/platform/pc/Makefile (revision 2a37b9f1eb93bba78ec231d42ef29f30dff550a0) @@ -0,0 +1,37 @@ +# +# Copyright (c) 2010 Lenka Trochtova +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# - Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# - Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# - The name of the author may not be used to endorse or promote products +# derived from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR +# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# + +USPACE_PREFIX = ../../.. +LIBS = $(LIBDRV_PREFIX)/libdrv.a +EXTRA_CFLAGS += -I$(LIBDRV_PREFIX)/include +BINARY = pc + +SOURCES = \ + pc.c + +include $(USPACE_PREFIX)/Makefile.common Index: uspace/drv/platform/pc/pc.c =================================================================== --- uspace/drv/platform/pc/pc.c (revision 2a37b9f1eb93bba78ec231d42ef29f30dff550a0) +++ uspace/drv/platform/pc/pc.c (revision 2a37b9f1eb93bba78ec231d42ef29f30dff550a0) @@ -0,0 +1,236 @@ +/* + * Copyright (c) 2010 Lenka Trochtova + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** + * @defgroup root_pc PC platform driver. + * @brief HelenOS PC platform driver. + * @{ + */ + +/** @file + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#define NAME "pc" + +typedef struct pc_fun { + hw_resource_list_t hw_resources; + pio_window_t pio_window; +} pc_fun_t; + +static int pc_dev_add(ddf_dev_t *dev); +static void root_pc_init(void); + +/** The root device driver's standard operations. */ +static driver_ops_t pc_ops = { + .dev_add = &pc_dev_add +}; + +/** The root device driver structure. */ +static driver_t pc_driver = { + .name = NAME, + .driver_ops = &pc_ops +}; + +static hw_resource_t pci_conf_regs[] = { + { + .type = IO_RANGE, + .res.io_range = { + .address = 0xCF8, + .size = 4, + .relative = false, + .endianness = LITTLE_ENDIAN + } + }, + { + .type = IO_RANGE, + .res.io_range = { + .address = 0xCFC, + .size = 4, + .relative = false, + .endianness = LITTLE_ENDIAN + } + } +}; + +static pc_fun_t pci_data = { + .hw_resources = { + sizeof(pci_conf_regs) / sizeof(pci_conf_regs[0]), + pci_conf_regs + }, + .pio_window = { + .mem = { + .base = UINT32_C(0), + .size = UINT32_C(0xffffffff) /* practical maximum */ + }, + .io = { + .base = UINT32_C(0), + .size = UINT32_C(0x10000) + } + } +}; + +/** Obtain function soft-state from DDF function node */ +static pc_fun_t *pc_fun(ddf_fun_t *fnode) +{ + return ddf_fun_data_get(fnode); +} + +static hw_resource_list_t *pc_get_resources(ddf_fun_t *fnode) +{ + pc_fun_t *fun = pc_fun(fnode); + + assert(fun != NULL); + return &fun->hw_resources; +} + +static bool pc_enable_interrupt(ddf_fun_t *fun) +{ + /* TODO */ + + return false; +} + +static pio_window_t *pc_get_pio_window(ddf_fun_t *fnode) +{ + pc_fun_t *fun = pc_fun(fnode); + + assert(fun != NULL); + return &fun->pio_window; +} + +static hw_res_ops_t fun_hw_res_ops = { + .get_resource_list = &pc_get_resources, + .enable_interrupt = &pc_enable_interrupt, +}; + +static pio_window_ops_t fun_pio_window_ops = { + .get_pio_window = &pc_get_pio_window +}; + +/* Initialized in root_pc_init() function. */ +static ddf_dev_ops_t pc_fun_ops; + +static bool +pc_add_fun(ddf_dev_t *dev, const char *name, const char *str_match_id, + pc_fun_t *fun_proto) +{ + ddf_msg(LVL_DEBUG, "Adding new function '%s'.", name); + + ddf_fun_t *fnode = NULL; + int rc; + + /* Create new device. */ + fnode = ddf_fun_create(dev, fun_inner, name); + if (fnode == NULL) + goto failure; + + pc_fun_t *fun = ddf_fun_data_alloc(fnode, sizeof(pc_fun_t)); + *fun = *fun_proto; + + /* Add match ID */ + rc = ddf_fun_add_match_id(fnode, str_match_id, 100); + if (rc != EOK) + goto failure; + + /* Set provided operations to the device. */ + ddf_fun_set_ops(fnode, &pc_fun_ops); + + /* Register function. */ + if (ddf_fun_bind(fnode) != EOK) { + ddf_msg(LVL_ERROR, "Failed binding function %s.", name); + goto failure; + } + + return true; + +failure: + if (fnode != NULL) + ddf_fun_destroy(fnode); + + ddf_msg(LVL_ERROR, "Failed adding function '%s'.", name); + + return false; +} + +static bool pc_add_functions(ddf_dev_t *dev) +{ + return pc_add_fun(dev, "pci0", "intel_pci", &pci_data); +} + +/** Get the root device. + * + * @param dev The device which is root of the whole device tree (both + * of HW and pseudo devices). + * @return Zero on success, negative error number otherwise. + */ +static int pc_dev_add(ddf_dev_t *dev) +{ + ddf_msg(LVL_DEBUG, "pc_dev_add, device handle = %d", + (int)ddf_dev_get_handle(dev)); + + /* Register functions. */ + if (!pc_add_functions(dev)) { + ddf_msg(LVL_ERROR, "Failed to add functions for PC platform."); + } + + return EOK; +} + +static void root_pc_init(void) +{ + ddf_log_init(NAME); + pc_fun_ops.interfaces[HW_RES_DEV_IFACE] = &fun_hw_res_ops; + pc_fun_ops.interfaces[PIO_WINDOW_DEV_IFACE] = &fun_pio_window_ops; +} + +int main(int argc, char *argv[]) +{ + printf(NAME ": HelenOS PC platform driver\n"); + root_pc_init(); + return ddf_driver_main(&pc_driver); +} + +/** + * @} + */ Index: uspace/drv/platform/pc/pc.ma =================================================================== --- uspace/drv/platform/pc/pc.ma (revision 2a37b9f1eb93bba78ec231d42ef29f30dff550a0) +++ uspace/drv/platform/pc/pc.ma (revision 2a37b9f1eb93bba78ec231d42ef29f30dff550a0) @@ -0,0 +1,1 @@ +10 platform/pc