Index: kernel/arch/mips32/include/context_offset.h
===================================================================
--- kernel/arch/mips32/include/context_offset.h	(revision 2fa10f640409c06070df4329491173719b3e824c)
+++ kernel/arch/mips32/include/context_offset.h	(revision 29fa68bbd80a0d830177316309af3cdd6a2b3044)
@@ -60,32 +60,4 @@
 # define OFFSET_F30     0x5c
 #endif /* KERNEL */
-
-/* istate_t */
-#define EOFFSET_AT     0x0
-#define EOFFSET_V0     0x4
-#define EOFFSET_V1     0x8
-#define EOFFSET_A0     0xc
-#define EOFFSET_A1     0x10
-#define EOFFSET_A2     0x14
-#define EOFFSET_A3     0x18
-#define EOFFSET_T0     0x1c
-#define EOFFSET_T1     0x20
-#define EOFFSET_T2     0x24
-#define EOFFSET_T3     0x28
-#define EOFFSET_T4     0x2c
-#define EOFFSET_T5     0x30
-#define EOFFSET_T6     0x34
-#define EOFFSET_T7     0x38
-#define EOFFSET_T8     0x3c
-#define EOFFSET_T9     0x40
-#define EOFFSET_GP     0x44
-#define EOFFSET_SP     0x48
-#define EOFFSET_RA     0x4c
-#define EOFFSET_LO     0x50
-#define EOFFSET_HI     0x54
-#define EOFFSET_STATUS 0x58
-#define EOFFSET_EPC    0x5c
-#define EOFFSET_K1     0x60
-#define REGISTER_SPACE 104	/* respect stack alignment */
 
 #ifdef __ASM__
Index: kernel/arch/mips32/include/exception.h
===================================================================
--- kernel/arch/mips32/include/exception.h	(revision 2fa10f640409c06070df4329491173719b3e824c)
+++ kernel/arch/mips32/include/exception.h	(revision 29fa68bbd80a0d830177316309af3cdd6a2b3044)
@@ -60,13 +60,17 @@
 
 typedef struct istate {
+	/*
+	 * The first seven registers are arranged so that the istate structure
+	 * can be used both for exception handlers and for the syscall handler.
+	 */
+	uint32_t a0;	/* arg1 */
+	uint32_t a1;	/* arg2 */
+	uint32_t a2;	/* arg3 */
+	uint32_t a3;	/* arg4 */
+	uint32_t t0;	/* arg5 */
+	uint32_t t1;	/* arg6 */
+	uint32_t v0;	/* arg7 */
+	uint32_t v1;
 	uint32_t at;
-	uint32_t v0;
-	uint32_t v1;
-	uint32_t a0;
-	uint32_t a1;
-	uint32_t a2;
-	uint32_t a3;
-	uint32_t t0;
-	uint32_t t1;
 	uint32_t t2;
 	uint32_t t3;
@@ -75,8 +79,19 @@
 	uint32_t t6;
 	uint32_t t7;
+	uint32_t s0;
+	uint32_t s1;
+	uint32_t s2;
+	uint32_t s3;
+	uint32_t s4;
+	uint32_t s5;
+	uint32_t s6;
+	uint32_t s7;
 	uint32_t t8;
 	uint32_t t9;
+	uint32_t kt0;
+	uint32_t kt1;	/* We use it as thread-local pointer */
 	uint32_t gp;
 	uint32_t sp;
+	uint32_t s8;
 	uint32_t ra;
 	
@@ -84,7 +99,8 @@
 	uint32_t hi;
 	
-	uint32_t status;  /* cp0_status */
-	uint32_t epc;     /* cp0_epc */
-	uint32_t k1;      /* We use it as thread-local pointer */
+	uint32_t status;	/* cp0_status */
+	uint32_t epc;		/* cp0_epc */
+
+	uint32_t alignment;	/* to make sizeof(istate_t) a multiple of 8 */
 } istate_t;
 
@@ -108,7 +124,5 @@
 NO_TRACE static inline unative_t istate_get_fp(istate_t *istate)
 {
-	/* FIXME */
-	
-	return 0;
+	return istate->sp;
 }
 
Index: kernel/arch/mips32/src/debug/stacktrace.c
===================================================================
--- kernel/arch/mips32/src/debug/stacktrace.c	(revision 2fa10f640409c06070df4329491173719b3e824c)
+++ kernel/arch/mips32/src/debug/stacktrace.c	(revision 29fa68bbd80a0d830177316309af3cdd6a2b3044)
@@ -31,4 +31,32 @@
  */
 /** @file
+ */
+
+/*
+ * This stack tracing code is based on the suggested algorithm described on page
+ * 3-27 and 3-28 of:
+ * 
+ * SYSTEM V
+ * APPLICATION BINARY INTERFACE
+ *
+ * MIPS RISC Processor
+ * Supplement
+ * 3rd Edition
+ *
+ * Unfortunately, GCC generates code which is not entirely compliant with this
+ * method. For example, it places the "jr ra" instruction quite arbitrarily in
+ * the middle of the function which makes the original algorithm unapplicable.
+ *
+ * We deal with this problem by simply not using those parts of the algorithm
+ * that rely on the "jr ra" instruction occurring in the last basic block of a
+ * function, which gives us still usable, but less reliable stack tracer. The
+ * unreliability stems from the fact that under some circumstances it can become
+ * confused and produce incorrect or incomplete stack trace. We apply extra
+ * sanity checks so that the algorithm is still safe and should not crash the
+ * system.
+ *
+ * Even though not perfect, our solution is pretty lightweight, especially when
+ * compared with a prospective alternative solution based on additional
+ * debugging information stored directly in the kernel image.
  */
 
@@ -96,4 +124,10 @@
 extern char ktext_end;
 
+static bool bounds_check(uintptr_t pc)
+{
+	return (pc >= (uintptr_t) &ktext_start) &&
+	    (pc < (uintptr_t) &ktext_end);
+}
+
 static bool
 scan(stack_trace_context_t *ctx, uintptr_t *prev_fp, uintptr_t *prev_ra)
@@ -106,4 +140,6 @@
 	do {
 		inst--;
+		if (!bounds_check((uintptr_t) inst))
+			return false;
 #if 0
 		/*
@@ -180,5 +216,5 @@
 					return false;
 				/* too big offsets are suspicious */
-				if (offset > 32 * 4)
+				if ((size_t) offset > sizeof(istate_t))
 					return false;
 
@@ -207,6 +243,5 @@
 {
 	return !((ctx->fp == 0) || ((ctx->fp % 8) != 0) ||
-	    (ctx->pc % 4 != 0) || (ctx->pc < (uintptr_t) &ktext_start) ||
-	    (ctx->pc >= (uintptr_t) &ktext_end));
+	    (ctx->pc % 4 != 0) || !bounds_check(ctx->pc));
 }
 
Index: kernel/arch/mips32/src/exception.c
===================================================================
--- kernel/arch/mips32/src/exception.c	(revision 2fa10f640409c06070df4329491173719b3e824c)
+++ kernel/arch/mips32/src/exception.c	(revision 29fa68bbd80a0d830177316309af3cdd6a2b3044)
@@ -74,14 +74,22 @@
 void istate_decode(istate_t *istate)
 {
-	printf("at=%p\tv0=%p\tv1=%p\n", istate->at, istate->v0, istate->v1);
-	printf("a0=%p\ta1=%p\ta2=%p\n", istate->a0, istate->a1, istate->a2);
-	printf("a3=%p\tt0=%p\tt1=%p\n", istate->a3, istate->t0, istate->t1);
-	printf("t2=%p\tt3=%p\tt4=%p\n", istate->t2, istate->t3, istate->t4);
-	printf("t5=%p\tt6=%p\tt7=%p\n", istate->t5, istate->t6, istate->t7);
-	printf("t8=%p\tt9=%p\tgp=%p\n", istate->t8, istate->t9, istate->gp);
-	printf("sp=%p\tra=%p\t\n", istate->sp, istate->ra);
-	printf("lo=%p\thi=%p\t\n", istate->lo, istate->hi);
-	printf("cp0_status=%p\tcp0_epc=%p\tk1=%p\n",
-	    istate->status, istate->epc, istate->k1);
+	printf("epc=%p\tsta=%p\tlo =%p\thi =%p\n",
+	    istate->epc, istate->status, istate->lo, istate->hi);
+	printf("a0 =%p\ta1 =%p\ta2 =%p\ta3 =%p\n",
+	    istate->a0, istate->a1, istate->a2, istate->a3);
+	printf("t0 =%p\tt1 =%p\tt2 =%p\tt3 =%p\n",
+	    istate->t0, istate->t1, istate->t2, istate->t3);
+	printf("t4 =%p\tt5 =%p\tt6 =%p\tt7 =%p\n",
+	    istate->t4, istate->t5, istate->t6, istate->t7);
+	printf("t8 =%p\tt9 =%p\tv0 =%p\tv1 =%p\n",
+	    istate->t8, istate->t9, istate->v0, istate->v1);
+	printf("s0 =%p\ts1 =%p\ts2 =%p\ts3 =%p\n",
+	    istate->s0, istate->s1, istate->s2, istate->s3);
+	printf("s4 =%p\ts5 =%p\ts6 =%p\ts7 =%p\n",
+	    istate->s4, istate->s5, istate->s6, istate->s7);
+	printf("s8 =%p\tat =%p\tkt0=%p\tkt1=%p\n",
+	    istate->s8, istate->at, istate->kt0, istate->kt1);
+	printf("sp =%p\tra =%p\tgp =%p\n",
+	    istate->sp, istate->ra, istate->gp);
 }
 
@@ -97,5 +105,5 @@
 		ASSERT(THREAD);
 		istate->epc += 4;
-		istate->v1 = istate->k1;
+		istate->v1 = istate->kt1;
 	} else
 		unhandled_exception(n, istate);
Index: kernel/arch/mips32/src/start.S
===================================================================
--- kernel/arch/mips32/src/start.S	(revision 2fa10f640409c06070df4329491173719b3e824c)
+++ kernel/arch/mips32/src/start.S	(revision 29fa68bbd80a0d830177316309af3cdd6a2b3044)
@@ -46,8 +46,58 @@
 
 /*
- * Which status bits should are thread-local:
+ * Which status bits are thread-local:
  * KSU(UM), EXL, ERL, IE
  */
 #define REG_SAVE_MASK 0x1f
+
+#define ISTATE_OFFSET_A0	0
+#define ISTATE_OFFSET_A1	4
+#define ISTATE_OFFSET_A2	8
+#define ISTATE_OFFSET_A3	12
+#define ISTATE_OFFSET_T0	16
+#define ISTATE_OFFSET_T1	20
+#define ISTATE_OFFSET_V0	24
+#define ISTATE_OFFSET_V1	28
+#define ISTATE_OFFSET_AT	32
+#define ISTATE_OFFSET_T2	36
+#define ISTATE_OFFSET_T3	40
+#define ISTATE_OFFSET_T4	44
+#define ISTATE_OFFSET_T5	48
+#define ISTATE_OFFSET_T6	52
+#define ISTATE_OFFSET_T7	56
+#define ISTATE_OFFSET_S0	60
+#define ISTATE_OFFSET_S1	64
+#define ISTATE_OFFSET_S2	68
+#define ISTATE_OFFSET_S3	72
+#define ISTATE_OFFSET_S4	76
+#define ISTATE_OFFSET_S5	80
+#define ISTATE_OFFSET_S6	84
+#define ISTATE_OFFSET_S7	88
+#define ISTATE_OFFSET_T8	92
+#define ISTATE_OFFSET_T9	96
+#define ISTATE_OFFSET_KT0	100
+#define ISTATE_OFFSET_KT1	104
+#define ISTATE_OFFSET_GP	108
+#define ISTATE_OFFSET_SP	112
+#define ISTATE_OFFSET_S8	116
+#define ISTATE_OFFSET_RA	120
+#define ISTATE_OFFSET_LO	124
+#define ISTATE_OFFSET_HI	128
+#define ISTATE_OFFSET_STATUS	132
+#define ISTATE_OFFSET_EPC	136
+#define ISTATE_OFFSET_ALIGNMENT	140
+
+#define ISTATE_SOFT_SIZE	144
+
+/*
+ * The fake ABI prologue is never executed and may not be part of the
+ * procedure's body. Instead, it should be immediately preceding the procedure's
+ * body. Its only purpose is to trick the stack trace walker into thinking that
+ * the exception is more or less just a normal function call.
+ */
+.macro FAKE_ABI_PROLOGUE
+	sub $sp, ISTATE_SOFT_SIZE
+	sw $ra, ISTATE_OFFSET_EPC($sp)
+.endm
 
 /*
@@ -58,30 +108,40 @@
  */
 .macro REGISTERS_STORE_AND_EXC_RESET r
-	sw $at, EOFFSET_AT(\r)
-	sw $v0, EOFFSET_V0(\r)
-	sw $v1, EOFFSET_V1(\r)
-	sw $a0, EOFFSET_A0(\r)
-	sw $a1, EOFFSET_A1(\r)
-	sw $a2, EOFFSET_A2(\r)
-	sw $a3, EOFFSET_A3(\r)
-	sw $t0, EOFFSET_T0(\r)
-	sw $t1, EOFFSET_T1(\r)
-	sw $t2, EOFFSET_T2(\r)
-	sw $t3, EOFFSET_T3(\r)
-	sw $t4, EOFFSET_T4(\r)
-	sw $t5, EOFFSET_T5(\r)
-	sw $t6, EOFFSET_T6(\r)
-	sw $t7, EOFFSET_T7(\r)
-	sw $t8, EOFFSET_T8(\r)
-	sw $t9, EOFFSET_T9(\r)
+	sw $at, ISTATE_OFFSET_AT(\r)
+	sw $v0, ISTATE_OFFSET_V0(\r)
+	sw $v1, ISTATE_OFFSET_V1(\r)
+	sw $a0, ISTATE_OFFSET_A0(\r)
+	sw $a1, ISTATE_OFFSET_A1(\r)
+	sw $a2, ISTATE_OFFSET_A2(\r)
+	sw $a3, ISTATE_OFFSET_A3(\r)
+	sw $t0, ISTATE_OFFSET_T0(\r)
+	sw $t1, ISTATE_OFFSET_T1(\r)
+	sw $t2, ISTATE_OFFSET_T2(\r)
+	sw $t3, ISTATE_OFFSET_T3(\r)
+	sw $t4, ISTATE_OFFSET_T4(\r)
+	sw $t5, ISTATE_OFFSET_T5(\r)
+	sw $t6, ISTATE_OFFSET_T6(\r)
+	sw $t7, ISTATE_OFFSET_T7(\r)
+	sw $t8, ISTATE_OFFSET_T8(\r)
+	sw $t9, ISTATE_OFFSET_T9(\r)
+	sw $s0, ISTATE_OFFSET_S0(\r)
+	sw $s1, ISTATE_OFFSET_S1(\r)
+	sw $s2, ISTATE_OFFSET_S2(\r)
+	sw $s3, ISTATE_OFFSET_S3(\r)
+	sw $s4, ISTATE_OFFSET_S4(\r)
+	sw $s5, ISTATE_OFFSET_S5(\r)
+	sw $s6, ISTATE_OFFSET_S6(\r)
+	sw $s7, ISTATE_OFFSET_S7(\r)
+	sw $s8, ISTATE_OFFSET_S8(\r)
 	
 	mflo $at
-	sw $at, EOFFSET_LO(\r)
+	sw $at, ISTATE_OFFSET_LO(\r)
 	mfhi $at
-	sw $at, EOFFSET_HI(\r)
-	
-	sw $gp, EOFFSET_GP(\r)
-	sw $ra, EOFFSET_RA(\r)
-	sw $k1, EOFFSET_K1(\r)
+	sw $at, ISTATE_OFFSET_HI(\r)
+	
+	sw $gp, ISTATE_OFFSET_GP(\r)
+	sw $ra, ISTATE_OFFSET_RA(\r)
+	sw $k0, ISTATE_OFFSET_KT0(\r)
+	sw $k1, ISTATE_OFFSET_KT1(\r)
 	
 	mfc0 $t0, $status
@@ -95,6 +155,6 @@
 	and $t0, $t0, $t3
 	
-	sw $t2, EOFFSET_STATUS(\r)
-	sw $t1, EOFFSET_EPC(\r)
+	sw $t2, ISTATE_OFFSET_STATUS(\r)
+	sw $t1, ISTATE_OFFSET_EPC(\r)
 	mtc0 $t0, $status
 .endm
@@ -106,5 +166,5 @@
 	 */
 	mfc0 $t0, $status
-	lw $t1,EOFFSET_STATUS(\r)
+	lw $t1, ISTATE_OFFSET_STATUS(\r)
 	
 	/* mask UM, EXL, ERL, IE */
@@ -116,35 +176,35 @@
 	mtc0 $t0, $status
 	
-	lw $v0, EOFFSET_V0(\r)
-	lw $v1, EOFFSET_V1(\r)
-	lw $a0, EOFFSET_A0(\r)
-	lw $a1, EOFFSET_A1(\r)
-	lw $a2, EOFFSET_A2(\r)
-	lw $a3, EOFFSET_A3(\r)
-	lw $t0, EOFFSET_T0(\r)
-	lw $t1, EOFFSET_T1(\r)
-	lw $t2, EOFFSET_T2(\r)
-	lw $t3, EOFFSET_T3(\r)
-	lw $t4, EOFFSET_T4(\r)
-	lw $t5, EOFFSET_T5(\r)
-	lw $t6, EOFFSET_T6(\r)
-	lw $t7, EOFFSET_T7(\r)
-	lw $t8, EOFFSET_T8(\r)
-	lw $t9, EOFFSET_T9(\r)
-	
-	lw $gp, EOFFSET_GP(\r)
-	lw $ra, EOFFSET_RA(\r)
-	lw $k1, EOFFSET_K1(\r)
-	
-	lw $at, EOFFSET_LO(\r)
+	lw $v0, ISTATE_OFFSET_V0(\r)
+	lw $v1, ISTATE_OFFSET_V1(\r)
+	lw $a0, ISTATE_OFFSET_A0(\r)
+	lw $a1, ISTATE_OFFSET_A1(\r)
+	lw $a2, ISTATE_OFFSET_A2(\r)
+	lw $a3, ISTATE_OFFSET_A3(\r)
+	lw $t0, ISTATE_OFFSET_T0(\r)
+	lw $t1, ISTATE_OFFSET_T1(\r)
+	lw $t2, ISTATE_OFFSET_T2(\r)
+	lw $t3, ISTATE_OFFSET_T3(\r)
+	lw $t4, ISTATE_OFFSET_T4(\r)
+	lw $t5, ISTATE_OFFSET_T5(\r)
+	lw $t6, ISTATE_OFFSET_T6(\r)
+	lw $t7, ISTATE_OFFSET_T7(\r)
+	lw $t8, ISTATE_OFFSET_T8(\r)
+	lw $t9, ISTATE_OFFSET_T9(\r)
+	
+	lw $gp, ISTATE_OFFSET_GP(\r)
+	lw $ra, ISTATE_OFFSET_RA(\r)
+	lw $k1, ISTATE_OFFSET_KT1(\r)
+	
+	lw $at, ISTATE_OFFSET_LO(\r)
 	mtlo $at
-	lw $at, EOFFSET_HI(\r)
+	lw $at, ISTATE_OFFSET_HI(\r)
 	mthi $at
 	
-	lw $at, EOFFSET_EPC(\r)
+	lw $at, ISTATE_OFFSET_EPC(\r)
 	mtc0 $at, $epc
 	
-	lw $at, EOFFSET_AT(\r)
-	lw $sp, EOFFSET_SP(\r)
+	lw $at, ISTATE_OFFSET_AT(\r)
+	lw $sp, ISTATE_OFFSET_SP(\r)
 .endm
 
@@ -159,5 +219,5 @@
 	
 	beq $k0, $0, 1f
-	add $k0, $sp, 0
+	move $k0, $sp
 	
 	/* move $k0 pointer to kernel stack */
@@ -166,5 +226,5 @@
 	
 	/* move $k0 (supervisor_sp) */
-	lw $k0, 0($k0)
+	lw $k0, ($k0)
 	
 	1:
@@ -202,9 +262,10 @@
 	nop
 
+	FAKE_ABI_PROLOGUE
 exception_handler:
 	KERNEL_STACK_TO_K0
 	
-	sub $k0, REGISTER_SPACE
-	sw $sp, EOFFSET_SP($k0)
+	sub $k0, ISTATE_SOFT_SIZE
+	sw $sp, ISTATE_OFFSET_SP($k0)
 	move $sp, $k0
 	
@@ -227,9 +288,4 @@
 	/* the $sp is automatically restored to former value */
 	eret
-
-#define SS_SP      EOFFSET_SP
-#define SS_STATUS  EOFFSET_STATUS
-#define SS_EPC     EOFFSET_EPC
-#define SS_K1      EOFFSET_K1
 
 /** Syscall entry
@@ -249,9 +305,8 @@
  */
 syscall_shortcut:
-	/* we have a lot of space on the stack, with free use */
 	mfc0 $t3, $epc
 	mfc0 $t2, $status
-	sw $t3, SS_EPC($sp)  /* save EPC */
-	sw $k1, SS_K1($sp)   /* save $k1 not saved on context switch */
+	sw $t3, ISTATE_OFFSET_EPC($sp)  /* save EPC */
+	sw $k1, ISTATE_OFFSET_KT1($sp)  /* save $k1 not saved on context switch */
 	
 	and $t4, $t2, REG_SAVE_MASK  /* save only KSU, EXL, ERL, IE */
@@ -260,20 +315,19 @@
 	ori $t2, $t2, 0x1  /* set IE */
 	
-	sw $t4, SS_STATUS($sp)
+	sw $t4, ISTATE_OFFSET_STATUS($sp)
 	mtc0 $t2, $status
 	
 	/*
 	 * Call the higher level system call handler.
-	 * We are going to reuse part of the unused exception stack frame.
 	 *
 	 */
-	sw $t0, STACK_ARG4($sp)  /* save the 5th argument on the stack */
-	sw $t1, STACK_ARG5($sp)  /* save the 6th argument on the stack */
+	sw $t0, ISTATE_OFFSET_T0($sp)  /* save the 5th argument on the stack */
+	sw $t1, ISTATE_OFFSET_T1($sp)  /* save the 6th argument on the stack */
 	jal syscall_handler
-	sw $v0, STACK_ARG6($sp)  /* save the syscall number on the stack */
+	sw $v0, ISTATE_OFFSET_V0($sp)  /* save the syscall number on the stack */
 	
 	/* restore status */
 	mfc0 $t2, $status
-	lw $t3, SS_STATUS($sp)
+	lw $t3, ISTATE_OFFSET_STATUS($sp)
 	
 	/*
@@ -288,34 +342,36 @@
 	
 	/* restore epc + 4 */
-	lw $t2, SS_EPC($sp)
-	lw $k1, SS_K1($sp)
+	lw $t2, ISTATE_OFFSET_EPC($sp)
+	lw $k1, ISTATE_OFFSET_KT1($sp)
 	addi $t2, $t2, 4
 	mtc0 $t2, $epc
 	
-	lw $sp, SS_SP($sp)  /* restore $sp */
-	eret
-
+	lw $sp, ISTATE_OFFSET_SP($sp)  /* restore $sp */
+	eret
+
+	FAKE_ABI_PROLOGUE
 tlb_refill_handler:
 	KERNEL_STACK_TO_K0
-	sub $k0, REGISTER_SPACE
+	sub $k0, ISTATE_SOFT_SIZE
 	REGISTERS_STORE_AND_EXC_RESET $k0
-	sw $sp,EOFFSET_SP($k0)
-	add $sp, $k0, 0
+	sw $sp, ISTATE_OFFSET_SP($k0)
+	move $sp, $k0
 	
 	jal tlb_refill
-	add $a0, $sp, 0 
+	move $a0, $sp 
 	
 	REGISTERS_LOAD $sp
 	eret
 
+	FAKE_ABI_PROLOGUE
 cache_error_handler:
 	KERNEL_STACK_TO_K0
-	sub $k0, REGISTER_SPACE
+	sub $k0, ISTATE_SOFT_SIZE 
 	REGISTERS_STORE_AND_EXC_RESET $k0
-	sw $sp,EOFFSET_SP($k0)
-	add $sp, $k0, 0
+	sw $sp, ISTATE_OFFSET_SP($k0)
+	move $sp, $k0
 	
 	jal cache_error
-	add $a0, $sp, 0
+	move $a0, $sp
 	
 	REGISTERS_LOAD $sp
@@ -323,7 +379,7 @@
 
 userspace_asm:
-	add $sp, $a0, 0
-	add $v0, $a1, 0
-	add $t9, $a2, 0    /* set up correct entry into PIC code */
+	move $sp, $a0
+	move $v0, $a1
+	move $t9, $a2      /* set up correct entry into PIC code */
 	xor $a0, $a0, $a0  /* $a0 is defined to hold pcb_ptr */
 	                   /* set it to 0 */