Index: boot/arch/arm32/src/asm.S
===================================================================
--- boot/arch/arm32/src/asm.S	(revision 9120b697b6954bfb0398d62934a04ba6394c8e6e)
+++ boot/arch/arm32/src/asm.S	(revision 296a80e2d4d51e45c959768550ffb9137741db4b)
@@ -56,5 +56,4 @@
 jump_to_kernel:
 	#
-	# TODO
 	# Make sure that the I-cache, D-cache and memory are mutually coherent
 	# before passing control to the copied code.
@@ -68,12 +67,19 @@
 #define CP15_C1_BP		11
 #define CP15_C1_DC		2
-	# Disable I-cache and D-cache before the kernel is started.
+
+
+#ifndef PROCESSOR_ARCH_armv7_a
 	mrc	p15, 0, r4, c1, c0, 0
+	
+	# D-cache before the kernel is started.
 	bic	r4, r4, #(1 << CP15_C1_DC)
-#ifndef PROCESSOR_ARCH_armv7_a
+
+	#Disable I-cache and Branche predicotrs on non-armv7
 	bic	r4, r4, #(1 << CP15_C1_IC)
 	bic	r4, r4, #(1 << CP15_C1_BP)
+	
+	mcr	p15, 0, r4, c1, c0, 0
 #endif
-	mcr	p15, 0, r4, c1, c0, 0
+
 
 	
@@ -82,4 +88,5 @@
 	dsb
 #else
+	andi r4, 0
 	#cp15 dsb, r4 is ignored (should be zero)
 	mcr p15, 0, r4, c7, c10, 4
Index: kernel/arch/arm32/include/arch/mm/page_armv6.h
===================================================================
--- kernel/arch/arm32/include/arch/mm/page_armv6.h	(revision 9120b697b6954bfb0398d62934a04ba6394c8e6e)
+++ kernel/arch/arm32/include/arch/mm/page_armv6.h	(revision 296a80e2d4d51e45c959768550ffb9137741db4b)
@@ -205,5 +205,6 @@
 		p->ns = 0;
 	}
-	DCCMVAU_write((uint32_t)p);
+	DCCMVAC_write((uint32_t)p);
+	//TODO: DCCMVAU should be enough but it does not work.
 }
 
@@ -236,11 +237,17 @@
 	 * tex=0 buf=1 and cache=0 => shareable device mmio
 	 */
-	p->cacheable = (flags & PAGE_CACHEABLE);
+
+	if (flags & PAGE_CACHEABLE) {
+		p->tex = 1;
+		p->cacheable = 1;
+	} else {
+		p->tex = 0;
+		p->cacheable = 0;
+	}
 	p->bufferable = 1;
-	p->tex = 0;
 	
 	/* Shareable is ignored for devices (non-cacheable),
 	 * turn it on for normal memory. */
-	p->shareable = 1;
+	p->shareable = 0;
 	
 	p->non_global = !(flags & PAGE_GLOBAL);
@@ -256,5 +263,6 @@
 			p->access_permission_1 = PTE_AP1_RO;
 	}
-	DCCMVAU_write((uint32_t)p);
+	DCCMVAC_write((uint32_t)p);
+	//TODO: DCCMVAU should be enough but it does not work.
 }
 
@@ -267,5 +275,6 @@
 	write_barrier();
 	p->descriptor_type = PTE_DESCRIPTOR_COARSE_TABLE;
-	DCCMVAU_write((uint32_t)p);
+	DCCMVAC_write((uint32_t)p);
+	//TODO: DCCMVAU should be enough but it does not work.
 }
 
@@ -275,5 +284,6 @@
 
 	p->descriptor_type = PTE_DESCRIPTOR_SMALL_PAGE;
-	DCCMVAU_write((uint32_t)p);
+	DCCMVAC_write((uint32_t)p);
+	//TODO: DCCMVAU should be enough but it does not work.
 }