Index: kernel/arch/arm32/include/arch/mm/page_armv6.h
===================================================================
--- kernel/arch/arm32/include/arch/mm/page_armv6.h	(revision 070349e348ec04212ca086b3a7d79298586ff93e)
+++ kernel/arch/arm32/include/arch/mm/page_armv6.h	(revision 296a80e2d4d51e45c959768550ffb9137741db4b)
@@ -205,5 +205,6 @@
 		p->ns = 0;
 	}
-	DCCMVAU_write((uint32_t)p);
+	DCCMVAC_write((uint32_t)p);
+	//TODO: DCCMVAU should be enough but it does not work.
 }
 
@@ -236,11 +237,17 @@
 	 * tex=0 buf=1 and cache=0 => shareable device mmio
 	 */
-	p->cacheable = (flags & PAGE_CACHEABLE);
+
+	if (flags & PAGE_CACHEABLE) {
+		p->tex = 1;
+		p->cacheable = 1;
+	} else {
+		p->tex = 0;
+		p->cacheable = 0;
+	}
 	p->bufferable = 1;
-	p->tex = 0;
 	
 	/* Shareable is ignored for devices (non-cacheable),
 	 * turn it on for normal memory. */
-	p->shareable = 1;
+	p->shareable = 0;
 	
 	p->non_global = !(flags & PAGE_GLOBAL);
@@ -256,5 +263,6 @@
 			p->access_permission_1 = PTE_AP1_RO;
 	}
-	DCCMVAU_write((uint32_t)p);
+	DCCMVAC_write((uint32_t)p);
+	//TODO: DCCMVAU should be enough but it does not work.
 }
 
@@ -267,5 +275,6 @@
 	write_barrier();
 	p->descriptor_type = PTE_DESCRIPTOR_COARSE_TABLE;
-	DCCMVAU_write((uint32_t)p);
+	DCCMVAC_write((uint32_t)p);
+	//TODO: DCCMVAU should be enough but it does not work.
 }
 
@@ -275,5 +284,6 @@
 
 	p->descriptor_type = PTE_DESCRIPTOR_SMALL_PAGE;
-	DCCMVAU_write((uint32_t)p);
+	DCCMVAC_write((uint32_t)p);
+	//TODO: DCCMVAU should be enough but it does not work.
 }