Changeset 28f81d21 in mainline


Ignore:
Timestamp:
2012-11-24T11:24:35Z (12 years ago)
Author:
Jan Vesely <jano.vesely@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
04cb6957
Parents:
d238aa9
Message:

arm32, fpu context: Use register interval instead of listing every single one

File:
1 edited

Legend:

Unmodified
Added
Removed
  • kernel/arch/arm32/src/cpu/cpu.c

    rd238aa9 r28f81d21  
    172172//              "vmrs r2, fpexc\n"
    173173                "stm %0, {r1, r2}\n"
    174                 "vstm %0, {d0, d1, d2, d3, d4, d5, d6, d7, d8, d9, d10, d11, d12, d13, d14, d15}\n"
     174                "vstm %0, {d0-d15}\n"
    175175                ::"r" (ctx): "r1","r2","memory"
    176176        );
     
    184184                "vmsr fpscr, r1\n"
    185185//              "vmsr fpexc, r2\n"
    186                 "vldm %0, {d0, d1, d2, d3, d4, d5, d6, d7, d8, d9, d10, d11, d12, d13, d14, d15}\n"
     186                "vldm %0, {d0-d15}\n"
    187187                ::"r" (ctx): "r1","r2"
    188188        );
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