Index: kernel/arch/arm32/src/fpu_context.c
===================================================================
--- kernel/arch/arm32/src/fpu_context.c	(revision ab52a3eecc1b2f233980f13b139dc8d7ef4a416e)
+++ kernel/arch/arm32/src/fpu_context.c	(revision 26a8c18d1889eb6baf7ed5b8637eae1ec540730d)
@@ -36,4 +36,5 @@
 #include <fpu_context.h>
 #include <arch.h>
+#include <arch/types.h>
 #include <cpu.h>
 
@@ -44,16 +45,71 @@
 #define FPSID_VARIANT(r)   (((r) >> 4) 0xf)
 #define FPSID_REVISION(r)   (((r) >> 0) 0xf)
+
+
 enum {
 	FPU_VFPv1 = 0x00,
 	FPU_VFPv2_COMMONv1 = 0x01,
 	FPU_VFPv3_COMMONv2 = 0x02,
-	FPU_VFPv3_NO_COMMON = 0x3, /* Does not support trap */
+	FPU_VFPv3_NO_COMMON = 0x3, /* Does not support fpu exc. traps */
 	FPU_VFPv3_COMMONv3 = 0x4,
 };
 
 enum {
-	FPEXC_ENABLED_FLAG = 0x40000000,
-	FPEXC_EX_FLAG = 0x80000000,
+	FPEXC_EX_FLAG = (1 << 31),
+	FPEXC_ENABLED_FLAG = (1 << 30),
 };
+
+/** ARM Architecture Reference Manual ch. B4.1.58, p. B$-1551 */
+enum {
+	FPSCR_N_FLAG = (1 << 31),
+	FPSCR_Z_FLAG = (1 << 30),
+	FPSCR_C_FLAG = (1 << 29),
+	FPSCR_V_FLAG = (1 << 28),
+	FPSCR_QC_FLAG = (1 << 27),
+	FPSCR_AHP_FLAG = (1 << 26),
+	FPSCR_DN_FLAG = (1 << 25),
+	FPSCR_FZ_FLAG = (1 << 24),
+	FPSCR_ROUND_MODE_MASK = (0x3 << 22),
+	FPSCR_ROUND_TO_NEAREST = (0x0 << 22),
+	FPSCR_ROUND_TO_POS_INF = (0x1 << 22),
+	FPSCR_ROUND_TO_NEG_INF = (0x2 << 22),
+	FPSCR_ROUND_TO_ZERO = (0x3 << 22),
+	FPSCR_STRIDE_MASK = (0x3 << 20),
+	FPSCR_STRIDE_SHIFT = 20,
+	FPSCR_LEN_MASK = (0x7 << 16),
+	FPSCR_LEN_SHIFT = 16,
+	FPSCR_DENORMAL_EN_FLAG = (1 << 15),
+	FPSCR_INEXACT_EN_FLAG = (1 << 12),
+	FPSCR_UNDERFLOW_EN_FLAG = (1 << 11),
+	FPSCR_OVERFLOW_EN_FLAG = (1 << 10),
+	FPSCR_ZERO_DIV_EN_FLAG = (1 << 9),
+	FPSCR_INVALID_OP_EN_FLAG = (1 << 8),
+	FPSCR_DENORMAL_FLAG = (1 << 7),
+	FPSCR_INEXACT_FLAG = (1 << 4),
+	FPSCR_UNDERFLOW_FLAG = (1 << 3),
+	FPSCR_OVERLOW_FLAG = (1 << 2),
+	FPSCR_DIV_ZERO_FLAG = (1 << 1),
+	FPSCR_INVALID_OP_FLAG = (1 << 0),
+
+	FPSCR_EN_ALL = FPSCR_DENORMAL_EN_FLAG | FPSCR_INEXACT_EN_FLAG | FPSCR_UNDERFLOW_EN_FLAG | FPSCR_OVERFLOW_EN_FLAG | FPSCR_ZERO_DIV_EN_FLAG | FPSCR_INVALID_OP_EN_FLAG,
+};
+
+static inline uint32_t fpscr_read()
+{
+	uint32_t reg;
+	asm volatile (
+		"vmrs %0, fpscr\n"
+		:"=r" (reg)::
+	);
+	return reg;
+}
+
+static inline void fpscr_write(uint32_t val)
+{
+	asm volatile (
+		"vmsr fpscr, %0\n"
+		::"r" (val):
+	);
+}
 
 static inline uint32_t fpexc_read()
@@ -177,4 +233,8 @@
 	fpexc_write(0);
 	fpu_enable();
+	/* Mask all exception traps,
+	 * The bits are RAZ/WI on archs that don't support fpu exc traps.
+	 */
+	fpscr_write(fpscr_read() & ~FPSCR_EN_ALL);
 }
 
@@ -230,5 +290,7 @@
 	const uint32_t fpexc = fpexc_read();
 	if (fpexc & FPEXC_ENABLED_FLAG) {
-		printf("FPU exception with FPU on\n");
+		const uint32_t fpscr = fpscr_read();
+		printf("FPU exception\n"
+		    "\tFPEXC: %" PRIx32 " FPSCR: %" PRIx32 "\n", fpexc, fpscr);
 		return false;
 	}