Changeset 25eec4e in mainline for kernel/arch/mips32/src/exception.c
- Timestamp:
- 2013-04-19T18:38:18Z (12 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- 6d717a4
- Parents:
- a1e2df13 (diff), 289cb7dd (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
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- 1 edited
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kernel/arch/mips32/src/exception.c
ra1e2df13 r25eec4e 165 165 static void interrupt_exception(unsigned int n, istate_t *istate) 166 166 { 167 uint32_t ip; 168 uint32_t im; 169 167 170 /* Decode interrupt number and process the interrupt */ 168 uint32_t cause = (cp0_cause_read() >> 8) & 0xff; 171 ip = (cp0_cause_read() & cp0_cause_ip_mask) >> cp0_cause_ip_shift; 172 im = (cp0_status_read() & cp0_status_im_mask) >> cp0_status_im_shift; 169 173 170 174 unsigned int i; 171 175 for (i = 0; i < 8; i++) { 172 if (cause & (1 << i)) { 176 177 /* 178 * The interrupt could only occur if it is unmasked in the 179 * status register. On the other hand, an interrupt can be 180 * apparently pending even if it is masked, so we need to 181 * check both the masked and pending interrupts. 182 */ 183 if (im & ip & (1 << i)) { 173 184 irq_t *irq = irq_dispatch_and_lock(i); 174 185 if (irq) {
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