Changes in boot/arch/arm32/src/asm.S [73b3ecd:24bead17] in mainline

File:

• boot/arch/arm32/src/asm.S (modified) (3 diffs)

boot/arch/arm32/src/asm.S

@@ -27 +27 @@
 #
 
-#include <abi/asmtool.h>
 #include <arch/arch.h>
 
 .section BOOTSTRAP
 
-SYMBOL(start)
+.global start
+.global boot_pt
+.global boot_stack
+.global halt
+.global jump_to_kernel
+
+start:
         ldr sp, =boot_stack
         b bootstrap
 
 .section BOOTPT
-SYMBOL(boot_pt)
+boot_pt:
         .space PTL0_ENTRIES * PTL0_ENTRY_SIZE
 
 .section BOOTSTACK
         .space 4096
-SYMBOL(boot_stack)
+boot_stack:
 
 .text
 
-FUNCTION_BEGIN(halt)
+halt:
         b halt
-FUNCTION_END(halt)
 
-FUNCTION_BEGIN(jump_to_kernel)
+jump_to_kernel:
         #
+        # TODO
         # Make sure that the I-cache, D-cache and memory are mutually coherent
         # before passing control to the copied code.
@@ -63 +68 @@
 #define CP15_C1_BP              11
 #define CP15_C1_DC              2
+        # Disable I-cache and D-cache before the kernel is started.
+        mrc     p15, 0, r4, c1, c0, 0
+        bic     r4, r4, #(1 << CP15_C1_DC)
+        bic     r4, r4, #(1 << CP15_C1_IC)
+        bic     r4, r4, #(1 << CP15_C1_BP)
+        mcr     p15, 0, r4, c1, c0, 0
 
-
-#ifndef PROCESSOR_ARCH_armv7_a
-        mrc     p15, 0, r4, c1, c0, 0
         
-        # D-cache before the kernel is started.
-        bic     r4, r4, #(1 << CP15_C1_DC)
-
-        # Disable I-cache and Branch predictors.
-        bic     r4, r4, #(1 << CP15_C1_IC)
-#ifdef PROCESSOR_ARCH_armv6
-        bic     r4, r4, #(1 << CP15_C1_BP)
-#endif
-        
-        mcr     p15, 0, r4, c1, c0, 0
-#endif
-        
-        # Wait for the operations to complete
+        #Wait for the operations to complete
 #ifdef PROCESSOR_ARCH_armv7_a
         dsb
 #else
-        # cp15 dsb, r4 is ignored (should be zero)
-        mov r4, #0
+        #cp15 dsb, r4 is ignored (should be zero)
         mcr p15, 0, r4, c7, c10, 4
 #endif
         
         # Clean ICache and BPredictors, r4 ignored (SBZ)
-        mov r4, #0
         mcr p15, 0, r4, c7, c5, 0
         nop
 
-        # Wait for the operations to complete
+        #Wait for the operations to complete
 #ifdef PROCESSOR_ARCH_armv7_a
         isb
         nop
-#elif defined(PROCESSOR_ARCH_armv6)
+#else
         # cp15 isb
         mcr p15, 0, r4, c7, c5, 4
@@ -104 +98 @@
 #endif
         mov pc, r0
-FUNCTION_END(jump_to_kernel)
-