Index: arch/mips/Makefile.inc
===================================================================
--- arch/mips/Makefile.inc	(revision 9060bd155ebb04d94b7cd551fd3413cf35cab490)
+++ arch/mips/Makefile.inc	(revision 24241cf473a552121fb672a727f4bb324465801e)
@@ -12,9 +12,7 @@
 BFD_ARCH=mips
 
-ASFLAGS=-mips3
-
-DEFS=-DARCH=$(ARCH) -DMACHINE=${MACHINE}
-CFLAGS=$(DEFS) -mno-abicalls -mips3 -G 0 -nostdlib -fno-builtin -O2 
-LFLAGS=-mips2 -M -no-check-sections
+DEFS=-DARCH=$(ARCH) -DMACHINE=${MACHINE} -DKERNEL_LOAD_ADDRESS=${KERNEL_LOAD_ADDRESS}
+CFLAGS=$(DEFS) -mno-abicalls -G 0 -nostdlib -fno-builtin -O2  -fno-zero-initialized-in-bss 
+LFLAGS=-M -N
 
 # It seems that on big endian either GCC or the simulators
@@ -23,26 +21,35 @@
 
 ifeq (${MACHINE},indy)
- CFLAGS += -EB -mmemcpy -DBIG_ENDIAN -DHAVE_FPU -DFPU_LAZY
- BFD = elf32-big
+ CFLAGS += -EB -mmemcpy -DBIG_ENDIAN -DHAVE_FPU -DFPU_LAZY -march=r4600
+ BFD = ecoff-bigmips
+ KERNEL_LOAD_ADDRESS = 0x88002000
 endif
 
 ifeq (${MACHINE},lgxemul)
- CFLAGS += -DHAVE_FPU -DFPU_LAZY
+ CFLAGS += -DHAVE_FPU -DFPU_LAZY -mips3
  BFD = ecoff-littlemips
+ KERNEL_LOAD_ADDRESS = 0x80010000
 endif
 
 ifeq (${MACHINE},bgxemul)
- CFLAGS += -EB -mmemcpy -DBIG_ENDIAN -DHAVE_FPU -DFPU_LAZY
+ CFLAGS += -EB -mmemcpy -DBIG_ENDIAN -DHAVE_FPU -DFPU_LAZY -mips3
  BFD = ecoff-bigmips
+ KERNEL_LOAD_ADDRESS = 0x80010000
 endif
 
+# MSIM needs lwl/swl patch & 4kc instruction patch to work
+# otherwise add -mmemcpy -mips3
 ifeq (${MACHINE},msim)
  BFD = binary
- CFLAGS += -msoft-float
+ CFLAGS += -msoft-float -march=4kc 
+ KERNEL_LOAD_ADDRESS = 0x80010000
 endif
 
+# SIMICS 4kc emulation is broken, although for instructions
+# that do not bother us
 ifeq (${MACHINE},simics)
  BFD = elf32-little
- CFLAGS += -msoft-float
+ CFLAGS += -msoft-float -mips3
+ KERNEL_LOAD_ADDRESS = 0x80010000
 endif
 
Index: arch/mips/_link.ld.in
===================================================================
--- arch/mips/_link.ld.in	(revision 9060bd155ebb04d94b7cd551fd3413cf35cab490)
+++ arch/mips/_link.ld.in	(revision 24241cf473a552121fb672a727f4bb324465801e)
@@ -16,5 +16,5 @@
 
 SECTIONS {
-	. = 0x80100000;
+	. = KERNEL_LOAD_ADDRESS;
 	.text : {
 		ktext_start = .;
@@ -30,10 +30,12 @@
 		LONG(kdata_end - kdata_start);
 		hardcoded_load_address = .;
-		LONG(0x80100000);
+		LONG(KERNEL_LOAD_ADDRESS);
+		*(.rodata*);
+		*(.sdata);
+		*(.reginfo);
 	}
 	_gp = . + 0x8000;
 	.lit8 : { *(.lit8) }
 	.lit4 : { *(.lit4) }
-	.sdata : { *(.sdata) }
 	.sbss : {
 		*(.sbss);
@@ -44,14 +46,16 @@
 		*(COMMON); 		/* global variables */
 	}
-	mysymtable : {
+
+	mysymtab : {
 		symbol_table = .;
-		*(symtab.*);            /* Symbol table, must be LAST symbol!*/
+		*(symtab.*);             /* Symbol table, must be LAST symbol!*/
 	}
 	kdata_end = .;
 
-	.mdebug : { *(.mdebug) }
-	.stab 0 : { *(.stab) }
-	.stabstr 0 : { *(.stabstr) }
-	.comment : { *(.comment) }
-	.note : { *(.note) }
+	/DISCARD/ : {
+	  *(.mdebug*);
+	  *(.pdr);
+	  *(.comment);
+	  *(.note);
+	}
 }
Index: arch/mips/boot/Makefile
===================================================================
--- arch/mips/boot/Makefile	(revision 9060bd155ebb04d94b7cd551fd3413cf35cab490)
+++ arch/mips/boot/Makefile	(revision 24241cf473a552121fb672a727f4bb324465801e)
@@ -14,5 +14,5 @@
 
 ASFLAGS=-mips2 -I../../../include
-LFLAGS=--oformat=binary -mips2 -e start -T _link.ld 
+LFLAGS=--oformat=binary -e start -T _link.ld 
 
 .S.o:
Index: arch/mips/boot/boot.S
===================================================================
--- arch/mips/boot/boot.S	(revision 9060bd155ebb04d94b7cd551fd3413cf35cab490)
+++ arch/mips/boot/boot.S	(revision 24241cf473a552121fb672a727f4bb324465801e)
@@ -34,4 +34,8 @@
 
 #include <arch/asm/boot.h>
+
+#ifndef KERNEL_LOAD_ADDRESS
+# define KERNEL_LOAD_ADDRESS 0x80010000
+#endif
 	
 .global start
Index: arch/mips/include/asm/boot.h
===================================================================
--- arch/mips/include/asm/boot.h	(revision 9060bd155ebb04d94b7cd551fd3413cf35cab490)
+++ arch/mips/include/asm/boot.h	(revision 24241cf473a552121fb672a727f4bb324465801e)
@@ -34,7 +34,3 @@
 #define TEMP_STACK_SIZE 0x100
 
-/* Kernel startup address */
-#define KERNEL_LOAD_ADDRESS 0x80100000
-
-
 #endif
Index: arch/mips/include/console.h
===================================================================
--- arch/mips/include/console.h	(revision 9060bd155ebb04d94b7cd551fd3413cf35cab490)
+++ arch/mips/include/console.h	(revision 24241cf473a552121fb672a727f4bb324465801e)
@@ -39,3 +39,6 @@
 void console_init(void);
 
+extern int bios_write(int fd, const char *buf, int size, int *cnt);
+
+
 #endif
Index: arch/mips/include/cp0.h
===================================================================
--- arch/mips/include/cp0.h	(revision 9060bd155ebb04d94b7cd551fd3413cf35cab490)
+++ arch/mips/include/cp0.h	(revision 24241cf473a552121fb672a727f4bb324465801e)
@@ -39,5 +39,7 @@
 #define cp0_status_fpu_bit              (1<<29)
 
-#define cp0_status_im7_shift		15
+#define cp0_status_im_shift		8
+#define cp0_status_im_mask              0xff00
+
 /*
  * Magic value for use in msim.
@@ -64,4 +66,8 @@
 }
 
+#define cp0_mask_all_int() cp0_status_write(cp0_status_read() & ~(cp0_status_im_mask))
+#define cp0_unmask_all_int() cp0_status_write(cp0_status_read() | cp0_status_im_mask)
+#define cp0_mask_int(it) cp0_status_write(cp0_status_read() & ~(1<<(cp0_status_im_shift+(it))))
+#define cp0_unmask_int(it) cp0_status_write(cp0_status_read() | (1<<(cp0_status_im_shift+(it))))
 
 
Index: arch/mips/include/interrupt.h
===================================================================
--- arch/mips/include/interrupt.h	(revision 9060bd155ebb04d94b7cd551fd3413cf35cab490)
+++ arch/mips/include/interrupt.h	(revision 24241cf473a552121fb672a727f4bb324465801e)
@@ -30,4 +30,6 @@
 #define __INTERRUPT_H__
 
+#define TIMER_INTERRUPT   7
+
 extern void interrupt(void);
 
Index: arch/mips/include/mm/memory_init.h
===================================================================
--- arch/mips/include/mm/memory_init.h	(revision 9060bd155ebb04d94b7cd551fd3413cf35cab490)
+++ arch/mips/include/mm/memory_init.h	(revision 24241cf473a552121fb672a727f4bb324465801e)
@@ -33,4 +33,5 @@
 
 #define get_memory_size()	CONFIG_MEMORY_SIZE
+//#define get_memory_size()	150*1024*1024
 
 #endif
Index: arch/mips/src/asm.S
===================================================================
--- arch/mips/src/asm.S	(revision 9060bd155ebb04d94b7cd551fd3413cf35cab490)
+++ arch/mips/src/asm.S	(revision 24241cf473a552121fb672a727f4bb324465801e)
@@ -118,4 +118,11 @@
 
 
+.global bios_write
+bios_write:
+	lw	$2, 0x80001020
+	lw	$2, 0x6c($2)
+	j	$2
+	nop
+	
 .global cpu_halt
 cpu_halt:
Index: arch/mips/src/console.c
===================================================================
--- arch/mips/src/console.c	(revision 9060bd155ebb04d94b7cd551fd3413cf35cab490)
+++ arch/mips/src/console.c	(revision 24241cf473a552121fb672a727f4bb324465801e)
@@ -31,4 +31,17 @@
 #include <arch/cp0.h>
 #include <arch/console.h>
+#include <arch.h>
+
+static void arc_putchar(const char ch)
+{
+	int cnt;
+	pri_t pri;
+
+	/* TODO: Should be spinlock? */
+	pri = cpu_priority_high();
+	bios_write(1, &ch, 1, &cnt);
+	cpu_priority_restore(pri);
+	
+}
 
 static void cons_putchar(const char ch)
Index: arch/mips/src/cpu/cpu.c
===================================================================
--- arch/mips/src/cpu/cpu.c	(revision 9060bd155ebb04d94b7cd551fd3413cf35cab490)
+++ arch/mips/src/cpu/cpu.c	(revision 24241cf473a552121fb672a727f4bb324465801e)
@@ -78,5 +78,6 @@
 	{ "Sony", "R3000" },		/* 0x21 */
 	{ "Toshiba", "R3000" },		/* 0x22 */
-	{ "NKK", "R3000" }		/* 0x23 */
+	{ "NKK", "R3000" },		/* 0x23 */
+	{ NULL, NULL }
 };
 
@@ -85,5 +86,6 @@
 	{"Invalid","Invalid"}, /* 0x81 */
 	{"Invalid","Invalid"}, /* 0x82 */
-	{"MIPS","4Km & 4Kp"} /* 0x83 */
+	{"MIPS","4Km & 4Kp"}, /* 0x83 */
+	{ NULL, NULL}
 };
 
@@ -101,9 +103,24 @@
 {
 	struct data_t *data;
+	int i;
 
 	if (m->arch.imp_num & 0x80) {
+		/* Count records */
+		for (i=0;imp_data80[i].vendor;i++)
+			;
+		if (m->arch.imp_num & 0x7f >= i) {
+			printf("imp=%d\n",m->arch.imp_num);
+			return;
+		}
 		data = &imp_data80[m->arch.imp_num & 0x7f];
-	} else
+	} else {
+		for (i=0;imp_data[i].vendor;i++)
+			;
+		if (m->arch.imp_num >= i) {
+			printf("imp=%d\n",m->arch.imp_num);
+			return;
+		}
 		data = &imp_data[m->arch.imp_num];
+	}
 
 	printf("cpu%d: %s %s (rev=%d.%d, imp=%d)\n",
Index: arch/mips/src/interrupt.c
===================================================================
--- arch/mips/src/interrupt.c	(revision 9060bd155ebb04d94b7cd551fd3413cf35cab490)
+++ arch/mips/src/interrupt.c	(revision 24241cf473a552121fb672a727f4bb324465801e)
@@ -82,7 +82,7 @@
 					panic("unhandled interrupt %d\n", i);
 					break;
-				case 7: /* Timer Interrupt */
-					cp0_compare_write(cp0_count_read() + cp0_compare_value); /* clear timer interrupt */
-					/* start counting over again */
+				case TIMER_INTERRUPT:
+					/* clear timer interrupt & set new */
+					cp0_compare_write(cp0_count_read() + cp0_compare_value); 
 					clock();
 					break;
Index: arch/mips/src/mips.c
===================================================================
--- arch/mips/src/mips.c	(revision 9060bd155ebb04d94b7cd551fd3413cf35cab490)
+++ arch/mips/src/mips.c	(revision 24241cf473a552121fb672a727f4bb324465801e)
@@ -36,4 +36,5 @@
 #include <arch/console.h>
 #include <memstr.h>
+#include <arch/interrupt.h>
 
 /* Size of the code jumping to the exception handler code 
@@ -48,11 +49,14 @@
 #include <arch/debug.h>
 
+#include <print.h>
 void arch_pre_mm_init(void)
 {
+	/* It is not assumed by default */
+	cpu_priority_high();
+
 	/* Copy the exception vectors to the right places */
 	memcpy(TLB_EXC, (char *)tlb_refill_entry, EXCEPTION_JUMP_SIZE);
 	memcpy(NORM_EXC, (char *)exception_entry, EXCEPTION_JUMP_SIZE);
 	memcpy(CACHE_EXC, (char *)cache_error_entry, EXCEPTION_JUMP_SIZE);
-
 
 	/*
@@ -62,8 +66,12 @@
 	cp0_status_write(cp0_status_read() & ~(cp0_status_bev_bootstrap_bit|cp0_status_erl_error_bit));
 
+	/* 
+	 * Mask all interrupts 
+	 */
+	cp0_mask_all_int();
 	/*
 	 * Unmask hardware clock interrupt.
 	 */
-	cp0_status_write(cp0_status_read() | (1<<cp0_status_im7_shift));
+	cp0_unmask_int(TIMER_INTERRUPT);
 
 	/*
Index: arch/mips/src/mm/frame.c
===================================================================
--- arch/mips/src/mm/frame.c	(revision 9060bd155ebb04d94b7cd551fd3413cf35cab490)
+++ arch/mips/src/mm/frame.c	(revision 24241cf473a552121fb672a727f4bb324465801e)
@@ -29,8 +29,10 @@
 #include <arch/mm/frame.h>
 #include <mm/frame.h>
+#include <arch/asm/boot.h>
+#include <arch/mm/page.h>
 
 void frame_arch_init(void)
 {
-	/* Disable first megabyte (God knows why) */
-	frame_region_not_free(0, 1024*1024);
+	/* Disable Everything until load address */
+	frame_region_not_free(0, KA2PA(KERNEL_LOAD_ADDRESS));
 }
Index: test/fpu/mips1/test.c
===================================================================
--- test/fpu/mips1/test.c	(revision 9060bd155ebb04d94b7cd551fd3413cf35cab490)
+++ test/fpu/mips1/test.c	(revision 24241cf473a552121fb672a727f4bb324465801e)
@@ -87,5 +87,5 @@
 	for (i = 0; i<ATTEMPTS; i++) {
 		__asm__ volatile (
-			"ctc1 %0,$1"
+			"mtc1 %0,$1"
 			:"=r"(arg)
 			);
@@ -93,10 +93,10 @@
 		scheduler();
 		__asm__ volatile (
-			"cfc1 %0,$1"
+			"mfc1 %0,$1"
 			:"=r"(after_arg)
 			);
 		
 		if(arg != after_arg)
-			panic("Control reg tid%d: arg(%d) != %d\n", 
+			panic("General reg tid%d: arg(%d) != %d\n", 
 			      THREAD->tid, arg, after_arg);
 	}