Changeset 235d31d in mainline for kernel/arch/sparc64/include


Ignore:
Timestamp:
2014-12-22T17:47:40Z (11 years ago)
Author:
Jakub Jermar <jakub@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
8c7d5ad
Parents:
eae91e0 (diff), 759ea0d (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the (diff) links above to see all the changes relative to each parent.
Message:

Merge the CHT pre-integration branch

This branch contains:

  • the merge of lp:~adam-hraska+lp/helenos/rcu, which brings:
  • a new preemptible kernel RCU variant called A-RCU,
  • a preemptible variant of Podzimek's non-preemptible kernel RCU and
  • a new variant of usersace RCU,
  • a new concurrent hash table (CHT) implementation based on RCU,
  • a deployment of CHT in kernel futex handling,
  • a deployment of the userspace RCU in the implementation of upgradable futexes,

all described in Adam Hraska's master thesis named Read-Copy-Update
for HelenOS, defended in 2013 at MFF UK; furthemore, the branch
fixes two synchronization bugs in condvars and waitq, respectively:

  • revid:adam.hraska+hos@gmail.com-20121116144921-3to9u1tn1sg07rg7
  • revid:adam.hraska+hos@gmail.com-20121116173623-km7gwtqixwudpe66
  • build fixes required to pass make check
  • overhaul of ia64 and sparc64 trap handling, to allow exc_dispatch() to be used now when the kernel is more picky about CPU state accounting
  • an important fix of the sparc64/sun4v preemptible trap handler
  • various other fixes of issues discovered on non-x86 architectures
Location:
kernel/arch/sparc64/include/arch
Files:
1 added
12 edited

Legend:

Unmodified
Added
Removed

  • kernel/arch/sparc64/include/arch/barrier.h

    reae91e0 r235d31d  
    3737
    3838#include <trace.h>
     39
     40#ifdef KERNEL
     41#include <arch/common.h>
     42#else
     43#include <libarch/common.h>
     44#endif
    3945
    4046/*

  • kernel/arch/sparc64/include/arch/interrupt.h

    reae91e0 r235d31d  
    4040#include <arch/istate.h>
    4141
    42 #define IVT_ITEMS  15
    43 #define IVT_FIRST  1
     42#define IVT_ITEMS  512
     43#define IVT_FIRST  0
    4444
    4545/* This needs to be defined for inter-architecture API portability. */
    … …  
    4747
    4848enum {
    49         IPI_TLB_SHOOTDOWN = VECTOR_TLB_SHOOTDOWN_IPI
     49        IPI_TLB_SHOOTDOWN = VECTOR_TLB_SHOOTDOWN_IPI,
     50        IPI_SMP_CALL
    5051};
     52
     53extern void exc_arch_init(void);
    5154
    5255#endif

  • kernel/arch/sparc64/include/arch/istate_struct.ag

    reae91e0 r235d31d  
    4141
    4242        members : [
     43
     44                #
     45                # Window save area for locals and inputs. Required by ABI.
     46                # Before using these, make sure that the corresponding register
     47                # window has been spilled into memory, otherwise l0-l7 and
     48                # i0-i7 will have undefined values.
     49                #
     50                {
     51                        name : l0,
     52                        type : uint64_t,
     53                },
     54                {
     55                        name : l1,
     56                        type : uint64_t,
     57                },
     58                {
     59                        name : l2,
     60                        type : uint64_t,
     61                },
     62                {
     63                        name : l3,
     64                        type : uint64_t,
     65                },
     66                {
     67                        name : l4,
     68                        type : uint64_t,
     69                },
     70                {
     71                        name : l5,
     72                        type : uint64_t,
     73                },
     74                {
     75                        name : l6,
     76                        type : uint64_t,
     77                },
     78                {
     79                        name : l7,
     80                        type : uint64_t,
     81                },
     82                {
     83                        name : i0,
     84                        type : uint64_t,
     85                },
     86                {
     87                        name : i1,
     88                        type : uint64_t,
     89                },
     90                {
     91                        name : i2,
     92                        type : uint64_t,
     93                },
     94                {
     95                        name : i3,
     96                        type : uint64_t,
     97                },
     98                {
     99                        name : i4,
     100                        type : uint64_t,
     101                },
     102                {
     103                        name : i5,
     104                        type : uint64_t,
     105                },
     106                {
     107                        name : i6,
     108                        type : uint64_t,
     109                },
     110                {
     111                        name : i7,
     112                        type : uint64_t,
     113                },
     114
     115                #
     116                # Six mandatory argument slots, required by the ABI, plus an
     117                # optional argument slot for the 7th argument used by our
     118                # syscalls. Since the preemptible handler is always passing
     119                # integral arguments, undef_arg[0] - undef_arg[5] are always
     120                # undefined.
     121                #
     122                {
     123                        name : undef_arg,
     124                        type : uint64_t,
     125                        elements : 6,
     126                },
     127                {
     128                        name : arg6,
     129                        type : uint64_t,
     130                },
     131
     132                #
     133                # From this point onwards, the istate layout is not dicated by
     134                # the ABI. The only requirement is the stack alignment.
     135                #
     136
    43137                {
    44138                        name : tnpc,
    … …  
    51145                {
    52146                        name : tstate,
     147                        type : uint64_t
     148                },
     149                {
     150                        name : y,
     151                        type : uint64_t,
     152                },
     153
     154                #
     155                # At the moment, these are defined only when needed by the
     156                # preemptible handler, so consider them undefined for now.
     157                #
     158                {
     159                        name : o0,
     160                        type : uint64_t,
     161                },
     162                {
     163                        name : o1,
     164                        type : uint64_t,
     165                },
     166                {
     167                        name : o2,
     168                        type : uint64_t,
     169                },
     170                {
     171                        name : o3,
     172                        type : uint64_t,
     173                },
     174                {
     175                        name : o4,
     176                        type : uint64_t,
     177                },
     178                {
     179                        name : o5,
     180                        type : uint64_t,
     181                },
     182                {
     183                        name : o6,
     184                        type : uint64_t,
     185                },
     186                {
     187                        name : o7,
     188                        type : uint64_t,
     189                },
     190
     191                #
     192                # I/DTLB Tag Access register or zero for non-MMU traps.
     193                #
     194                {
     195                        name : tlb_tag_access,
    53196                        type : uint64_t
    54197                }

  • kernel/arch/sparc64/include/arch/mm/sun4u/tlb.h

    reae91e0 r235d31d  
    678678}
    679679
    680 extern void fast_instruction_access_mmu_miss(sysarg_t, istate_t *);
    681 extern void fast_data_access_mmu_miss(tlb_tag_access_reg_t, istate_t *);
    682 extern void fast_data_access_protection(tlb_tag_access_reg_t , istate_t *);
     680extern void fast_instruction_access_mmu_miss(unsigned int, istate_t *);
     681extern void fast_data_access_mmu_miss(unsigned int, istate_t *);
     682extern void fast_data_access_protection(unsigned int, istate_t *);
    683683
    684684extern void dtlb_insert_mapping(uintptr_t, uintptr_t, int, bool, bool);

  • kernel/arch/sparc64/include/arch/mm/sun4v/tlb.h

    reae91e0 r235d31d  
    141141}
    142142
    143 extern void fast_instruction_access_mmu_miss(sysarg_t, istate_t *);
    144 extern void fast_data_access_mmu_miss(sysarg_t, istate_t *);
    145 extern void fast_data_access_protection(sysarg_t, istate_t *);
     143extern void fast_instruction_access_mmu_miss(unsigned int, istate_t *);
     144extern void fast_data_access_mmu_miss(unsigned int, istate_t *);
     145extern void fast_data_access_protection(unsigned int, istate_t *);
    146146
    147147extern void dtlb_insert_mapping(uintptr_t, uintptr_t, int, bool, bool);

  • kernel/arch/sparc64/include/arch/trap/exception.h

    reae91e0 r235d31d  
    7171extern void dump_istate(istate_t *istate);
    7272
    73 extern void instruction_access_exception(int n, istate_t *istate);
    74 extern void instruction_access_error(int n, istate_t *istate);
    75 extern void illegal_instruction(int n, istate_t *istate);
    76 extern void privileged_opcode(int n, istate_t *istate);
    77 extern void unimplemented_LDD(int n, istate_t *istate);
    78 extern void unimplemented_STD(int n, istate_t *istate);
    79 extern void fp_disabled(int n, istate_t *istate);
    80 extern void fp_exception_ieee_754(int n, istate_t *istate);
    81 extern void fp_exception_other(int n, istate_t *istate);
    82 extern void tag_overflow(int n, istate_t *istate);
    83 extern void division_by_zero(int n, istate_t *istate);
    84 extern void data_access_exception(int n, istate_t *istate);
    85 extern void data_access_error(int n, istate_t *istate);
    86 extern void mem_address_not_aligned(int n, istate_t *istate);
    87 extern void LDDF_mem_address_not_aligned(int n, istate_t *istate);
    88 extern void STDF_mem_address_not_aligned(int n, istate_t *istate);
    89 extern void privileged_action(int n, istate_t *istate);
    90 extern void LDQF_mem_address_not_aligned(int n, istate_t *istate);
    91 extern void STQF_mem_address_not_aligned(int n, istate_t *istate);
     73extern void instruction_access_exception(unsigned int, istate_t *);
     74extern void instruction_access_error(unsigned int, istate_t *);
     75extern void illegal_instruction(unsigned int, istate_t *);
     76extern void privileged_opcode(unsigned int, istate_t *);
     77extern void unimplemented_LDD(unsigned int, istate_t *);
     78extern void unimplemented_STD(unsigned int, istate_t *);
     79extern void fp_disabled(unsigned int, istate_t *);
     80extern void fp_exception_ieee_754(unsigned int, istate_t *);
     81extern void fp_exception_other(unsigned int, istate_t *);
     82extern void tag_overflow(unsigned int, istate_t *);
     83extern void division_by_zero(unsigned int, istate_t *);
     84extern void data_access_exception(unsigned int, istate_t *);
     85extern void data_access_error(unsigned int, istate_t *);
     86extern void mem_address_not_aligned(unsigned int, istate_t *);
     87extern void LDDF_mem_address_not_aligned(unsigned int, istate_t *);
     88extern void STDF_mem_address_not_aligned(unsigned int, istate_t *);
     89extern void privileged_action(unsigned int, istate_t *);
     90extern void LDQF_mem_address_not_aligned(unsigned int, istate_t *);
     91extern void STQF_mem_address_not_aligned(unsigned int, istate_t *);
    9292
    9393#endif /* !__ASM__ */

  • kernel/arch/sparc64/include/arch/trap/interrupt.h

    reae91e0 r235d31d  
    6363#define IGN_SHIFT       6
    6464
    65 
    66 #ifdef __ASM__
    67 .macro INTERRUPT_LEVEL_N_HANDLER n
    68         mov \n - 1, %g2
    69         PREEMPTIBLE_HANDLER exc_dispatch
    70 .endm
    71 #endif
    72 
    7365#ifndef __ASM__
    7466
    7567#include <arch/interrupt.h>
    7668
    77 extern void interrupt(int n, istate_t *istate);
     69extern void interrupt(unsigned int n, istate_t *istate);
     70
    7871#endif /* !def __ASM__ */
    7972

  • kernel/arch/sparc64/include/arch/trap/sun4u/interrupt.h

    reae91e0 r235d31d  
    9292#define INTERRUPT_VECTOR_TRAP_HANDLER_SIZE      TRAP_TABLE_ENTRY_SIZE
    9393
    94 #ifdef __ASM__
    95 .macro INTERRUPT_VECTOR_TRAP_HANDLER
    96         PREEMPTIBLE_HANDLER interrupt
    97 .endm
    98 #endif /* __ASM__ */
    99 
    100 
    10194#endif
    10295

  • kernel/arch/sparc64/include/arch/trap/sun4u/mmu.h

    reae91e0 r235d31d  
    74740:
    7575        wrpr %g0, PSTATE_PRIV_BIT | PSTATE_AG_BIT, %pstate
    76         PREEMPTIBLE_HANDLER fast_instruction_access_mmu_miss
     76        mov TT_FAST_INSTRUCTION_ACCESS_MMU_MISS, %g2
     77        mov VA_IMMU_TAG_ACCESS, %g5
     78        ldxa [%g5] ASI_IMMU, %g5                        ! read the faulting Context and VPN
     79        PREEMPTIBLE_HANDLER exc_dispatch
    7780.endm
    7881
    … …  
    107110        wr %g0, ASI_DMMU, %asi
    108111        ldxa [VA_DMMU_TAG_ACCESS] %asi, %g1             ! read the faulting Context and VPN
    109         set TLB_TAG_ACCESS_CONTEXT_MASK, %g2
     112        ldx [%g7 + %lo(tlb_tag_access_context_mask)], %g2
    110113        andcc %g1, %g2, %g3                             ! get Context
    111114        bnz %xcc, 0f                                    ! Context is non-zero
    … …  
    138141        wrpr %g0, PSTATE_PRIV_BIT | PSTATE_AG_BIT, %pstate
    139142
    140         /*
    141          * Read the Tag Access register for the higher-level handler.
    142          * This is necessary to survive nested DTLB misses.
    143          */     
    144         ldxa [VA_DMMU_TAG_ACCESS] %asi, %g2
    145 
    146         /*
    147          * g2 will be passed as an argument to fast_data_access_mmu_miss().
    148          */
    149         PREEMPTIBLE_HANDLER fast_data_access_mmu_miss
     143        mov TT_FAST_DATA_ACCESS_MMU_MISS, %g2
     144        ldxa [VA_DMMU_TAG_ACCESS] %asi, %g5             ! read the faulting Context and VPN
     145        PREEMPTIBLE_HANDLER exc_dispatch
    150146.endm
    151147
    … …  
    164160        wrpr %g0, PSTATE_PRIV_BIT | PSTATE_AG_BIT, %pstate
    165161
    166         /*
    167          * Read the Tag Access register for the higher-level handler.
    168          * This is necessary to survive nested DTLB misses.
    169          */     
    170         mov VA_DMMU_TAG_ACCESS, %g2
    171         ldxa [%g2] ASI_DMMU, %g2
    172 
    173         /*
    174          * g2 will be passed as an argument to fast_data_access_mmu_miss().
    175          */
    176         PREEMPTIBLE_HANDLER fast_data_access_protection
     162        mov TT_FAST_DATA_ACCESS_PROTECTION, %g2
     163        mov VA_DMMU_TAG_ACCESS, %g5
     164        ldxa [%g5] ASI_DMMU, %g5                        ! read the faulting Context and VPN
     165        PREEMPTIBLE_HANDLER exc_dispatch
    177166.endm
    178167

  • kernel/arch/sparc64/include/arch/trap/sun4v/interrupt.h

    reae91e0 r235d31d  
    4040#ifndef __ASM__
    4141
     42#include <arch/istate_struct.h>
     43
    4244extern void sun4v_ipi_init(void);
    43 extern void cpu_mondo(void);
     45extern void cpu_mondo(unsigned int, istate_t *);
    4446
    4547#endif

  • kernel/arch/sparc64/include/arch/trap/sun4v/mmu.h

    reae91e0 r235d31d  
    7373
    7474.macro FAST_INSTRUCTION_ACCESS_MMU_MISS_HANDLER
    75         PREEMPTIBLE_HANDLER fast_instruction_access_mmu_miss
     75        mov TT_FAST_INSTRUCTION_ACCESS_MMU_MISS, %g2
     76        clr %g5         ! XXX
     77        PREEMPTIBLE_HANDLER exc_dispatch
    7678.endm
    7779
    … …  
    123125         * mapped. In such a case, this handler will be called from TL = 1.
    124126         * We handle the situation by pretending that the MMU miss occurred
    125          * on TL = 0. Once the MMU miss trap is services, the instruction which
     127         * on TL = 0. Once the MMU miss trap is serviced, the instruction which
    126128         * caused the spill/fill trap is restarted, the spill/fill trap occurs,
    127          * but this time its handler accesse memory which IS mapped.
     129         * but this time its handler accesses memory which is mapped.
    128130         */
    129131        .if (\tl > 0)
    … …  
    131133        .endif
    132134
     135        mov TT_FAST_DATA_ACCESS_MMU_MISS, %g2
     136
    133137        /*
    134          * Save the faulting virtual page and faulting context to the %g2
    135          * register. The most significant 51 bits of the %g2 register will
     138         * Save the faulting virtual page and faulting context to the %g5
     139         * register. The most significant 51 bits of the %g5 register will
    136140         * contain the virtual address which caused the fault truncated to the
    137          * page boundary. The least significant 13 bits of the %g2 register
     141         * page boundary. The least significant 13 bits of the %g5 register
    138142         * will contain the number of the context in which the fault occurred.
    139          * The value of the %g2 register will be passed as a parameter to the
    140          * higher level service routine.
     143         * The value of the %g5 register will be stored in the istate structure
     144         * for inspeciton by the higher level service routine.
    141145         */
    142         or %g1, %g3, %g2
     146        or %g1, %g3, %g5
    143147
    144         PREEMPTIBLE_HANDLER fast_data_access_mmu_miss
     148        PREEMPTIBLE_HANDLER exc_dispatch
    145149.endm
    146150
    … …  
    170174        sllx %g1, TTE_DATA_TADDR_OFFSET, %g1
    171175
     176        mov TT_FAST_DATA_ACCESS_PROTECTION, %g2
     177
    172178        /* the same as for FAST_DATA_ACCESS_MMU_MISS_HANDLER */
    173         or %g1, %g3, %g2
     179        or %g1, %g3, %g5
    174180
    175         PREEMPTIBLE_HANDLER fast_data_access_protection
     181        PREEMPTIBLE_HANDLER exc_dispatch
    176182.endm
    177183#endif /* __ASM__ */

  • kernel/arch/sparc64/include/arch/trap/trap_table.h

    reae91e0 r235d31d  
    4343#define TRAP_TABLE_SIZE         (TRAP_TABLE_ENTRY_COUNT * TRAP_TABLE_ENTRY_SIZE)
    4444
    45 #define ISTATE_END_OFFSET(o)    ((o) - ISTATE_SIZE)
    46 
    47 /*
    48  * The one STACK_ITEM_SIZE is counted for space holding the 7th
    49  * argument to syscall_handler (i.e. syscall number) and the other
    50  * STACK_ITEM_SIZE is counted because of the required alignment.
    51  */
    52 #define PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE \
    53     (STACK_WINDOW_SAVE_AREA_SIZE + STACK_ARG_SAVE_AREA_SIZE + \
    54     (2 * STACK_ITEM_SIZE) + (ISTATE_SIZE + 9 * 8))
    55 /* <-- istate_t ends here */
    56 #define SAVED_TSTATE    ISTATE_END_OFFSET(ISTATE_OFFSET_TSTATE)
    57 #define SAVED_TPC       ISTATE_END_OFFSET(ISTATE_OFFSET_TPC)
    58 #define SAVED_TNPC      ISTATE_END_OFFSET(ISTATE_OFFSET_TNPC)
    59 /* <-- istate_t begins here */
    60 #define SAVED_Y         -(1 * 8 + ISTATE_SIZE)
    61 #define SAVED_I0        -(2 * 8 + ISTATE_SIZE)
    62 #define SAVED_I1        -(3 * 8 + ISTATE_SIZE)
    63 #define SAVED_I2        -(4 * 8 + ISTATE_SIZE)
    64 #define SAVED_I3        -(5 * 8 + ISTATE_SIZE)
    65 #define SAVED_I4        -(6 * 8 + ISTATE_SIZE)
    66 #define SAVED_I5        -(7 * 8 + ISTATE_SIZE)
    67 #define SAVED_I6        -(8 * 8 + ISTATE_SIZE)
    68 #define SAVED_I7        -(9 * 8 + ISTATE_SIZE)
    69 
    7045#ifndef __ASM__
    7146
    … …  
    8055extern trap_table_entry_t trap_table[TRAP_TABLE_ENTRY_COUNT];
    8156extern trap_table_entry_t trap_table_save[TRAP_TABLE_ENTRY_COUNT];
     57
    8258#endif /* !__ASM__ */
    8359
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