Index: kernel/arch/abs32le/include/arch/asm.h
===================================================================
--- kernel/arch/abs32le/include/arch/asm.h	(revision fd57745cd4811832fa23ba1cef7638038244f2b5)
+++ kernel/arch/abs32le/include/arch/asm.h	(revision 231c770580f4400a6e0e7612723b1efb16fd5390)
@@ -51,5 +51,6 @@
 	   this function. */
 
-	while (true);
+	while (true)
+		;
 }
 
Index: kernel/arch/abs32le/include/arch/atomic.h
===================================================================
--- kernel/arch/abs32le/include/arch/atomic.h	(revision fd57745cd4811832fa23ba1cef7638038244f2b5)
+++ kernel/arch/abs32le/include/arch/atomic.h	(revision 231c770580f4400a6e0e7612723b1efb16fd5390)
@@ -115,5 +115,6 @@
 {
 	do {
-		while (val->count);
+		while (val->count)
+			;
 	} while (test_and_set(val));
 }
Index: kernel/arch/abs32le/src/abs32le.c
===================================================================
--- kernel/arch/abs32le/src/abs32le.c	(revision fd57745cd4811832fa23ba1cef7638038244f2b5)
+++ kernel/arch/abs32le/src/abs32le.c	(revision 231c770580f4400a6e0e7612723b1efb16fd5390)
@@ -110,5 +110,6 @@
 void context_restore_arch(context_t *ctx)
 {
-	while (true);
+	while (true)
+		;
 }
 
Index: kernel/arch/abs32le/src/userspace.c
===================================================================
--- kernel/arch/abs32le/src/userspace.c	(revision fd57745cd4811832fa23ba1cef7638038244f2b5)
+++ kernel/arch/abs32le/src/userspace.c	(revision 231c770580f4400a6e0e7612723b1efb16fd5390)
@@ -44,5 +44,6 @@
 	   space mode and jumps to kernel_uarg->uspace_entry. */
 
-	while (true);
+	while (true)
+		;
 }
 
Index: kernel/arch/amd64/include/arch/atomic.h
===================================================================
--- kernel/arch/amd64/include/arch/atomic.h	(revision fd57745cd4811832fa23ba1cef7638038244f2b5)
+++ kernel/arch/amd64/include/arch/atomic.h	(revision 231c770580f4400a6e0e7612723b1efb16fd5390)
@@ -45,11 +45,11 @@
 #ifdef CONFIG_SMP
 	asm volatile (
-		"lock incq %[count]\n"
-		: [count] "+m" (val->count)
-	);
-#else
-	asm volatile (
-		"incq %[count]\n"
-		: [count] "+m" (val->count)
+	    "lock incq %[count]\n"
+	    : [count] "+m" (val->count)
+	);
+#else
+	asm volatile (
+	    "incq %[count]\n"
+	    : [count] "+m" (val->count)
 	);
 #endif /* CONFIG_SMP */
@@ -60,11 +60,11 @@
 #ifdef CONFIG_SMP
 	asm volatile (
-		"lock decq %[count]\n"
-		: [count] "+m" (val->count)
-	);
-#else
-	asm volatile (
-		"decq %[count]\n"
-		: [count] "+m" (val->count)
+	    "lock decq %[count]\n"
+	    : [count] "+m" (val->count)
+	);
+#else
+	asm volatile (
+	    "decq %[count]\n"
+	    : [count] "+m" (val->count)
 	);
 #endif /* CONFIG_SMP */
@@ -76,7 +76,7 @@
 
 	asm volatile (
-		"lock xaddq %[r], %[count]\n"
-		: [count] "+m" (val->count),
-		  [r] "+r" (r)
+	    "lock xaddq %[r], %[count]\n"
+	    : [count] "+m" (val->count),
+	      [r] "+r" (r)
 	);
 
@@ -89,7 +89,7 @@
 
 	asm volatile (
-		"lock xaddq %[r], %[count]\n"
-		: [count] "+m" (val->count),
-		  [r] "+r" (r)
+	    "lock xaddq %[r], %[count]\n"
+	    : [count] "+m" (val->count),
+	      [r] "+r" (r)
 	);
 
@@ -105,7 +105,7 @@
 
 	asm volatile (
-		"xchgq %[v], %[count]\n"
-		: [v] "+r" (v),
-		  [count] "+m" (val->count)
+	    "xchgq %[v], %[count]\n"
+	    : [v] "+r" (v),
+	      [count] "+m" (val->count)
 	);
 
@@ -120,16 +120,16 @@
 	preemption_disable();
 	asm volatile (
-		"0:\n"
-		"	pause\n"
-		"	mov %[count], %[tmp]\n"
-		"	testq %[tmp], %[tmp]\n"
-		"	jnz 0b\n"       /* lightweight looping on locked spinlock */
-
-		"	incq %[tmp]\n"  /* now use the atomic operation */
-		"	xchgq %[count], %[tmp]\n"
-		"	testq %[tmp], %[tmp]\n"
-		"	jnz 0b\n"
-		: [count] "+m" (val->count),
-		  [tmp] "=&r" (tmp)
+	    "0:\n"
+	    "	pause\n"
+	    "	mov %[count], %[tmp]\n"
+	    "	testq %[tmp], %[tmp]\n"
+	    "	jnz 0b\n"       /* lightweight looping on locked spinlock */
+
+	    "	incq %[tmp]\n"  /* now use the atomic operation */
+	    "	xchgq %[count], %[tmp]\n"
+	    "	testq %[tmp], %[tmp]\n"
+	    "	jnz 0b\n"
+	    : [count] "+m" (val->count),
+	      [tmp] "=&r" (tmp)
 	);
 
Index: kernel/arch/amd64/include/arch/cpuid.h
===================================================================
--- kernel/arch/amd64/include/arch/cpuid.h	(revision fd57745cd4811832fa23ba1cef7638038244f2b5)
+++ kernel/arch/amd64/include/arch/cpuid.h	(revision 231c770580f4400a6e0e7612723b1efb16fd5390)
@@ -55,5 +55,5 @@
 	uint32_t cpuid_ecx;
 	uint32_t cpuid_edx;
-} __attribute__ ((packed)) cpu_info_t;
+} __attribute__((packed)) cpu_info_t;
 
 extern int has_cpuid(void);
Index: kernel/arch/amd64/include/arch/cycle.h
===================================================================
--- kernel/arch/amd64/include/arch/cycle.h	(revision fd57745cd4811832fa23ba1cef7638038244f2b5)
+++ kernel/arch/amd64/include/arch/cycle.h	(revision 231c770580f4400a6e0e7612723b1efb16fd5390)
@@ -44,7 +44,7 @@
 
 	asm volatile (
-		"rdtsc\n"
-		: "=a" (lower),
-		  "=d" (upper)
+	    "rdtsc\n"
+	    : "=a" (lower),
+	      "=d" (upper)
 	);
 
Index: kernel/arch/amd64/include/arch/mm/page.h
===================================================================
--- kernel/arch/amd64/include/arch/mm/page.h	(revision fd57745cd4811832fa23ba1cef7638038244f2b5)
+++ kernel/arch/amd64/include/arch/mm/page.h	(revision 231c770580f4400a6e0e7612723b1efb16fd5390)
@@ -198,5 +198,5 @@
 	unsigned int accessed : 1;
 	unsigned int dirty : 1;
-	unsigned int unused: 1;
+	unsigned int unused : 1;
 	unsigned int global : 1;
 	unsigned int soft_valid : 1;  /**< Valid content even if present bit is cleared. */
@@ -205,5 +205,5 @@
 	unsigned int addr_32_51 : 21;
 	unsigned int no_execute : 1;
-} __attribute__ ((packed)) pte_t;
+} __attribute__((packed)) pte_t;
 
 NO_TRACE static inline unsigned int get_pt_flags(pte_t *pt, size_t i)
Index: kernel/arch/amd64/include/arch/pm.h
===================================================================
--- kernel/arch/amd64/include/arch/pm.h	(revision fd57745cd4811832fa23ba1cef7638038244f2b5)
+++ kernel/arch/amd64/include/arch/pm.h	(revision 231c770580f4400a6e0e7612723b1efb16fd5390)
@@ -37,6 +37,6 @@
 
 #ifndef __ASSEMBLER__
-	#include <typedefs.h>
-	#include <arch/context.h>
+#include <typedefs.h>
+#include <arch/context.h>
 #endif
 
@@ -91,55 +91,55 @@
 
 typedef struct {
-	unsigned limit_0_15: 16;
-	unsigned base_0_15: 16;
-	unsigned base_16_23: 8;
-	unsigned access: 8;
-	unsigned limit_16_19: 4;
-	unsigned available: 1;
-	unsigned longmode: 1;
-	unsigned special: 1;
+	unsigned limit_0_15 : 16;
+	unsigned base_0_15 : 16;
+	unsigned base_16_23 : 8;
+	unsigned access : 8;
+	unsigned limit_16_19 : 4;
+	unsigned available : 1;
+	unsigned longmode : 1;
+	unsigned special : 1;
 	unsigned granularity : 1;
-	unsigned base_24_31: 8;
-} __attribute__ ((packed)) descriptor_t;
+	unsigned base_24_31 : 8;
+} __attribute__((packed)) descriptor_t;
 
 typedef struct {
-	unsigned limit_0_15: 16;
-	unsigned base_0_15: 16;
-	unsigned base_16_23: 8;
-	unsigned type: 4;
+	unsigned limit_0_15 : 16;
+	unsigned base_0_15 : 16;
+	unsigned base_16_23 : 8;
+	unsigned type : 4;
 	unsigned : 1;
 	unsigned dpl : 2;
 	unsigned present : 1;
-	unsigned limit_16_19: 4;
-	unsigned available: 1;
+	unsigned limit_16_19 : 4;
+	unsigned available : 1;
 	unsigned : 2;
 	unsigned granularity : 1;
-	unsigned base_24_31: 8;
+	unsigned base_24_31 : 8;
 	unsigned base_32_63 : 32;
 	unsigned  : 32;
-} __attribute__ ((packed)) tss_descriptor_t;
+} __attribute__((packed)) tss_descriptor_t;
 
 typedef struct {
-	unsigned offset_0_15: 16;
-	unsigned selector: 16;
-	unsigned ist:3;
-	unsigned unused: 5;
-	unsigned type: 5;
-	unsigned dpl: 2;
+	unsigned offset_0_15 : 16;
+	unsigned selector : 16;
+	unsigned ist : 3;
+	unsigned unused : 5;
+	unsigned type : 5;
+	unsigned dpl : 2;
 	unsigned present : 1;
-	unsigned offset_16_31: 16;
-	unsigned offset_32_63: 32;
+	unsigned offset_16_31 : 16;
+	unsigned offset_32_63 : 32;
 	unsigned  : 32;
-} __attribute__ ((packed)) idescriptor_t;
+} __attribute__((packed)) idescriptor_t;
 
 typedef struct {
 	uint16_t limit;
 	uint64_t base;
-} __attribute__ ((packed)) ptr_16_64_t;
+} __attribute__((packed)) ptr_16_64_t;
 
 typedef struct {
 	uint16_t limit;
 	uint32_t base;
-} __attribute__ ((packed)) ptr_16_32_t;
+} __attribute__((packed)) ptr_16_32_t;
 
 typedef struct {
@@ -160,5 +160,5 @@
 	uint16_t iomap_base;
 	uint8_t iomap[TSS_IOMAP_SIZE];
-} __attribute__ ((packed)) tss_t;
+} __attribute__((packed)) tss_t;
 
 extern tss_t *tss_p;
Index: kernel/arch/amd64/src/cpu/cpu.c
===================================================================
--- kernel/arch/amd64/src/cpu/cpu.c	(revision fd57745cd4811832fa23ba1cef7638038244f2b5)
+++ kernel/arch/amd64/src/cpu/cpu.c	(revision 231c770580f4400a6e0e7612723b1efb16fd5390)
@@ -136,5 +136,5 @@
 }
 
-void cpu_print_report(cpu_t* m)
+void cpu_print_report(cpu_t *m)
 {
 	printf("cpu%d: (%s family=%d model=%d stepping=%d apicid=%u) %dMHz\n",
Index: kernel/arch/amd64/src/fpu_context.c
===================================================================
--- kernel/arch/amd64/src/fpu_context.c	(revision fd57745cd4811832fa23ba1cef7638038244f2b5)
+++ kernel/arch/amd64/src/fpu_context.c	(revision 231c770580f4400a6e0e7612723b1efb16fd5390)
@@ -40,6 +40,6 @@
 {
 	asm volatile (
-		"fxsave %[fctx]\n"
-		: [fctx] "=m" (fctx->fpu)
+	    "fxsave %[fctx]\n"
+	    : [fctx] "=m" (fctx->fpu)
 	);
 }
@@ -49,6 +49,6 @@
 {
 	asm volatile (
-		"fxrstor %[fctx]\n"
-		: [fctx] "=m" (fctx->fpu)
+	    "fxrstor %[fctx]\n"
+	    : [fctx] "=m" (fctx->fpu)
 	);
 }
@@ -60,5 +60,5 @@
 	 * it masks all FPU exceptions*/
 	asm volatile (
-		"fninit\n"
+	    "fninit\n"
 	);
 }
Index: kernel/arch/amd64/src/interrupt.c
===================================================================
--- kernel/arch/amd64/src/interrupt.c	(revision fd57745cd4811832fa23ba1cef7638038244f2b5)
+++ kernel/arch/amd64/src/interrupt.c	(revision 231c770580f4400a6e0e7612723b1efb16fd5390)
@@ -60,7 +60,7 @@
  */
 
-void (* disable_irqs_function)(uint16_t irqmask) = NULL;
-void (* enable_irqs_function)(uint16_t irqmask) = NULL;
-void (* eoi_function)(void) = NULL;
+void (*disable_irqs_function)(uint16_t irqmask) = NULL;
+void (*enable_irqs_function)(uint16_t irqmask) = NULL;
+void (*eoi_function)(void) = NULL;
 const char *irqs_info = NULL;
 
@@ -231,5 +231,5 @@
 	    (iroutine_t) tlb_shootdown_ipi);
 	exc_register(VECTOR_SMP_CALL_IPI, "smp_call", true,
-		(iroutine_t) arch_smp_call_ipi_recv);
+	    (iroutine_t) arch_smp_call_ipi_recv);
 #endif
 }
Index: kernel/arch/amd64/src/pm.c
===================================================================
--- kernel/arch/amd64/src/pm.c	(revision fd57745cd4811832fa23ba1cef7638038244f2b5)
+++ kernel/arch/amd64/src/pm.c	(revision 231c770580f4400a6e0e7612723b1efb16fd5390)
@@ -55,5 +55,5 @@
 		.limit_0_15 = 0xffffU,
 		.limit_16_19 = 0xfU,
-	  	.access = AR_PRESENT | AR_CODE | DPL_KERNEL | AR_READABLE,
+		.access = AR_PRESENT | AR_CODE | DPL_KERNEL | AR_READABLE,
 		.longmode = 1,
 		.granularity = 1
Index: kernel/arch/arm32/include/arch/mm/page_fault.h
===================================================================
--- kernel/arch/arm32/include/arch/mm/page_fault.h	(revision fd57745cd4811832fa23ba1cef7638038244f2b5)
+++ kernel/arch/arm32/include/arch/mm/page_fault.h	(revision 231c770580f4400a6e0e7612723b1efb16fd5390)
@@ -58,5 +58,5 @@
 		unsigned fs : 1; /**< armv6+ mandated, earlier IPLM. DEFINED */
 		unsigned wr : 1; /**< armv6+ only */
-		unsigned ext : 1 ; /**< external abort */
+		unsigned ext : 1; /**< external abort */
 		unsigned cm : 1; /**< Cache maintenance, needs LPAE support */
 		unsigned should_be_zero : 18;
Index: kernel/arch/arm32/src/arm32.c
===================================================================
--- kernel/arch/arm32/src/arm32.c	(revision fd57745cd4811832fa23ba1cef7638038244f2b5)
+++ kernel/arch/arm32/src/arm32.c	(revision 231c770580f4400a6e0e7612723b1efb16fd5390)
@@ -156,5 +156,6 @@
 {
 	/* not implemented */
-	while (true);
+	while (true)
+		;
 }
 
Index: kernel/arch/arm32/src/atomic.c
===================================================================
--- kernel/arch/arm32/src/atomic.c	(revision fd57745cd4811832fa23ba1cef7638038244f2b5)
+++ kernel/arch/arm32/src/atomic.c	(revision 231c770580f4400a6e0e7612723b1efb16fd5390)
@@ -44,5 +44,5 @@
  * returns the previous value of \a *ptr.
  */
-void * __sync_val_compare_and_swap_4(void **ptr, void *expected, void *new_val)
+void *__sync_val_compare_and_swap_4(void **ptr, void *expected, void *new_val)
 {
 	/*
@@ -55,5 +55,5 @@
 	irq_spinlock_lock(&cas_lock, true);
 
-	void * cur_val = *ptr;
+	void *cur_val = *ptr;
 
 	if (cur_val == expected) {
Index: kernel/arch/arm32/src/cpu/cpu.c
===================================================================
--- kernel/arch/arm32/src/cpu/cpu.c	(revision fd57745cd4811832fa23ba1cef7638038244f2b5)
+++ kernel/arch/arm32/src/cpu/cpu.c	(revision 231c770580f4400a6e0e7612723b1efb16fd5390)
@@ -62,13 +62,19 @@
 
 /** Implementers (vendor) names */
-static const char * implementer(unsigned id)
+static const char *implementer(unsigned id)
 {
 	switch (id) {
-	case 0x41: return "ARM Limited";
-	case 0x44: return "Digital Equipment Corporation";
-	case 0x4d: return "Motorola, Freescale Semiconductor Inc.";
-	case 0x51: return "Qualcomm Inc.";
-	case 0x56: return "Marvell Semiconductor Inc.";
-	case 0x69: return "Intel Corporation";
+	case 0x41:
+		return "ARM Limited";
+	case 0x44:
+		return "Digital Equipment Corporation";
+	case 0x4d:
+		return "Motorola, Freescale Semiconductor Inc.";
+	case 0x51:
+		return "Qualcomm Inc.";
+	case 0x56:
+		return "Marvell Semiconductor Inc.";
+	case 0x69:
+		return "Intel Corporation";
 	}
 	return "Unknown implementer";
@@ -76,5 +82,5 @@
 
 /** Architecture names */
-static const char * architecture_string(cpu_arch_t *arch)
+static const char *architecture_string(cpu_arch_t *arch)
 {
 	static const char *arch_data[] = {
Index: kernel/arch/arm32/src/fpu_context.c
===================================================================
--- kernel/arch/arm32/src/fpu_context.c	(revision fd57745cd4811832fa23ba1cef7638038244f2b5)
+++ kernel/arch/arm32/src/fpu_context.c	(revision 231c770580f4400a6e0e7612723b1efb16fd5390)
@@ -126,5 +126,5 @@
 	 * Moreover they need to have same access enabled */
 	if (((cpacr & CPACR_CP_MASK(10)) != CPACR_CP_FULL_ACCESS(10)) &&
-	   ((cpacr & CPACR_CP_MASK(11)) != CPACR_CP_FULL_ACCESS(11))) {
+	    ((cpacr & CPACR_CP_MASK(11)) != CPACR_CP_FULL_ACCESS(11))) {
 		printf("No access to CP10 and CP11: %" PRIx32 "\n", cpacr);
 		return 0;
Index: kernel/arch/arm32/src/mach/beagleboardxm/beagleboardxm.c
===================================================================
--- kernel/arch/arm32/src/mach/beagleboardxm/beagleboardxm.c	(revision fd57745cd4811832fa23ba1cef7638038244f2b5)
+++ kernel/arch/arm32/src/mach/beagleboardxm/beagleboardxm.c	(revision 231c770580f4400a6e0e7612723b1efb16fd5390)
@@ -130,5 +130,6 @@
 static void bbxm_cpu_halt(void)
 {
-	while (1);
+	while (1)
+		;
 }
 
Index: kernel/arch/arm32/src/mach/beaglebone/beaglebone.c
===================================================================
--- kernel/arch/arm32/src/mach/beaglebone/beaglebone.c	(revision fd57745cd4811832fa23ba1cef7638038244f2b5)
+++ kernel/arch/arm32/src/mach/beaglebone/beaglebone.c	(revision 231c770580f4400a6e0e7612723b1efb16fd5390)
@@ -137,5 +137,5 @@
 	/* Select the SYSCLK as the clock source for the dmtimer2 module */
 	am335x_clock_source_select(bbone.cm_dpll_addr, DMTIMER2,
-	   CLK_SRC_M_OSC);
+	    CLK_SRC_M_OSC);
 	/* Initialize the DMTIMER2 */
 	if (am335x_ctrl_module_clock_freq_get(bbone.ctrl_module,
@@ -159,5 +159,6 @@
 static void bbone_cpu_halt(void)
 {
-	while (1);
+	while (1)
+		;
 }
 
Index: kernel/arch/arm32/src/machine_func.c
===================================================================
--- kernel/arch/arm32/src/machine_func.c	(revision fd57745cd4811832fa23ba1cef7638038244f2b5)
+++ kernel/arch/arm32/src/machine_func.c	(revision 231c770580f4400a6e0e7612723b1efb16fd5390)
@@ -137,5 +137,5 @@
 }
 
-const char * machine_get_platform_name(void)
+const char *machine_get_platform_name(void)
 {
 	if (machine_ops->machine_get_platform_name)
Index: kernel/arch/arm32/src/mm/page_fault.c
===================================================================
--- kernel/arch/arm32/src/mm/page_fault.c	(revision fd57745cd4811832fa23ba1cef7638038244f2b5)
+++ kernel/arch/arm32/src/mm/page_fault.c	(revision 231c770580f4400a6e0e7612723b1efb16fd5390)
@@ -75,5 +75,5 @@
 } dfsr_source_t;
 
-static inline const char * dfsr_source_to_str(dfsr_source_t source)
+static inline const char *dfsr_source_to_str(dfsr_source_t source)
 {
 	switch (source)	{
@@ -149,5 +149,5 @@
 		panic("page_fault - instruction does not access memory "
 		    "(instr_code: %#0" PRIx32 ", badvaddr:%p).",
-		    *(uint32_t*)instr_union.instr, (void *) badvaddr);
+		    *(uint32_t *)instr_union.instr, (void *) badvaddr);
 		return PF_ACCESS_EXEC;
 	}
@@ -177,5 +177,5 @@
 		{ 0x0fb00000, 0x01000000, PF_ACCESS_WRITE },
 	};
-	const uint32_t inst = *(uint32_t*)instr_addr;
+	const uint32_t inst = *(uint32_t *)instr_addr;
 	for (unsigned i = 0; i < sizeof(ls_inst) / sizeof(ls_inst[0]); ++i) {
 		if ((inst & ls_inst[i].mask) == ls_inst[i].value) {
Index: kernel/arch/arm32/src/userspace.c
===================================================================
--- kernel/arch/arm32/src/userspace.c	(revision fd57745cd4811832fa23ba1cef7638038244f2b5)
+++ kernel/arch/arm32/src/userspace.c	(revision 231c770580f4400a6e0e7612723b1efb16fd5390)
@@ -104,15 +104,15 @@
 	/* set user mode, set registers, jump */
 	asm volatile (
-		"mov sp, %[ustate]\n"
-		"msr spsr_c, %[user_mode]\n"
-		"ldmfd sp, {r0-r12, sp, lr}^\n"
-		"nop\n"		/* Cannot access sp immediately after ldm(2) */
-		"add sp, sp, #(15*4)\n"
-		"ldmfd sp!, {pc}^\n"
-		:: [ustate] "r" (&ustate), [user_mode] "r" (user_mode)
+	    "mov sp, %[ustate]\n"
+	    "msr spsr_c, %[user_mode]\n"
+	    "ldmfd sp, {r0-r12, sp, lr}^\n"
+	    "nop\n"		/* Cannot access sp immediately after ldm(2) */
+	    "add sp, sp, #(15*4)\n"
+	    "ldmfd sp!, {pc}^\n"
+	    :: [ustate] "r" (&ustate), [user_mode] "r" (user_mode)
 	);
 
 	/* unreachable */
-	while(1)
+	while (1)
 		;
 }
Index: kernel/arch/ia32/include/arch/atomic.h
===================================================================
--- kernel/arch/ia32/include/arch/atomic.h	(revision fd57745cd4811832fa23ba1cef7638038244f2b5)
+++ kernel/arch/ia32/include/arch/atomic.h	(revision 231c770580f4400a6e0e7612723b1efb16fd5390)
@@ -46,11 +46,11 @@
 #ifdef CONFIG_SMP
 	asm volatile (
-		"lock incl %[count]\n"
-		: [count] "+m" (val->count)
-	);
-#else
-	asm volatile (
-		"incl %[count]\n"
-		: [count] "+m" (val->count)
+	    "lock incl %[count]\n"
+	    : [count] "+m" (val->count)
+	);
+#else
+	asm volatile (
+	    "incl %[count]\n"
+	    : [count] "+m" (val->count)
 	);
 #endif /* CONFIG_SMP */
@@ -61,11 +61,11 @@
 #ifdef CONFIG_SMP
 	asm volatile (
-		"lock decl %[count]\n"
-		: [count] "+m" (val->count)
-	);
-#else
-	asm volatile (
-		"decl %[count]\n"
-		: [count] "+m" (val->count)
+	    "lock decl %[count]\n"
+	    : [count] "+m" (val->count)
+	);
+#else
+	asm volatile (
+	    "decl %[count]\n"
+	    : [count] "+m" (val->count)
 	);
 #endif /* CONFIG_SMP */
@@ -77,7 +77,7 @@
 
 	asm volatile (
-		"lock xaddl %[r], %[count]\n"
-		: [count] "+m" (val->count),
-		  [r] "+r" (r)
+	    "lock xaddl %[r], %[count]\n"
+	    : [count] "+m" (val->count),
+	      [r] "+r" (r)
 	);
 
@@ -90,7 +90,7 @@
 
 	asm volatile (
-		"lock xaddl %[r], %[count]\n"
-		: [count] "+m" (val->count),
-		  [r] "+r" (r)
+	    "lock xaddl %[r], %[count]\n"
+	    : [count] "+m" (val->count),
+	      [r] "+r" (r)
 	);
 
@@ -106,7 +106,7 @@
 
 	asm volatile (
-		"xchgl %[v], %[count]\n"
-		: [v] "+r" (v),
-		  [count] "+m" (val->count)
+	    "xchgl %[v], %[count]\n"
+	    : [v] "+r" (v),
+	      [count] "+m" (val->count)
 	);
 
@@ -122,18 +122,18 @@
 	preemption_disable();
 	asm volatile (
-		"0:\n"
+	    "0:\n"
 #ifndef PROCESSOR_i486
-		"pause\n"        /* Pentium 4's HT love this instruction */
-#endif
-		"mov %[count], %[tmp]\n"
-		"testl %[tmp], %[tmp]\n"
-		"jnz 0b\n"       /* lightweight looping on locked spinlock */
-
-		"incl %[tmp]\n"  /* now use the atomic operation */
-		"xchgl %[count], %[tmp]\n"
-		"testl %[tmp], %[tmp]\n"
-		"jnz 0b\n"
-		: [count] "+m" (val->count),
-		  [tmp] "=&r" (tmp)
+	    "pause\n"        /* Pentium 4's HT love this instruction */
+#endif
+	    "mov %[count], %[tmp]\n"
+	    "testl %[tmp], %[tmp]\n"
+	    "jnz 0b\n"       /* lightweight looping on locked spinlock */
+
+	    "incl %[tmp]\n"  /* now use the atomic operation */
+	    "xchgl %[count], %[tmp]\n"
+	    "testl %[tmp], %[tmp]\n"
+	    "jnz 0b\n"
+	    : [count] "+m" (val->count),
+	      [tmp] "=&r" (tmp)
 	);
 
Index: kernel/arch/ia32/include/arch/barrier.h
===================================================================
--- kernel/arch/ia32/include/arch/barrier.h	(revision fd57745cd4811832fa23ba1cef7638038244f2b5)
+++ kernel/arch/ia32/include/arch/barrier.h	(revision 231c770580f4400a6e0e7612723b1efb16fd5390)
@@ -56,16 +56,16 @@
 #ifndef __PIC__
 	asm volatile (
-		"xorl %%eax, %%eax\n"
-		"cpuid\n"
-		::: "eax", "ebx", "ecx", "edx", "memory"
+	    "xorl %%eax, %%eax\n"
+	    "cpuid\n"
+	    ::: "eax", "ebx", "ecx", "edx", "memory"
 	);
 #else
 	/* Must not clobber PIC register ebx */
 	asm volatile (
-		"movl %%ebx, %%esi\n"
-		"xorl %%eax, %%eax\n"
-		"cpuid\n"
-		"movl %%esi, %%ebx\n"
-		::: "eax", "ecx", "edx", "esi", "memory"
+	    "movl %%ebx, %%esi\n"
+	    "xorl %%eax, %%eax\n"
+	    "cpuid\n"
+	    "movl %%esi, %%ebx\n"
+	    ::: "eax", "ecx", "edx", "esi", "memory"
 	);
 #endif
@@ -73,27 +73,27 @@
 
 #if defined(CONFIG_FENCES_P4)
-	#define memory_barrier()  asm volatile ("mfence\n" ::: "memory")
-	#define read_barrier()    asm volatile ("lfence\n" ::: "memory")
-	#ifdef CONFIG_WEAK_MEMORY
-		#define write_barrier()  asm volatile ("sfence\n" ::: "memory")
-	#else
-		#define write_barrier()  asm volatile ("" ::: "memory");
-	#endif
+#define memory_barrier()  asm volatile ("mfence\n" ::: "memory")
+#define read_barrier()    asm volatile ("lfence\n" ::: "memory")
+#ifdef CONFIG_WEAK_MEMORY
+#define write_barrier()  asm volatile ("sfence\n" ::: "memory")
+#else
+#define write_barrier()  asm volatile ("" ::: "memory");
+#endif
 #elif defined(CONFIG_FENCES_P3)
-	#define memory_barrier()  cpuid_serialization()
-	#define read_barrier()    cpuid_serialization()
-	#ifdef CONFIG_WEAK_MEMORY
-		#define write_barrier()  asm volatile ("sfence\n" ::: "memory")
-	#else
-		#define write_barrier()  asm volatile ("" ::: "memory");
-	#endif
+#define memory_barrier()  cpuid_serialization()
+#define read_barrier()    cpuid_serialization()
+#ifdef CONFIG_WEAK_MEMORY
+#define write_barrier()  asm volatile ("sfence\n" ::: "memory")
 #else
-	#define memory_barrier()  cpuid_serialization()
-	#define read_barrier()    cpuid_serialization()
-	#ifdef CONFIG_WEAK_MEMORY
-		#define write_barrier()  cpuid_serialization()
-	#else
-		#define write_barrier()  asm volatile ("" ::: "memory");
-	#endif
+#define write_barrier()  asm volatile ("" ::: "memory");
+#endif
+#else
+#define memory_barrier()  cpuid_serialization()
+#define read_barrier()    cpuid_serialization()
+#ifdef CONFIG_WEAK_MEMORY
+#define write_barrier()  cpuid_serialization()
+#else
+#define write_barrier()  asm volatile ("" ::: "memory");
+#endif
 #endif
 
Index: kernel/arch/ia32/include/arch/cpuid.h
===================================================================
--- kernel/arch/ia32/include/arch/cpuid.h	(revision fd57745cd4811832fa23ba1cef7638038244f2b5)
+++ kernel/arch/ia32/include/arch/cpuid.h	(revision 231c770580f4400a6e0e7612723b1efb16fd5390)
@@ -85,20 +85,20 @@
 
 	asm volatile (
-		"pushf\n"                      /* read flags */
-		"popl %[ret]\n"
-		"movl %[ret], %[val]\n"
+	    "pushf\n"                      /* read flags */
+	    "popl %[ret]\n"
+	    "movl %[ret], %[val]\n"
 
-		"xorl %[eflags_id], %[val]\n"  /* swap the ID bit */
+	    "xorl %[eflags_id], %[val]\n"  /* swap the ID bit */
 
-		"pushl %[val]\n"               /* propagate the change into flags */
-		"popf\n"
-		"pushf\n"
-		"popl %[val]\n"
+	    "pushl %[val]\n"               /* propagate the change into flags */
+	    "popf\n"
+	    "pushf\n"
+	    "popl %[val]\n"
 
-		"andl %[eflags_id], %[ret]\n"  /* interrested only in ID bit */
-		"andl %[eflags_id], %[val]\n"
-		"xorl %[val], %[ret]\n"
-		: [ret] "=r" (ret), [val] "=r" (val)
-		: [eflags_id] "i" (EFLAGS_ID)
+	    "andl %[eflags_id], %[ret]\n"  /* interrested only in ID bit */
+	    "andl %[eflags_id], %[val]\n"
+	    "xorl %[val], %[ret]\n"
+	    : [ret] "=r" (ret), [val] "=r" (val)
+	    : [eflags_id] "i" (EFLAGS_ID)
 	);
 
@@ -109,8 +109,8 @@
 {
 	asm volatile (
-		"cpuid\n"
-		: "=a" (info->cpuid_eax), "=b" (info->cpuid_ebx),
-		  "=c" (info->cpuid_ecx), "=d" (info->cpuid_edx)
-		: "a" (cmd)
+	    "cpuid\n"
+	    : "=a" (info->cpuid_eax), "=b" (info->cpuid_ebx),
+	      "=c" (info->cpuid_ecx), "=d" (info->cpuid_edx)
+	    : "a" (cmd)
 	);
 }
Index: kernel/arch/ia32/include/arch/cycle.h
===================================================================
--- kernel/arch/ia32/include/arch/cycle.h	(revision fd57745cd4811832fa23ba1cef7638038244f2b5)
+++ kernel/arch/ia32/include/arch/cycle.h	(revision 231c770580f4400a6e0e7612723b1efb16fd5390)
@@ -45,7 +45,7 @@
 	uint64_t v;
 
-	asm volatile(
-		"rdtsc\n"
-		: "=A" (v)
+	asm volatile (
+	    "rdtsc\n"
+	    : "=A" (v)
 	);
 
Index: kernel/arch/ia32/include/arch/mm/page.h
===================================================================
--- kernel/arch/ia32/include/arch/mm/page.h	(revision fd57745cd4811832fa23ba1cef7638038244f2b5)
+++ kernel/arch/ia32/include/arch/mm/page.h	(revision 231c770580f4400a6e0e7612723b1efb16fd5390)
@@ -178,5 +178,5 @@
 	unsigned avl : 2;
 	unsigned frame_address : 20;
-} __attribute__ ((packed)) pte_t;
+} __attribute__((packed)) pte_t;
 
 NO_TRACE static inline unsigned int get_pt_flags(pte_t *pt, size_t i)
Index: kernel/arch/ia32/include/arch/pm.h
===================================================================
--- kernel/arch/ia32/include/arch/pm.h	(revision fd57745cd4811832fa23ba1cef7638038244f2b5)
+++ kernel/arch/ia32/include/arch/pm.h	(revision 231c770580f4400a6e0e7612723b1efb16fd5390)
@@ -89,26 +89,26 @@
 	uint16_t limit;
 	uint32_t base;
-} __attribute__ ((packed)) ptr_16_32_t;
+} __attribute__((packed)) ptr_16_32_t;
 
 typedef struct {
-	unsigned limit_0_15: 16;
-	unsigned base_0_15: 16;
-	unsigned base_16_23: 8;
-	unsigned access: 8;
-	unsigned limit_16_19: 4;
-	unsigned available: 1;
-	unsigned unused: 1;
-	unsigned special: 1;
+	unsigned limit_0_15 : 16;
+	unsigned base_0_15 : 16;
+	unsigned base_16_23 : 8;
+	unsigned access : 8;
+	unsigned limit_16_19 : 4;
+	unsigned available : 1;
+	unsigned unused : 1;
+	unsigned special : 1;
 	unsigned granularity : 1;
-	unsigned base_24_31: 8;
-} __attribute__ ((packed)) descriptor_t;
+	unsigned base_24_31 : 8;
+} __attribute__((packed)) descriptor_t;
 
 typedef struct {
-	unsigned offset_0_15: 16;
-	unsigned selector: 16;
-	unsigned unused: 8;
-	unsigned access: 8;
-	unsigned offset_16_31: 16;
-} __attribute__ ((packed)) idescriptor_t;
+	unsigned offset_0_15 : 16;
+	unsigned selector : 16;
+	unsigned unused : 8;
+	unsigned access : 8;
+	unsigned offset_16_31 : 16;
+} __attribute__((packed)) idescriptor_t;
 
 typedef struct {
@@ -152,5 +152,5 @@
 	uint16_t iomap_base;
 	uint8_t iomap[TSS_IOMAP_SIZE];
-} __attribute__ ((packed)) tss_t;
+} __attribute__((packed)) tss_t;
 
 extern ptr_16_32_t gdtr;
Index: kernel/arch/ia32/include/arch/smp/apic.h
===================================================================
--- kernel/arch/ia32/include/arch/smp/apic.h	(revision fd57745cd4811832fa23ba1cef7638038244f2b5)
+++ kernel/arch/ia32/include/arch/smp/apic.h	(revision 231c770580f4400a6e0e7612723b1efb16fd5390)
@@ -128,5 +128,5 @@
 			unsigned int shorthand : 2;     /**< Destination Shorthand. */
 			unsigned int : 12;              /**< Reserved. */
-		} __attribute__ ((packed));
+		} __attribute__((packed));
 	};
 	union {
@@ -135,7 +135,7 @@
 			unsigned int : 24;  /**< Reserved. */
 			uint8_t dest;       /**< Destination field. */
-		} __attribute__ ((packed));
+		} __attribute__((packed));
 	};
-} __attribute__ ((packed)) icr_t;
+} __attribute__((packed)) icr_t;
 
 /* End Of Interrupt. */
@@ -158,5 +158,5 @@
 		unsigned int illegal_register_address : 1;
 		unsigned int : 24;
-	} __attribute__ ((packed));
+	} __attribute__((packed));
 } esr_t;
 
@@ -169,5 +169,5 @@
 		unsigned int pri_sc : 4;  /**< Task Priority Sub-Class. */
 		unsigned int pri : 4;     /**< Task Priority. */
-	} __attribute__ ((packed));
+	} __attribute__((packed));
 } tpr_t;
 
@@ -182,5 +182,5 @@
 		unsigned int focus_checking : 1;  /**< Focus Processor Checking. */
 		unsigned int : 22;                /**< Reserved. */
-	} __attribute__ ((packed));
+	} __attribute__((packed));
 } svr_t;
 
@@ -193,5 +193,5 @@
 		unsigned int div_value : 4;  /**< Divide Value, bit 2 is always 0. */
 		unsigned int : 28;           /**< Reserved. */
-	} __attribute__ ((packed));
+	} __attribute__((packed));
 } tdcr_t;
 
@@ -215,5 +215,5 @@
 		unsigned int mode : 1;    /**< Timer Mode. */
 		unsigned int : 14;        /**< Reserved. */
-	} __attribute__ ((packed));
+	} __attribute__((packed));
 } lvt_tm_t;
 
@@ -234,5 +234,5 @@
 		unsigned int masked : 1;        /**< Interrupt Mask. */
 		unsigned int : 15;              /**< Reserved. */
-	} __attribute__ ((packed));
+	} __attribute__((packed));
 } lvt_lint_t;
 
@@ -249,5 +249,5 @@
 		unsigned int masked : 1;  /**< Interrupt Mask. */
 		unsigned int : 15;        /**< Reserved. */
-	} __attribute__ ((packed));
+	} __attribute__((packed));
 } lvt_error_t;
 
@@ -260,5 +260,5 @@
 		unsigned int : 24;  /**< Reserved. */
 		uint8_t apic_id;    /**< Local APIC ID. */
-	} __attribute__ ((packed));
+	} __attribute__((packed));
 } l_apic_id_t;
 
@@ -279,5 +279,5 @@
 		unsigned int : 24;  /**< Reserved. */
 		uint8_t id;         /**< Logical APIC ID. */
-	} __attribute__ ((packed));
+	} __attribute__((packed));
 } ldr_t;
 
@@ -290,5 +290,5 @@
 		unsigned int : 28;       /**< Reserved, all ones. */
 		unsigned int model : 4;  /**< Model. */
-	} __attribute__ ((packed));
+	} __attribute__((packed));
 } dfr_t;
 
@@ -308,5 +308,5 @@
 		uint8_t reg_addr;   /**< APIC Register Address. */
 		unsigned int : 24;  /**< Reserved. */
-	} __attribute__ ((packed));
+	} __attribute__((packed));
 } io_regsel_t;
 
@@ -325,5 +325,5 @@
 			unsigned int masked : 1;        /**< Interrupt Mask. */
 			unsigned int : 15;              /**< Reserved. */
-		} __attribute__ ((packed));
+		} __attribute__((packed));
 	};
 	union {
@@ -332,8 +332,8 @@
 			unsigned int : 24;  /**< Reserved. */
 			uint8_t dest : 8;   /**< Destination Field. */
-		} __attribute__ ((packed));
+		} __attribute__((packed));
 	};
 
-} __attribute__ ((packed)) io_redirection_reg_t;
+} __attribute__((packed)) io_redirection_reg_t;
 
 
@@ -345,5 +345,5 @@
 		unsigned int apic_id : 4;  /**< IO APIC ID. */
 		unsigned int : 4;          /**< Reserved. */
-	} __attribute__ ((packed));
+	} __attribute__((packed));
 } io_apic_id_t;
 
Index: kernel/arch/ia32/include/arch/smp/mps.h
===================================================================
--- kernel/arch/ia32/include/arch/smp/mps.h	(revision fd57745cd4811832fa23ba1cef7638038244f2b5)
+++ kernel/arch/ia32/include/arch/smp/mps.h	(revision 231c770580f4400a6e0e7612723b1efb16fd5390)
@@ -55,5 +55,5 @@
 	uint8_t mpfib4;
 	uint8_t mpfib5;
-} __attribute__ ((packed));
+} __attribute__((packed));
 
 struct mps_ct {
@@ -72,5 +72,5 @@
 	uint8_t reserved;
 	uint8_t base_table[0];
-} __attribute__ ((packed));
+} __attribute__((packed));
 
 struct __processor_entry {
@@ -82,5 +82,5 @@
 	uint32_t feature_flags;
 	uint32_t reserved[2];
-} __attribute__ ((packed));
+} __attribute__((packed));
 
 struct __bus_entry {
@@ -88,5 +88,5 @@
 	uint8_t bus_id;
 	uint8_t bus_type[6];
-} __attribute__ ((packed));
+} __attribute__((packed));
 
 struct __io_apic_entry {
@@ -96,5 +96,5 @@
 	uint8_t io_apic_flags;
 	uint32_t io_apic;
-} __attribute__ ((packed));
+} __attribute__((packed));
 
 struct __io_intr_entry {
@@ -107,5 +107,5 @@
 	uint8_t dst_io_apic_id;
 	uint8_t dst_io_apic_pin;
-} __attribute__ ((packed));
+} __attribute__((packed));
 
 struct __l_intr_entry {
@@ -118,5 +118,5 @@
 	uint8_t dst_l_apic_id;
 	uint8_t dst_l_apic_pin;
-} __attribute__ ((packed));
+} __attribute__((packed));
 
 extern struct smp_config_operations mps_config_operations;
Index: kernel/arch/ia32/src/fpu_context.c
===================================================================
--- kernel/arch/ia32/src/fpu_context.c	(revision fd57745cd4811832fa23ba1cef7638038244f2b5)
+++ kernel/arch/ia32/src/fpu_context.c	(revision 231c770580f4400a6e0e7612723b1efb16fd5390)
@@ -71,6 +71,6 @@
 {
 	asm volatile (
-		"fnsave %[fctx]"
-		: [fctx] "=m" (fctx->fpu)
+	    "fnsave %[fctx]"
+	    : [fctx] "=m" (fctx->fpu)
 	);
 }
@@ -79,6 +79,6 @@
 {
 	asm volatile (
-		"frstor %[fctx]"
-		: [fctx] "=m" (fctx->fpu)
+	    "frstor %[fctx]"
+	    : [fctx] "=m" (fctx->fpu)
 	);
 }
@@ -87,6 +87,6 @@
 {
 	asm volatile (
-		"fxsave %[fctx]"
-		: [fctx] "=m" (fctx->fpu)
+	    "fxsave %[fctx]"
+	    : [fctx] "=m" (fctx->fpu)
 	);
 }
@@ -95,6 +95,6 @@
 {
 	asm volatile (
-		"fxrstor %[fctx]"
-		: [fctx] "=m" (fctx->fpu)
+	    "fxrstor %[fctx]"
+	    : [fctx] "=m" (fctx->fpu)
 	);
 }
@@ -131,12 +131,12 @@
 
 	asm volatile (
-		"fninit\n"
-		"stmxcsr %[help0]\n"
-		"mov %[help0], %[help1]\n"
-		"or %[magic], %[help1]\n"
-		"mov %[help1], %[help0]\n"
-		"ldmxcsr %[help0]\n"
-		: [help0] "+m" (help0), [help1] "+r" (help1)
-		: [magic] "i" (X87_ALL_MASK)
+	    "fninit\n"
+	    "stmxcsr %[help0]\n"
+	    "mov %[help0], %[help1]\n"
+	    "or %[magic], %[help1]\n"
+	    "mov %[help1], %[help0]\n"
+	    "ldmxcsr %[help0]\n"
+	    : [help0] "+m" (help0), [help1] "+r" (help1)
+	    : [magic] "i" (X87_ALL_MASK)
 	);
 }
Index: kernel/arch/ia32/src/interrupt.c
===================================================================
--- kernel/arch/ia32/src/interrupt.c	(revision fd57745cd4811832fa23ba1cef7638038244f2b5)
+++ kernel/arch/ia32/src/interrupt.c	(revision 231c770580f4400a6e0e7612723b1efb16fd5390)
@@ -62,7 +62,7 @@
  */
 
-void (* disable_irqs_function)(uint16_t irqmask) = NULL;
-void (* enable_irqs_function)(uint16_t irqmask) = NULL;
-void (* eoi_function)(void) = NULL;
+void (*disable_irqs_function)(uint16_t irqmask) = NULL;
+void (*enable_irqs_function)(uint16_t irqmask) = NULL;
+void (*eoi_function)(void) = NULL;
 const char *irqs_info = NULL;
 
@@ -146,6 +146,6 @@
 	uint32_t mxcsr;
 	asm volatile (
-		"stmxcsr %[mxcsr]\n"
-		: [mxcsr] "=m" (mxcsr)
+	    "stmxcsr %[mxcsr]\n"
+	    : [mxcsr] "=m" (mxcsr)
 	);
 
Index: kernel/arch/ia32/src/mm/frame.c
===================================================================
--- kernel/arch/ia32/src/mm/frame.c	(revision fd57745cd4811832fa23ba1cef7638038244f2b5)
+++ kernel/arch/ia32/src/mm/frame.c	(revision 231c770580f4400a6e0e7612723b1efb16fd5390)
@@ -142,5 +142,5 @@
 			name = "invalid";
 
-		printf("%#018" PRIx64 " %#018" PRIx64" %s\n", e820table[i].base_address,
+		printf("%#018" PRIx64 " %#018" PRIx64 " %s\n", e820table[i].base_address,
 		    e820table[i].size, name);
 	}
Index: kernel/arch/ia32/src/smp/apic.c
===================================================================
--- kernel/arch/ia32/src/smp/apic.c	(revision fd57745cd4811832fa23ba1cef7638038244f2b5)
+++ kernel/arch/ia32/src/smp/apic.c	(revision 231c770580f4400a6e0e7612723b1efb16fd5390)
@@ -482,5 +482,6 @@
 	l_apic[ICRT] = 0xffffffff;
 
-	while (l_apic[CCRT] == t1);
+	while (l_apic[CCRT] == t1)
+		;
 
 	t1 = l_apic[CCRT];
Index: kernel/arch/ia32/src/smp/mps.c
===================================================================
--- kernel/arch/ia32/src/smp/mps.c	(revision fd57745cd4811832fa23ba1cef7638038244f2b5)
+++ kernel/arch/ia32/src/smp/mps.c	(revision 231c770580f4400a6e0e7612723b1efb16fd5390)
@@ -257,5 +257,5 @@
 	}
 
-	log_printf(", bus=%" PRIu8 " irq=%" PRIu8 " io_apic=%" PRIu8" pin=%"
+	log_printf(", bus=%" PRIu8 " irq=%" PRIu8 " io_apic=%" PRIu8 " pin=%"
 	    PRIu8, iointr->src_bus_id, iointr->src_bus_irq,
 	    iointr->dst_io_apic_id, iointr->dst_io_apic_pin);
@@ -320,5 +320,5 @@
 	}
 
-	log_printf(", bus=%" PRIu8 " irq=%" PRIu8 " l_apic=%" PRIu8" pin=%"
+	log_printf(", bus=%" PRIu8 " irq=%" PRIu8 " l_apic=%" PRIu8 " pin=%"
 	    PRIu8, lintr->src_bus_id, lintr->src_bus_irq,
 	    lintr->dst_l_apic_id, lintr->dst_l_apic_pin);
Index: kernel/arch/ia64/include/arch/asm.h
===================================================================
--- kernel/arch/ia64/include/arch/asm.h	(revision fd57745cd4811832fa23ba1cef7638038244f2b5)
+++ kernel/arch/ia64/include/arch/asm.h	(revision 231c770580f4400a6e0e7612723b1efb16fd5390)
@@ -60,7 +60,7 @@
 
 	asm volatile (
-		"mf\n"
-		"mf.a\n"
-		::: "memory"
+	    "mf\n"
+	    "mf.a\n"
+	    ::: "memory"
 	);
 }
@@ -74,7 +74,7 @@
 
 	asm volatile (
-		"mf\n"
-		"mf.a\n"
-		::: "memory"
+	    "mf\n"
+	    "mf.a\n"
+	    ::: "memory"
 	);
 }
@@ -88,7 +88,7 @@
 
 	asm volatile (
-		"mf\n"
-		"mf.a\n"
-		::: "memory"
+	    "mf\n"
+	    "mf.a\n"
+	    ::: "memory"
 	);
 }
@@ -99,6 +99,6 @@
 
 	asm volatile (
-		"mf\n"
-		::: "memory"
+	    "mf\n"
+	    ::: "memory"
 	);
 
@@ -109,6 +109,6 @@
 
 	asm volatile (
-		"mf.a\n"
-		::: "memory"
+	    "mf.a\n"
+	    ::: "memory"
 	);
 
@@ -121,6 +121,6 @@
 
 	asm volatile (
-		"mf\n"
-		::: "memory"
+	    "mf\n"
+	    ::: "memory"
 	);
 
@@ -131,6 +131,6 @@
 
 	asm volatile (
-		"mf.a\n"
-		::: "memory"
+	    "mf.a\n"
+	    ::: "memory"
 	);
 
@@ -143,6 +143,6 @@
 
 	asm volatile (
-		"mf\n"
-		::: "memory"
+	    "mf\n"
+	    ::: "memory"
 	);
 
@@ -153,6 +153,6 @@
 
 	asm volatile (
-		"mf.a\n"
-		::: "memory"
+	    "mf.a\n"
+	    ::: "memory"
 	);
 
@@ -171,6 +171,6 @@
 
 	asm volatile (
-		"mov %[value] = r12"
-		: [value] "=r" (value)
+	    "mov %[value] = r12"
+	    : [value] "=r" (value)
 	);
 
@@ -188,6 +188,6 @@
 
 	asm volatile (
-		"mov %[value] = psr\n"
-		: [value] "=r" (v)
+	    "mov %[value] = psr\n"
+	    : [value] "=r" (v)
 	);
 
@@ -205,6 +205,6 @@
 
 	asm volatile (
-		"mov %[value] = cr.iva\n"
-		: [value] "=r" (v)
+	    "mov %[value] = cr.iva\n"
+	    : [value] "=r" (v)
 	);
 
@@ -220,6 +220,6 @@
 {
 	asm volatile (
-		"mov cr.iva = %[value]\n"
-		:: [value] "r" (v)
+	    "mov cr.iva = %[value]\n"
+	    :: [value] "r" (v)
 	);
 }
@@ -236,6 +236,6 @@
 
 	asm volatile (
-		"mov %[value] = cr.ivr\n"
-		: [value] "=r" (v)
+	    "mov %[value] = cr.ivr\n"
+	    : [value] "=r" (v)
 	);
 
@@ -248,6 +248,6 @@
 
 	asm volatile (
-		"mov %[value] = cr64\n"
-		: [value] "=r" (v)
+	    "mov %[value] = cr64\n"
+	    : [value] "=r" (v)
 	);
 
@@ -263,6 +263,6 @@
 {
 	asm volatile (
-		"mov ar.itc = %[value]\n"
-		:: [value] "r" (v)
+	    "mov ar.itc = %[value]\n"
+	    :: [value] "r" (v)
 	);
 }
@@ -278,6 +278,6 @@
 
 	asm volatile (
-		"mov %[value] = ar.itc\n"
-		: [value] "=r" (v)
+	    "mov %[value] = ar.itc\n"
+	    : [value] "=r" (v)
 	);
 
@@ -293,6 +293,6 @@
 {
 	asm volatile (
-		"mov cr.itm = %[value]\n"
-		:: [value] "r" (v)
+	    "mov cr.itm = %[value]\n"
+	    :: [value] "r" (v)
 	);
 }
@@ -308,6 +308,6 @@
 
 	asm volatile (
-		"mov %[value] = cr.itm\n"
-		: [value] "=r" (v)
+	    "mov %[value] = cr.itm\n"
+	    : [value] "=r" (v)
 	);
 
@@ -325,6 +325,6 @@
 
 	asm volatile (
-		"mov %[value] = cr.itv\n"
-		: [value] "=r" (v)
+	    "mov %[value] = cr.itv\n"
+	    : [value] "=r" (v)
 	);
 
@@ -340,6 +340,6 @@
 {
 	asm volatile (
-		"mov cr.itv = %[value]\n"
-		:: [value] "r" (v)
+	    "mov cr.itv = %[value]\n"
+	    :: [value] "r" (v)
 	);
 }
@@ -353,6 +353,6 @@
 {
 	asm volatile (
-		"mov cr.eoi = %[value]\n"
-		:: [value] "r" (v)
+	    "mov cr.eoi = %[value]\n"
+	    :: [value] "r" (v)
 	);
 }
@@ -368,6 +368,6 @@
 
 	asm volatile (
-		"mov %[value] = cr.tpr\n"
-		: [value] "=r" (v)
+	    "mov %[value] = cr.tpr\n"
+	    : [value] "=r" (v)
 	);
 
@@ -383,6 +383,6 @@
 {
 	asm volatile (
-		"mov cr.tpr = %[value]\n"
-		:: [value] "r" (v)
+	    "mov cr.tpr = %[value]\n"
+	    :: [value] "r" (v)
 	);
 }
@@ -401,8 +401,8 @@
 
 	asm volatile (
-		"mov %[value] = psr\n"
-		"rsm %[mask]\n"
-		: [value] "=r" (v)
-		: [mask] "i" (PSR_I_MASK)
+	    "mov %[value] = psr\n"
+	    "rsm %[mask]\n"
+	    : [value] "=r" (v)
+	    : [mask] "i" (PSR_I_MASK)
 	);
 
@@ -423,10 +423,10 @@
 
 	asm volatile (
-		"mov %[value] = psr\n"
-		"ssm %[mask]\n"
-		";;\n"
-		"srlz.d\n"
-		: [value] "=r" (v)
-		: [mask] "i" (PSR_I_MASK)
+	    "mov %[value] = psr\n"
+	    "ssm %[mask]\n"
+	    ";;\n"
+	    "srlz.d\n"
+	    : [value] "=r" (v)
+	    : [mask] "i" (PSR_I_MASK)
 	);
 
@@ -473,8 +473,8 @@
 {
 	asm volatile (
-		"rsm %[mask]\n"
-		";;\n"
-		"srlz.d\n"
-		:: [mask] "i" (PSR_PK_MASK)
+	    "rsm %[mask]\n"
+	    ";;\n"
+	    "srlz.d\n"
+	    :: [mask] "i" (PSR_PK_MASK)
 	);
 }
Index: kernel/arch/ia64/include/arch/atomic.h
===================================================================
--- kernel/arch/ia64/include/arch/atomic.h	(revision fd57745cd4811832fa23ba1cef7638038244f2b5)
+++ kernel/arch/ia64/include/arch/atomic.h	(revision 231c770580f4400a6e0e7612723b1efb16fd5390)
@@ -43,8 +43,8 @@
 
 	asm volatile (
-		"movl %[v] = 0x1;;\n"
-		"xchg8 %[v] = %[count], %[v];;\n"
-		: [v] "=r" (v),
-		  [count] "+m" (val->count)
+	    "movl %[v] = 0x1;;\n"
+	    "xchg8 %[v] = %[count], %[v];;\n"
+	    : [v] "=r" (v),
+	      [count] "+m" (val->count)
 	);
 
@@ -55,5 +55,6 @@
 {
 	do {
-		while (val->count);
+		while (val->count)
+			;
 	} while (test_and_set(val));
 }
@@ -64,7 +65,7 @@
 
 	asm volatile (
-		"fetchadd8.rel %[v] = %[count], 1\n"
-		: [v] "=r" (v),
-		  [count] "+m" (val->count)
+	    "fetchadd8.rel %[v] = %[count], 1\n"
+	    : [v] "=r" (v),
+	      [count] "+m" (val->count)
 	);
 }
@@ -75,7 +76,7 @@
 
 	asm volatile (
-		"fetchadd8.rel %[v] = %[count], -1\n"
-		: [v] "=r" (v),
-		  [count] "+m" (val->count)
+	    "fetchadd8.rel %[v] = %[count], -1\n"
+	    : [v] "=r" (v),
+	      [count] "+m" (val->count)
 	);
 }
@@ -86,7 +87,7 @@
 
 	asm volatile (
-		"fetchadd8.rel %[v] = %[count], 1\n"
-		: [v] "=r" (v),
-		  [count] "+m" (val->count)
+	    "fetchadd8.rel %[v] = %[count], 1\n"
+	    : [v] "=r" (v),
+	      [count] "+m" (val->count)
 	);
 
@@ -99,7 +100,7 @@
 
 	asm volatile (
-		"fetchadd8.rel %[v] = %[count], -1\n"
-		: [v] "=r" (v),
-		  [count] "+m" (val->count)
+	    "fetchadd8.rel %[v] = %[count], -1\n"
+	    : [v] "=r" (v),
+	      [count] "+m" (val->count)
 	);
 
@@ -112,7 +113,7 @@
 
 	asm volatile (
-		"fetchadd8.rel %[v] = %[count], 1\n"
-		: [v] "=r" (v),
-		  [count] "+m" (val->count)
+	    "fetchadd8.rel %[v] = %[count], 1\n"
+	    : [v] "=r" (v),
+	      [count] "+m" (val->count)
 	);
 
@@ -125,7 +126,7 @@
 
 	asm volatile (
-		"fetchadd8.rel %[v] = %[count], -1\n"
-		: [v] "=r" (v),
-		  [count] "+m" (val->count)
+	    "fetchadd8.rel %[v] = %[count], -1\n"
+	    : [v] "=r" (v),
+	      [count] "+m" (val->count)
 	);
 
Index: kernel/arch/ia64/include/arch/cpu.h
===================================================================
--- kernel/arch/ia64/include/arch/cpu.h	(revision fd57745cd4811832fa23ba1cef7638038244f2b5)
+++ kernel/arch/ia64/include/arch/cpu.h	(revision 231c770580f4400a6e0e7612723b1efb16fd5390)
@@ -68,7 +68,7 @@
 
 	asm volatile (
-		"mov %[v] = cpuid[%[r]]\n"
-		: [v] "=r" (v)
-		: [r] "r" (n)
+	    "mov %[v] = cpuid[%[r]]\n"
+	    : [v] "=r" (v)
+	    : [r] "r" (n)
 	);
 
Index: kernel/arch/ia64/include/arch/mm/page.h
===================================================================
--- kernel/arch/ia64/include/arch/mm/page.h	(revision fd57745cd4811832fa23ba1cef7638038244f2b5)
+++ kernel/arch/ia64/include/arch/mm/page.h	(revision 231c770580f4400a6e0e7612723b1efb16fd5390)
@@ -56,7 +56,7 @@
 
 #ifdef __ASSEMBLER__
-	#define VRN_KERNEL  7
+#define VRN_KERNEL  7
 #else
-	#define VRN_KERNEL  7ULL
+#define VRN_KERNEL  7ULL
 #endif
 
@@ -97,5 +97,5 @@
 	unsigned long long tag : 63;
 	unsigned int ti : 1;
-} __attribute__ ((packed));
+} __attribute__((packed));
 
 union vhpt_tag {
@@ -129,5 +129,5 @@
 	/* Word 3 */
 	uint64_t ig3 : 64;
-} __attribute__ ((packed));
+} __attribute__((packed));
 
 struct vhpt_entry_not_present {
@@ -147,5 +147,5 @@
 	/* Word 3 */
 	uint64_t ig3 : 64;
-} __attribute__ ((packed));
+} __attribute__((packed));
 
 typedef union {
@@ -161,5 +161,5 @@
 	unsigned int rid : 24;
 	unsigned int : 32;
-} __attribute__ ((packed));
+} __attribute__((packed));
 
 typedef union {
@@ -175,5 +175,5 @@
 	unsigned int : 6;
 	unsigned long long base : 49;
-} __attribute__ ((packed));
+} __attribute__((packed));
 
 typedef union pta_register {
@@ -196,7 +196,7 @@
 
 	asm volatile (
-		"thash %[ret] = %[va]\n"
-		: [ret] "=r" (ret)
-		: [va] "r" (va)
+	    "thash %[ret] = %[va]\n"
+	    : [ret] "=r" (ret)
+	    : [va] "r" (va)
 	);
 
@@ -218,7 +218,7 @@
 
 	asm volatile (
-		"ttag %[ret] = %[va]\n"
-		: [ret] "=r" (ret)
-		: [va] "r" (va)
+	    "ttag %[ret] = %[va]\n"
+	    : [ret] "=r" (ret)
+	    : [va] "r" (va)
 	);
 
@@ -239,7 +239,7 @@
 
 	asm volatile (
-		"mov %[ret] = rr[%[index]]\n"
-		: [ret] "=r" (ret)
-		: [index] "r" (i << VRN_SHIFT)
+	    "mov %[ret] = rr[%[index]]\n"
+	    : [ret] "=r" (ret)
+	    : [index] "r" (i << VRN_SHIFT)
 	);
 
@@ -257,7 +257,7 @@
 
 	asm volatile (
-		"mov rr[%[index]] = %[value]\n"
-		:: [index] "r" (i << VRN_SHIFT),
-		   [value] "r" (v)
+	    "mov rr[%[index]] = %[value]\n"
+	    :: [index] "r" (i << VRN_SHIFT),
+	      [value] "r" (v)
 	);
 }
@@ -272,6 +272,6 @@
 
 	asm volatile (
-		"mov %[ret] = cr.pta\n"
-		: [ret] "=r" (ret)
+	    "mov %[ret] = cr.pta\n"
+	    : [ret] "=r" (ret)
 	);
 
@@ -286,6 +286,6 @@
 {
 	asm volatile (
-		"mov cr.pta = %[value]\n"
-		:: [value] "r" (v)
+	    "mov cr.pta = %[value]\n"
+	    :: [value] "r" (v)
 	);
 }
Index: kernel/arch/ia64/include/arch/mm/tlb.h
===================================================================
--- kernel/arch/ia64/include/arch/mm/tlb.h	(revision fd57745cd4811832fa23ba1cef7638038244f2b5)
+++ kernel/arch/ia64/include/arch/mm/tlb.h	(revision 231c770580f4400a6e0e7612723b1efb16fd5390)
@@ -69,6 +69,6 @@
 		unsigned int key : 24;  /**< Protection key, unused. */
 		unsigned int : 32;
-	} __attribute__ ((packed));
-} __attribute__ ((packed)) tlb_entry_t;
+	} __attribute__((packed));
+} __attribute__((packed)) tlb_entry_t;
 
 extern void tc_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry, bool dtc);
Index: kernel/arch/ia64/include/arch/register.h
===================================================================
--- kernel/arch/ia64/include/arch/register.h	(revision fd57745cd4811832fa23ba1cef7638038244f2b5)
+++ kernel/arch/ia64/include/arch/register.h	(revision 231c770580f4400a6e0e7612723b1efb16fd5390)
@@ -184,5 +184,5 @@
 		unsigned int bn : 1;   /**< Register Bank. */
 		unsigned int ia : 1;   /**< Disable Instruction Access-bit faults. */
-	} __attribute__ ((packed));
+	} __attribute__((packed));
 } psr_t;
 
@@ -196,5 +196,5 @@
 		unsigned int : 11;
 		unsigned int loadrs : 14;
-	} __attribute__ ((packed));
+	} __attribute__((packed));
 } rsc_t;
 
@@ -210,8 +210,8 @@
 	struct {
 		unsigned int : 4;
-		unsigned int mic: 4;  /**< Mask Interrupt Class. */
+		unsigned int mic : 4;  /**< Mask Interrupt Class. */
 		unsigned int : 8;
-		unsigned int mmi: 1;  /**< Mask Maskable Interrupts. */
-	} __attribute__ ((packed));
+		unsigned int mmi : 1;  /**< Mask Maskable Interrupts. */
+	} __attribute__((packed));
 } cr_tpr_t;
 
@@ -225,5 +225,5 @@
 		unsigned int : 3;
 		unsigned int m : 1;       /**< Mask. */
-	} __attribute__ ((packed));
+	} __attribute__((packed));
 } cr_itv_t;
 
@@ -238,5 +238,5 @@
 				unsigned int ge_na : 4;
 				unsigned int ge_code : 4;
-			} __attribute__ ((packed));
+			} __attribute__((packed));
 		};
 		uint8_t vector;
@@ -254,5 +254,5 @@
 		unsigned int ed : 1;  /**< Exception Deferral. */
 		unsigned int : 20;
-	} __attribute__ ((packed));
+	} __attribute__((packed));
 } cr_isr_t;
 
@@ -266,5 +266,5 @@
 		uint8_t family;
 		uint8_t archrev;
-	} __attribute__ ((packed));
+	} __attribute__((packed));
 } cpuid3_t;
 
Index: kernel/arch/ia64/src/fpu_context.c
===================================================================
--- kernel/arch/ia64/src/fpu_context.c	(revision fd57745cd4811832fa23ba1cef7638038244f2b5)
+++ kernel/arch/ia64/src/fpu_context.c	(revision 231c770580f4400a6e0e7612723b1efb16fd5390)
@@ -41,209 +41,209 @@
 {
 	asm volatile (
-		"stf.spill %[f32] = f32\n"
-		"stf.spill %[f33] = f33\n"
-		"stf.spill %[f34] = f34\n"
-		"stf.spill %[f35] = f35\n"
-		"stf.spill %[f36] = f36\n"
-		"stf.spill %[f37] = f37\n"
-		"stf.spill %[f38] = f38\n"
-		"stf.spill %[f39] = f39\n"
-		"stf.spill %[f40] = f40\n"
-		"stf.spill %[f41] = f41\n"
-		"stf.spill %[f42] = f42\n"
-		"stf.spill %[f43] = f43\n"
-		"stf.spill %[f44] = f44\n"
-		"stf.spill %[f45] = f45\n"
-		"stf.spill %[f46] = f46\n"
-		"stf.spill %[f47] = f47\n"
-		"stf.spill %[f48] = f48\n"
-		"stf.spill %[f49] = f49\n"
-		"stf.spill %[f50] = f50\n"
-		"stf.spill %[f51] = f51\n"
-		"stf.spill %[f52] = f52\n"
-		"stf.spill %[f53] = f53\n"
-		"stf.spill %[f54] = f54\n"
-		"stf.spill %[f55] = f55\n"
-		"stf.spill %[f56] = f56\n"
-		"stf.spill %[f57] = f57\n"
-		"stf.spill %[f58] = f58\n"
-		"stf.spill %[f59] = f59\n"
-		"stf.spill %[f60] = f60\n"
-		"stf.spill %[f61] = f61\n"
-		:
-		[f32] "=m" (fctx->fr[0]),
-		[f33] "=m" (fctx->fr[1]),
-		[f34] "=m" (fctx->fr[2]),
-		[f35] "=m" (fctx->fr[3]),
-		[f36] "=m" (fctx->fr[4]),
-		[f37] "=m" (fctx->fr[5]),
-		[f38] "=m" (fctx->fr[6]),
-		[f39] "=m" (fctx->fr[7]),
-		[f40] "=m" (fctx->fr[8]),
-		[f41] "=m" (fctx->fr[9]),
-		[f42] "=m" (fctx->fr[10]),
-		[f43] "=m" (fctx->fr[11]),
-		[f44] "=m" (fctx->fr[12]),
-		[f45] "=m" (fctx->fr[13]),
-		[f46] "=m" (fctx->fr[14]),
-		[f47] "=m" (fctx->fr[15]),
-		[f48] "=m" (fctx->fr[16]),
-		[f49] "=m" (fctx->fr[17]),
-		[f50] "=m" (fctx->fr[18]),
-		[f51] "=m" (fctx->fr[19]),
-		[f52] "=m" (fctx->fr[20]),
-		[f53] "=m" (fctx->fr[21]),
-		[f54] "=m" (fctx->fr[22]),
-		[f55] "=m" (fctx->fr[23]),
-		[f56] "=m" (fctx->fr[24]),
-		[f57] "=m" (fctx->fr[25]),
-		[f58] "=m" (fctx->fr[26]),
-		[f59] "=m" (fctx->fr[27]),
-		[f60] "=m" (fctx->fr[28]),
-		[f61] "=m" (fctx->fr[29])
-	);
-
-	asm volatile (
-		"stf.spill %[f62] = f62\n"
-		"stf.spill %[f63] = f63\n"
-		"stf.spill %[f64] = f64\n"
-		"stf.spill %[f65] = f65\n"
-		"stf.spill %[f66] = f66\n"
-		"stf.spill %[f67] = f67\n"
-		"stf.spill %[f68] = f68\n"
-		"stf.spill %[f69] = f69\n"
-		"stf.spill %[f70] = f70\n"
-		"stf.spill %[f71] = f71\n"
-		"stf.spill %[f72] = f72\n"
-		"stf.spill %[f73] = f73\n"
-		"stf.spill %[f74] = f74\n"
-		"stf.spill %[f75] = f75\n"
-		"stf.spill %[f76] = f76\n"
-		"stf.spill %[f77] = f77\n"
-		"stf.spill %[f78] = f78\n"
-		"stf.spill %[f79] = f79\n"
-		"stf.spill %[f80] = f80\n"
-		"stf.spill %[f81] = f81\n"
-		"stf.spill %[f82] = f82\n"
-		"stf.spill %[f83] = f83\n"
-		"stf.spill %[f84] = f84\n"
-		"stf.spill %[f85] = f85\n"
-		"stf.spill %[f86] = f86\n"
-		"stf.spill %[f87] = f87\n"
-		"stf.spill %[f88] = f88\n"
-		"stf.spill %[f89] = f89\n"
-		"stf.spill %[f90] = f90\n"
-		"stf.spill %[f91] = f91\n"
-		:
-		[f62] "=m" (fctx->fr[30]),
-		[f63] "=m" (fctx->fr[31]),
-		[f64] "=m" (fctx->fr[32]),
-		[f65] "=m" (fctx->fr[33]),
-		[f66] "=m" (fctx->fr[34]),
-		[f67] "=m" (fctx->fr[35]),
-		[f68] "=m" (fctx->fr[36]),
-		[f69] "=m" (fctx->fr[37]),
-		[f70] "=m" (fctx->fr[38]),
-		[f71] "=m" (fctx->fr[39]),
-		[f72] "=m" (fctx->fr[40]),
-		[f73] "=m" (fctx->fr[41]),
-		[f74] "=m" (fctx->fr[42]),
-		[f75] "=m" (fctx->fr[43]),
-		[f76] "=m" (fctx->fr[44]),
-		[f77] "=m" (fctx->fr[45]),
-		[f78] "=m" (fctx->fr[46]),
-		[f79] "=m" (fctx->fr[47]),
-		[f80] "=m" (fctx->fr[48]),
-		[f81] "=m" (fctx->fr[49]),
-		[f82] "=m" (fctx->fr[50]),
-		[f83] "=m" (fctx->fr[51]),
-		[f84] "=m" (fctx->fr[52]),
-		[f85] "=m" (fctx->fr[53]),
-		[f86] "=m" (fctx->fr[54]),
-		[f87] "=m" (fctx->fr[55]),
-		[f88] "=m" (fctx->fr[56]),
-		[f89] "=m" (fctx->fr[57]),
-		[f90] "=m" (fctx->fr[58]),
-		[f91] "=m" (fctx->fr[59])
-	);
-
-	asm volatile (
-		"stf.spill %[f92] = f92\n"
-		"stf.spill %[f93] = f93\n"
-		"stf.spill %[f94] = f94\n"
-		"stf.spill %[f95] = f95\n"
-		"stf.spill %[f96] = f96\n"
-		"stf.spill %[f97] = f97\n"
-		"stf.spill %[f98] = f98\n"
-		"stf.spill %[f99] = f99\n"
-		"stf.spill %[f100] = f100\n"
-		"stf.spill %[f101] = f101\n"
-		"stf.spill %[f102] = f102\n"
-		"stf.spill %[f103] = f103\n"
-		"stf.spill %[f104] = f104\n"
-		"stf.spill %[f105] = f105\n"
-		"stf.spill %[f106] = f106\n"
-		"stf.spill %[f107] = f107\n"
-		"stf.spill %[f108] = f108\n"
-		"stf.spill %[f109] = f109\n"
-		"stf.spill %[f110] = f110\n"
-		"stf.spill %[f111] = f111\n"
-		"stf.spill %[f112] = f112\n"
-		"stf.spill %[f113] = f113\n"
-		"stf.spill %[f114] = f114\n"
-		"stf.spill %[f115] = f115\n"
-		"stf.spill %[f116] = f116\n"
-		"stf.spill %[f117] = f117\n"
-		"stf.spill %[f118] = f118\n"
-		"stf.spill %[f119] = f119\n"
-		"stf.spill %[f120] = f120\n"
-		"stf.spill %[f121] = f121\n"
-		:
-		[f92] "=m" (fctx->fr[60]),
-		[f93] "=m" (fctx->fr[61]),
-		[f94] "=m" (fctx->fr[62]),
-		[f95] "=m" (fctx->fr[63]),
-		[f96] "=m" (fctx->fr[64]),
-		[f97] "=m" (fctx->fr[65]),
-		[f98] "=m" (fctx->fr[66]),
-		[f99] "=m" (fctx->fr[67]),
-		[f100] "=m" (fctx->fr[68]),
-		[f101] "=m" (fctx->fr[69]),
-		[f102] "=m" (fctx->fr[70]),
-		[f103] "=m" (fctx->fr[71]),
-		[f104] "=m" (fctx->fr[72]),
-		[f105] "=m" (fctx->fr[73]),
-		[f106] "=m" (fctx->fr[74]),
-		[f107] "=m" (fctx->fr[75]),
-		[f108] "=m" (fctx->fr[76]),
-		[f109] "=m" (fctx->fr[77]),
-		[f110] "=m" (fctx->fr[78]),
-		[f111] "=m" (fctx->fr[79]),
-		[f112] "=m" (fctx->fr[80]),
-		[f113] "=m" (fctx->fr[81]),
-		[f114] "=m" (fctx->fr[82]),
-		[f115] "=m" (fctx->fr[83]),
-		[f116] "=m" (fctx->fr[84]),
-		[f117] "=m" (fctx->fr[85]),
-		[f118] "=m" (fctx->fr[86]),
-		[f119] "=m" (fctx->fr[87]),
-		[f120] "=m" (fctx->fr[88]),
-		[f121] "=m" (fctx->fr[89])
-	);
-
-	asm volatile (
-		"stf.spill %[f122] = f122\n"
-		"stf.spill %[f123] = f123\n"
-		"stf.spill %[f124] = f124\n"
-		"stf.spill %[f125] = f125\n"
-		"stf.spill %[f126] = f126\n"
-		"stf.spill %[f127] = f127\n"
-		:
-		[f122] "=m" (fctx->fr[90]),
-		[f123] "=m" (fctx->fr[91]),
-		[f124] "=m" (fctx->fr[92]),
-		[f125] "=m" (fctx->fr[93]),
-		[f126] "=m" (fctx->fr[94]),
-		[f127] "=m" (fctx->fr[95])
+	    "stf.spill %[f32] = f32\n"
+	    "stf.spill %[f33] = f33\n"
+	    "stf.spill %[f34] = f34\n"
+	    "stf.spill %[f35] = f35\n"
+	    "stf.spill %[f36] = f36\n"
+	    "stf.spill %[f37] = f37\n"
+	    "stf.spill %[f38] = f38\n"
+	    "stf.spill %[f39] = f39\n"
+	    "stf.spill %[f40] = f40\n"
+	    "stf.spill %[f41] = f41\n"
+	    "stf.spill %[f42] = f42\n"
+	    "stf.spill %[f43] = f43\n"
+	    "stf.spill %[f44] = f44\n"
+	    "stf.spill %[f45] = f45\n"
+	    "stf.spill %[f46] = f46\n"
+	    "stf.spill %[f47] = f47\n"
+	    "stf.spill %[f48] = f48\n"
+	    "stf.spill %[f49] = f49\n"
+	    "stf.spill %[f50] = f50\n"
+	    "stf.spill %[f51] = f51\n"
+	    "stf.spill %[f52] = f52\n"
+	    "stf.spill %[f53] = f53\n"
+	    "stf.spill %[f54] = f54\n"
+	    "stf.spill %[f55] = f55\n"
+	    "stf.spill %[f56] = f56\n"
+	    "stf.spill %[f57] = f57\n"
+	    "stf.spill %[f58] = f58\n"
+	    "stf.spill %[f59] = f59\n"
+	    "stf.spill %[f60] = f60\n"
+	    "stf.spill %[f61] = f61\n"
+	    :
+	      [f32] "=m" (fctx->fr[0]),
+	      [f33] "=m" (fctx->fr[1]),
+	      [f34] "=m" (fctx->fr[2]),
+	      [f35] "=m" (fctx->fr[3]),
+	      [f36] "=m" (fctx->fr[4]),
+	      [f37] "=m" (fctx->fr[5]),
+	      [f38] "=m" (fctx->fr[6]),
+	      [f39] "=m" (fctx->fr[7]),
+	      [f40] "=m" (fctx->fr[8]),
+	      [f41] "=m" (fctx->fr[9]),
+	      [f42] "=m" (fctx->fr[10]),
+	      [f43] "=m" (fctx->fr[11]),
+	      [f44] "=m" (fctx->fr[12]),
+	      [f45] "=m" (fctx->fr[13]),
+	      [f46] "=m" (fctx->fr[14]),
+	      [f47] "=m" (fctx->fr[15]),
+	      [f48] "=m" (fctx->fr[16]),
+	      [f49] "=m" (fctx->fr[17]),
+	      [f50] "=m" (fctx->fr[18]),
+	      [f51] "=m" (fctx->fr[19]),
+	      [f52] "=m" (fctx->fr[20]),
+	      [f53] "=m" (fctx->fr[21]),
+	      [f54] "=m" (fctx->fr[22]),
+	      [f55] "=m" (fctx->fr[23]),
+	      [f56] "=m" (fctx->fr[24]),
+	      [f57] "=m" (fctx->fr[25]),
+	      [f58] "=m" (fctx->fr[26]),
+	      [f59] "=m" (fctx->fr[27]),
+	      [f60] "=m" (fctx->fr[28]),
+	      [f61] "=m" (fctx->fr[29])
+	);
+
+	asm volatile (
+	    "stf.spill %[f62] = f62\n"
+	    "stf.spill %[f63] = f63\n"
+	    "stf.spill %[f64] = f64\n"
+	    "stf.spill %[f65] = f65\n"
+	    "stf.spill %[f66] = f66\n"
+	    "stf.spill %[f67] = f67\n"
+	    "stf.spill %[f68] = f68\n"
+	    "stf.spill %[f69] = f69\n"
+	    "stf.spill %[f70] = f70\n"
+	    "stf.spill %[f71] = f71\n"
+	    "stf.spill %[f72] = f72\n"
+	    "stf.spill %[f73] = f73\n"
+	    "stf.spill %[f74] = f74\n"
+	    "stf.spill %[f75] = f75\n"
+	    "stf.spill %[f76] = f76\n"
+	    "stf.spill %[f77] = f77\n"
+	    "stf.spill %[f78] = f78\n"
+	    "stf.spill %[f79] = f79\n"
+	    "stf.spill %[f80] = f80\n"
+	    "stf.spill %[f81] = f81\n"
+	    "stf.spill %[f82] = f82\n"
+	    "stf.spill %[f83] = f83\n"
+	    "stf.spill %[f84] = f84\n"
+	    "stf.spill %[f85] = f85\n"
+	    "stf.spill %[f86] = f86\n"
+	    "stf.spill %[f87] = f87\n"
+	    "stf.spill %[f88] = f88\n"
+	    "stf.spill %[f89] = f89\n"
+	    "stf.spill %[f90] = f90\n"
+	    "stf.spill %[f91] = f91\n"
+	    :
+	      [f62] "=m" (fctx->fr[30]),
+	      [f63] "=m" (fctx->fr[31]),
+	      [f64] "=m" (fctx->fr[32]),
+	      [f65] "=m" (fctx->fr[33]),
+	      [f66] "=m" (fctx->fr[34]),
+	      [f67] "=m" (fctx->fr[35]),
+	      [f68] "=m" (fctx->fr[36]),
+	      [f69] "=m" (fctx->fr[37]),
+	      [f70] "=m" (fctx->fr[38]),
+	      [f71] "=m" (fctx->fr[39]),
+	      [f72] "=m" (fctx->fr[40]),
+	      [f73] "=m" (fctx->fr[41]),
+	      [f74] "=m" (fctx->fr[42]),
+	      [f75] "=m" (fctx->fr[43]),
+	      [f76] "=m" (fctx->fr[44]),
+	      [f77] "=m" (fctx->fr[45]),
+	      [f78] "=m" (fctx->fr[46]),
+	      [f79] "=m" (fctx->fr[47]),
+	      [f80] "=m" (fctx->fr[48]),
+	      [f81] "=m" (fctx->fr[49]),
+	      [f82] "=m" (fctx->fr[50]),
+	      [f83] "=m" (fctx->fr[51]),
+	      [f84] "=m" (fctx->fr[52]),
+	      [f85] "=m" (fctx->fr[53]),
+	      [f86] "=m" (fctx->fr[54]),
+	      [f87] "=m" (fctx->fr[55]),
+	      [f88] "=m" (fctx->fr[56]),
+	      [f89] "=m" (fctx->fr[57]),
+	      [f90] "=m" (fctx->fr[58]),
+	      [f91] "=m" (fctx->fr[59])
+	);
+
+	asm volatile (
+	    "stf.spill %[f92] = f92\n"
+	    "stf.spill %[f93] = f93\n"
+	    "stf.spill %[f94] = f94\n"
+	    "stf.spill %[f95] = f95\n"
+	    "stf.spill %[f96] = f96\n"
+	    "stf.spill %[f97] = f97\n"
+	    "stf.spill %[f98] = f98\n"
+	    "stf.spill %[f99] = f99\n"
+	    "stf.spill %[f100] = f100\n"
+	    "stf.spill %[f101] = f101\n"
+	    "stf.spill %[f102] = f102\n"
+	    "stf.spill %[f103] = f103\n"
+	    "stf.spill %[f104] = f104\n"
+	    "stf.spill %[f105] = f105\n"
+	    "stf.spill %[f106] = f106\n"
+	    "stf.spill %[f107] = f107\n"
+	    "stf.spill %[f108] = f108\n"
+	    "stf.spill %[f109] = f109\n"
+	    "stf.spill %[f110] = f110\n"
+	    "stf.spill %[f111] = f111\n"
+	    "stf.spill %[f112] = f112\n"
+	    "stf.spill %[f113] = f113\n"
+	    "stf.spill %[f114] = f114\n"
+	    "stf.spill %[f115] = f115\n"
+	    "stf.spill %[f116] = f116\n"
+	    "stf.spill %[f117] = f117\n"
+	    "stf.spill %[f118] = f118\n"
+	    "stf.spill %[f119] = f119\n"
+	    "stf.spill %[f120] = f120\n"
+	    "stf.spill %[f121] = f121\n"
+	    :
+	      [f92] "=m" (fctx->fr[60]),
+	      [f93] "=m" (fctx->fr[61]),
+	      [f94] "=m" (fctx->fr[62]),
+	      [f95] "=m" (fctx->fr[63]),
+	      [f96] "=m" (fctx->fr[64]),
+	      [f97] "=m" (fctx->fr[65]),
+	      [f98] "=m" (fctx->fr[66]),
+	      [f99] "=m" (fctx->fr[67]),
+	      [f100] "=m" (fctx->fr[68]),
+	      [f101] "=m" (fctx->fr[69]),
+	      [f102] "=m" (fctx->fr[70]),
+	      [f103] "=m" (fctx->fr[71]),
+	      [f104] "=m" (fctx->fr[72]),
+	      [f105] "=m" (fctx->fr[73]),
+	      [f106] "=m" (fctx->fr[74]),
+	      [f107] "=m" (fctx->fr[75]),
+	      [f108] "=m" (fctx->fr[76]),
+	      [f109] "=m" (fctx->fr[77]),
+	      [f110] "=m" (fctx->fr[78]),
+	      [f111] "=m" (fctx->fr[79]),
+	      [f112] "=m" (fctx->fr[80]),
+	      [f113] "=m" (fctx->fr[81]),
+	      [f114] "=m" (fctx->fr[82]),
+	      [f115] "=m" (fctx->fr[83]),
+	      [f116] "=m" (fctx->fr[84]),
+	      [f117] "=m" (fctx->fr[85]),
+	      [f118] "=m" (fctx->fr[86]),
+	      [f119] "=m" (fctx->fr[87]),
+	      [f120] "=m" (fctx->fr[88]),
+	      [f121] "=m" (fctx->fr[89])
+	);
+
+	asm volatile (
+	    "stf.spill %[f122] = f122\n"
+	    "stf.spill %[f123] = f123\n"
+	    "stf.spill %[f124] = f124\n"
+	    "stf.spill %[f125] = f125\n"
+	    "stf.spill %[f126] = f126\n"
+	    "stf.spill %[f127] = f127\n"
+	    :
+	      [f122] "=m" (fctx->fr[90]),
+	      [f123] "=m" (fctx->fr[91]),
+	      [f124] "=m" (fctx->fr[92]),
+	      [f125] "=m" (fctx->fr[93]),
+	      [f126] "=m" (fctx->fr[94]),
+	      [f127] "=m" (fctx->fr[95])
 	);
 }
@@ -252,209 +252,209 @@
 {
 	asm volatile (
-		"ldf.fill f32 = %[f32]\n"
-		"ldf.fill f33 = %[f33]\n"
-		"ldf.fill f34 = %[f34]\n"
-		"ldf.fill f35 = %[f35]\n"
-		"ldf.fill f36 = %[f36]\n"
-		"ldf.fill f37 = %[f37]\n"
-		"ldf.fill f38 = %[f38]\n"
-		"ldf.fill f39 = %[f39]\n"
-		"ldf.fill f40 = %[f40]\n"
-		"ldf.fill f41 = %[f41]\n"
-		"ldf.fill f42 = %[f42]\n"
-		"ldf.fill f43 = %[f43]\n"
-		"ldf.fill f44 = %[f44]\n"
-		"ldf.fill f45 = %[f45]\n"
-		"ldf.fill f46 = %[f46]\n"
-		"ldf.fill f47 = %[f47]\n"
-		"ldf.fill f48 = %[f48]\n"
-		"ldf.fill f49 = %[f49]\n"
-		"ldf.fill f50 = %[f50]\n"
-		"ldf.fill f51 = %[f51]\n"
-		"ldf.fill f52 = %[f52]\n"
-		"ldf.fill f53 = %[f53]\n"
-		"ldf.fill f54 = %[f54]\n"
-		"ldf.fill f55 = %[f55]\n"
-		"ldf.fill f56 = %[f56]\n"
-		"ldf.fill f57 = %[f57]\n"
-		"ldf.fill f58 = %[f58]\n"
-		"ldf.fill f59 = %[f59]\n"
-		"ldf.fill f60 = %[f60]\n"
-		"ldf.fill f61 = %[f61]\n"
-		::
-		[f32] "m" (fctx->fr[0]),
-		[f33] "m" (fctx->fr[1]),
-		[f34] "m" (fctx->fr[2]),
-		[f35] "m" (fctx->fr[3]),
-		[f36] "m" (fctx->fr[4]),
-		[f37] "m" (fctx->fr[5]),
-		[f38] "m" (fctx->fr[6]),
-		[f39] "m" (fctx->fr[7]),
-		[f40] "m" (fctx->fr[8]),
-		[f41] "m" (fctx->fr[9]),
-		[f42] "m" (fctx->fr[10]),
-		[f43] "m" (fctx->fr[11]),
-		[f44] "m" (fctx->fr[12]),
-		[f45] "m" (fctx->fr[13]),
-		[f46] "m" (fctx->fr[14]),
-		[f47] "m" (fctx->fr[15]),
-		[f48] "m" (fctx->fr[16]),
-		[f49] "m" (fctx->fr[17]),
-		[f50] "m" (fctx->fr[18]),
-		[f51] "m" (fctx->fr[19]),
-		[f52] "m" (fctx->fr[20]),
-		[f53] "m" (fctx->fr[21]),
-		[f54] "m" (fctx->fr[22]),
-		[f55] "m" (fctx->fr[23]),
-		[f56] "m" (fctx->fr[24]),
-		[f57] "m" (fctx->fr[25]),
-		[f58] "m" (fctx->fr[26]),
-		[f59] "m" (fctx->fr[27]),
-		[f60] "m" (fctx->fr[28]),
-		[f61] "m" (fctx->fr[29])
-	);
-
-	asm volatile (
-		"ldf.fill f62 = %[f62]\n"
-		"ldf.fill f63 = %[f63]\n"
-		"ldf.fill f64 = %[f64]\n"
-		"ldf.fill f65 = %[f65]\n"
-		"ldf.fill f66 = %[f66]\n"
-		"ldf.fill f67 = %[f67]\n"
-		"ldf.fill f68 = %[f68]\n"
-		"ldf.fill f69 = %[f69]\n"
-		"ldf.fill f70 = %[f70]\n"
-		"ldf.fill f71 = %[f71]\n"
-		"ldf.fill f72 = %[f72]\n"
-		"ldf.fill f73 = %[f73]\n"
-		"ldf.fill f74 = %[f74]\n"
-		"ldf.fill f75 = %[f75]\n"
-		"ldf.fill f76 = %[f76]\n"
-		"ldf.fill f77 = %[f77]\n"
-		"ldf.fill f78 = %[f78]\n"
-		"ldf.fill f79 = %[f79]\n"
-		"ldf.fill f80 = %[f80]\n"
-		"ldf.fill f81 = %[f81]\n"
-		"ldf.fill f82 = %[f82]\n"
-		"ldf.fill f83 = %[f83]\n"
-		"ldf.fill f84 = %[f84]\n"
-		"ldf.fill f85 = %[f85]\n"
-		"ldf.fill f86 = %[f86]\n"
-		"ldf.fill f87 = %[f87]\n"
-		"ldf.fill f88 = %[f88]\n"
-		"ldf.fill f89 = %[f89]\n"
-		"ldf.fill f90 = %[f90]\n"
-		"ldf.fill f91 = %[f91]\n"
-		::
-		[f62] "m" (fctx->fr[30]),
-		[f63] "m" (fctx->fr[31]),
-		[f64] "m" (fctx->fr[32]),
-		[f65] "m" (fctx->fr[33]),
-		[f66] "m" (fctx->fr[34]),
-		[f67] "m" (fctx->fr[35]),
-		[f68] "m" (fctx->fr[36]),
-		[f69] "m" (fctx->fr[37]),
-		[f70] "m" (fctx->fr[38]),
-		[f71] "m" (fctx->fr[39]),
-		[f72] "m" (fctx->fr[40]),
-		[f73] "m" (fctx->fr[41]),
-		[f74] "m" (fctx->fr[42]),
-		[f75] "m" (fctx->fr[43]),
-		[f76] "m" (fctx->fr[44]),
-		[f77] "m" (fctx->fr[45]),
-		[f78] "m" (fctx->fr[46]),
-		[f79] "m" (fctx->fr[47]),
-		[f80] "m" (fctx->fr[48]),
-		[f81] "m" (fctx->fr[49]),
-		[f82] "m" (fctx->fr[50]),
-		[f83] "m" (fctx->fr[51]),
-		[f84] "m" (fctx->fr[52]),
-		[f85] "m" (fctx->fr[53]),
-		[f86] "m" (fctx->fr[54]),
-		[f87] "m" (fctx->fr[55]),
-		[f88] "m" (fctx->fr[56]),
-		[f89] "m" (fctx->fr[57]),
-		[f90] "m" (fctx->fr[58]),
-		[f91] "m" (fctx->fr[59])
-	);
-
-	asm volatile (
-		"ldf.fill f92 = %[f92]\n"
-		"ldf.fill f93 = %[f93]\n"
-		"ldf.fill f94 = %[f94]\n"
-		"ldf.fill f95 = %[f95]\n"
-		"ldf.fill f96 = %[f96]\n"
-		"ldf.fill f97 = %[f97]\n"
-		"ldf.fill f98 = %[f98]\n"
-		"ldf.fill f99 = %[f99]\n"
-		"ldf.fill f100 = %[f100]\n"
-		"ldf.fill f101 = %[f101]\n"
-		"ldf.fill f102 = %[f102]\n"
-		"ldf.fill f103 = %[f103]\n"
-		"ldf.fill f104 = %[f104]\n"
-		"ldf.fill f105 = %[f105]\n"
-		"ldf.fill f106 = %[f106]\n"
-		"ldf.fill f107 = %[f107]\n"
-		"ldf.fill f108 = %[f108]\n"
-		"ldf.fill f109 = %[f109]\n"
-		"ldf.fill f110 = %[f110]\n"
-		"ldf.fill f111 = %[f111]\n"
-		"ldf.fill f112 = %[f112]\n"
-		"ldf.fill f113 = %[f113]\n"
-		"ldf.fill f114 = %[f114]\n"
-		"ldf.fill f115 = %[f115]\n"
-		"ldf.fill f116 = %[f116]\n"
-		"ldf.fill f117 = %[f117]\n"
-		"ldf.fill f118 = %[f118]\n"
-		"ldf.fill f119 = %[f119]\n"
-		"ldf.fill f120 = %[f120]\n"
-		"ldf.fill f121 = %[f121]\n"
-		::
-		[f92] "m" (fctx->fr[60]),
-		[f93] "m" (fctx->fr[61]),
-		[f94] "m" (fctx->fr[62]),
-		[f95] "m" (fctx->fr[63]),
-		[f96] "m" (fctx->fr[64]),
-		[f97] "m" (fctx->fr[65]),
-		[f98] "m" (fctx->fr[66]),
-		[f99] "m" (fctx->fr[67]),
-		[f100] "m" (fctx->fr[68]),
-		[f101] "m" (fctx->fr[69]),
-		[f102] "m" (fctx->fr[70]),
-		[f103] "m" (fctx->fr[71]),
-		[f104] "m" (fctx->fr[72]),
-		[f105] "m" (fctx->fr[73]),
-		[f106] "m" (fctx->fr[74]),
-		[f107] "m" (fctx->fr[75]),
-		[f108] "m" (fctx->fr[76]),
-		[f109] "m" (fctx->fr[77]),
-		[f110] "m" (fctx->fr[78]),
-		[f111] "m" (fctx->fr[79]),
-		[f112] "m" (fctx->fr[80]),
-		[f113] "m" (fctx->fr[81]),
-		[f114] "m" (fctx->fr[82]),
-		[f115] "m" (fctx->fr[83]),
-		[f116] "m" (fctx->fr[84]),
-		[f117] "m" (fctx->fr[85]),
-		[f118] "m" (fctx->fr[86]),
-		[f119] "m" (fctx->fr[87]),
-		[f120] "m" (fctx->fr[88]),
-		[f121] "m" (fctx->fr[89])
-	);
-
-	asm volatile (
-		"ldf.fill f122 = %[f122]\n"
-		"ldf.fill f123 = %[f123]\n"
-		"ldf.fill f124 = %[f124]\n"
-		"ldf.fill f125 = %[f125]\n"
-		"ldf.fill f126 = %[f126]\n"
-		"ldf.fill f127 = %[f127]\n"
-		::
-		[f122] "m" (fctx->fr[90]),
-		[f123] "m" (fctx->fr[91]),
-		[f124] "m" (fctx->fr[92]),
-		[f125] "m" (fctx->fr[93]),
-		[f126] "m" (fctx->fr[94]),
-		[f127] "m" (fctx->fr[95])
+	    "ldf.fill f32 = %[f32]\n"
+	    "ldf.fill f33 = %[f33]\n"
+	    "ldf.fill f34 = %[f34]\n"
+	    "ldf.fill f35 = %[f35]\n"
+	    "ldf.fill f36 = %[f36]\n"
+	    "ldf.fill f37 = %[f37]\n"
+	    "ldf.fill f38 = %[f38]\n"
+	    "ldf.fill f39 = %[f39]\n"
+	    "ldf.fill f40 = %[f40]\n"
+	    "ldf.fill f41 = %[f41]\n"
+	    "ldf.fill f42 = %[f42]\n"
+	    "ldf.fill f43 = %[f43]\n"
+	    "ldf.fill f44 = %[f44]\n"
+	    "ldf.fill f45 = %[f45]\n"
+	    "ldf.fill f46 = %[f46]\n"
+	    "ldf.fill f47 = %[f47]\n"
+	    "ldf.fill f48 = %[f48]\n"
+	    "ldf.fill f49 = %[f49]\n"
+	    "ldf.fill f50 = %[f50]\n"
+	    "ldf.fill f51 = %[f51]\n"
+	    "ldf.fill f52 = %[f52]\n"
+	    "ldf.fill f53 = %[f53]\n"
+	    "ldf.fill f54 = %[f54]\n"
+	    "ldf.fill f55 = %[f55]\n"
+	    "ldf.fill f56 = %[f56]\n"
+	    "ldf.fill f57 = %[f57]\n"
+	    "ldf.fill f58 = %[f58]\n"
+	    "ldf.fill f59 = %[f59]\n"
+	    "ldf.fill f60 = %[f60]\n"
+	    "ldf.fill f61 = %[f61]\n"
+	    ::
+	      [f32] "m" (fctx->fr[0]),
+	      [f33] "m" (fctx->fr[1]),
+	      [f34] "m" (fctx->fr[2]),
+	      [f35] "m" (fctx->fr[3]),
+	      [f36] "m" (fctx->fr[4]),
+	      [f37] "m" (fctx->fr[5]),
+	      [f38] "m" (fctx->fr[6]),
+	      [f39] "m" (fctx->fr[7]),
+	      [f40] "m" (fctx->fr[8]),
+	      [f41] "m" (fctx->fr[9]),
+	      [f42] "m" (fctx->fr[10]),
+	      [f43] "m" (fctx->fr[11]),
+	      [f44] "m" (fctx->fr[12]),
+	      [f45] "m" (fctx->fr[13]),
+	      [f46] "m" (fctx->fr[14]),
+	      [f47] "m" (fctx->fr[15]),
+	      [f48] "m" (fctx->fr[16]),
+	      [f49] "m" (fctx->fr[17]),
+	      [f50] "m" (fctx->fr[18]),
+	      [f51] "m" (fctx->fr[19]),
+	      [f52] "m" (fctx->fr[20]),
+	      [f53] "m" (fctx->fr[21]),
+	      [f54] "m" (fctx->fr[22]),
+	      [f55] "m" (fctx->fr[23]),
+	      [f56] "m" (fctx->fr[24]),
+	      [f57] "m" (fctx->fr[25]),
+	      [f58] "m" (fctx->fr[26]),
+	      [f59] "m" (fctx->fr[27]),
+	      [f60] "m" (fctx->fr[28]),
+	      [f61] "m" (fctx->fr[29])
+	);
+
+	asm volatile (
+	    "ldf.fill f62 = %[f62]\n"
+	    "ldf.fill f63 = %[f63]\n"
+	    "ldf.fill f64 = %[f64]\n"
+	    "ldf.fill f65 = %[f65]\n"
+	    "ldf.fill f66 = %[f66]\n"
+	    "ldf.fill f67 = %[f67]\n"
+	    "ldf.fill f68 = %[f68]\n"
+	    "ldf.fill f69 = %[f69]\n"
+	    "ldf.fill f70 = %[f70]\n"
+	    "ldf.fill f71 = %[f71]\n"
+	    "ldf.fill f72 = %[f72]\n"
+	    "ldf.fill f73 = %[f73]\n"
+	    "ldf.fill f74 = %[f74]\n"
+	    "ldf.fill f75 = %[f75]\n"
+	    "ldf.fill f76 = %[f76]\n"
+	    "ldf.fill f77 = %[f77]\n"
+	    "ldf.fill f78 = %[f78]\n"
+	    "ldf.fill f79 = %[f79]\n"
+	    "ldf.fill f80 = %[f80]\n"
+	    "ldf.fill f81 = %[f81]\n"
+	    "ldf.fill f82 = %[f82]\n"
+	    "ldf.fill f83 = %[f83]\n"
+	    "ldf.fill f84 = %[f84]\n"
+	    "ldf.fill f85 = %[f85]\n"
+	    "ldf.fill f86 = %[f86]\n"
+	    "ldf.fill f87 = %[f87]\n"
+	    "ldf.fill f88 = %[f88]\n"
+	    "ldf.fill f89 = %[f89]\n"
+	    "ldf.fill f90 = %[f90]\n"
+	    "ldf.fill f91 = %[f91]\n"
+	    ::
+	      [f62] "m" (fctx->fr[30]),
+	      [f63] "m" (fctx->fr[31]),
+	      [f64] "m" (fctx->fr[32]),
+	      [f65] "m" (fctx->fr[33]),
+	      [f66] "m" (fctx->fr[34]),
+	      [f67] "m" (fctx->fr[35]),
+	      [f68] "m" (fctx->fr[36]),
+	      [f69] "m" (fctx->fr[37]),
+	      [f70] "m" (fctx->fr[38]),
+	      [f71] "m" (fctx->fr[39]),
+	      [f72] "m" (fctx->fr[40]),
+	      [f73] "m" (fctx->fr[41]),
+	      [f74] "m" (fctx->fr[42]),
+	      [f75] "m" (fctx->fr[43]),
+	      [f76] "m" (fctx->fr[44]),
+	      [f77] "m" (fctx->fr[45]),
+	      [f78] "m" (fctx->fr[46]),
+	      [f79] "m" (fctx->fr[47]),
+	      [f80] "m" (fctx->fr[48]),
+	      [f81] "m" (fctx->fr[49]),
+	      [f82] "m" (fctx->fr[50]),
+	      [f83] "m" (fctx->fr[51]),
+	      [f84] "m" (fctx->fr[52]),
+	      [f85] "m" (fctx->fr[53]),
+	      [f86] "m" (fctx->fr[54]),
+	      [f87] "m" (fctx->fr[55]),
+	      [f88] "m" (fctx->fr[56]),
+	      [f89] "m" (fctx->fr[57]),
+	      [f90] "m" (fctx->fr[58]),
+	      [f91] "m" (fctx->fr[59])
+	);
+
+	asm volatile (
+	    "ldf.fill f92 = %[f92]\n"
+	    "ldf.fill f93 = %[f93]\n"
+	    "ldf.fill f94 = %[f94]\n"
+	    "ldf.fill f95 = %[f95]\n"
+	    "ldf.fill f96 = %[f96]\n"
+	    "ldf.fill f97 = %[f97]\n"
+	    "ldf.fill f98 = %[f98]\n"
+	    "ldf.fill f99 = %[f99]\n"
+	    "ldf.fill f100 = %[f100]\n"
+	    "ldf.fill f101 = %[f101]\n"
+	    "ldf.fill f102 = %[f102]\n"
+	    "ldf.fill f103 = %[f103]\n"
+	    "ldf.fill f104 = %[f104]\n"
+	    "ldf.fill f105 = %[f105]\n"
+	    "ldf.fill f106 = %[f106]\n"
+	    "ldf.fill f107 = %[f107]\n"
+	    "ldf.fill f108 = %[f108]\n"
+	    "ldf.fill f109 = %[f109]\n"
+	    "ldf.fill f110 = %[f110]\n"
+	    "ldf.fill f111 = %[f111]\n"
+	    "ldf.fill f112 = %[f112]\n"
+	    "ldf.fill f113 = %[f113]\n"
+	    "ldf.fill f114 = %[f114]\n"
+	    "ldf.fill f115 = %[f115]\n"
+	    "ldf.fill f116 = %[f116]\n"
+	    "ldf.fill f117 = %[f117]\n"
+	    "ldf.fill f118 = %[f118]\n"
+	    "ldf.fill f119 = %[f119]\n"
+	    "ldf.fill f120 = %[f120]\n"
+	    "ldf.fill f121 = %[f121]\n"
+	    ::
+	      [f92] "m" (fctx->fr[60]),
+	      [f93] "m" (fctx->fr[61]),
+	      [f94] "m" (fctx->fr[62]),
+	      [f95] "m" (fctx->fr[63]),
+	      [f96] "m" (fctx->fr[64]),
+	      [f97] "m" (fctx->fr[65]),
+	      [f98] "m" (fctx->fr[66]),
+	      [f99] "m" (fctx->fr[67]),
+	      [f100] "m" (fctx->fr[68]),
+	      [f101] "m" (fctx->fr[69]),
+	      [f102] "m" (fctx->fr[70]),
+	      [f103] "m" (fctx->fr[71]),
+	      [f104] "m" (fctx->fr[72]),
+	      [f105] "m" (fctx->fr[73]),
+	      [f106] "m" (fctx->fr[74]),
+	      [f107] "m" (fctx->fr[75]),
+	      [f108] "m" (fctx->fr[76]),
+	      [f109] "m" (fctx->fr[77]),
+	      [f110] "m" (fctx->fr[78]),
+	      [f111] "m" (fctx->fr[79]),
+	      [f112] "m" (fctx->fr[80]),
+	      [f113] "m" (fctx->fr[81]),
+	      [f114] "m" (fctx->fr[82]),
+	      [f115] "m" (fctx->fr[83]),
+	      [f116] "m" (fctx->fr[84]),
+	      [f117] "m" (fctx->fr[85]),
+	      [f118] "m" (fctx->fr[86]),
+	      [f119] "m" (fctx->fr[87]),
+	      [f120] "m" (fctx->fr[88]),
+	      [f121] "m" (fctx->fr[89])
+	);
+
+	asm volatile (
+	    "ldf.fill f122 = %[f122]\n"
+	    "ldf.fill f123 = %[f123]\n"
+	    "ldf.fill f124 = %[f124]\n"
+	    "ldf.fill f125 = %[f125]\n"
+	    "ldf.fill f126 = %[f126]\n"
+	    "ldf.fill f127 = %[f127]\n"
+	    ::
+	      [f122] "m" (fctx->fr[90]),
+	      [f123] "m" (fctx->fr[91]),
+	      [f124] "m" (fctx->fr[92]),
+	      [f125] "m" (fctx->fr[93]),
+	      [f126] "m" (fctx->fr[94]),
+	      [f127] "m" (fctx->fr[95])
 	);
 }
@@ -465,17 +465,17 @@
 
 	asm volatile (
-		"rsm %0 ;;"
-		"srlz.i\n"
-		"srlz.d ;;\n"
-		:
-		: "i" (PSR_DFH_MASK)
-	);
-
-	asm volatile (
-		"mov %0 = ar.fpsr ;;\n"
-		"or %0 = %0,%1 ;;\n"
-		"mov ar.fpsr = %0 ;;\n"
-		: "+r" (a)
-		: "r" (0x38)
+	    "rsm %0 ;;"
+	    "srlz.i\n"
+	    "srlz.d ;;\n"
+	    :
+	    : "i" (PSR_DFH_MASK)
+	);
+
+	asm volatile (
+	    "mov %0 = ar.fpsr ;;\n"
+	    "or %0 = %0,%1 ;;\n"
+	    "mov ar.fpsr = %0 ;;\n"
+	    : "+r" (a)
+	    : "r" (0x38)
 	);
 }
@@ -483,20 +483,20 @@
 void fpu_disable(void)
 {
-	uint64_t a = 0 ;
-
-	asm volatile (
-		"ssm %0 ;;\n"
-		"srlz.i\n"
-		"srlz.d ;;\n"
-		:
-		: "i" (PSR_DFH_MASK)
-	);
-
-	asm volatile (
-		"mov %0 = ar.fpsr ;;\n"
-		"or %0 = %0,%1 ;;\n"
-		"mov ar.fpsr = %0 ;;\n"
-		: "+r" (a)
-		: "r" (0x38)
+	uint64_t a = 0;
+
+	asm volatile (
+	    "ssm %0 ;;\n"
+	    "srlz.i\n"
+	    "srlz.d ;;\n"
+	    :
+	    : "i" (PSR_DFH_MASK)
+	);
+
+	asm volatile (
+	    "mov %0 = ar.fpsr ;;\n"
+	    "or %0 = %0,%1 ;;\n"
+	    "mov ar.fpsr = %0 ;;\n"
+	    : "+r" (a)
+	    : "r" (0x38)
 	);
 }
@@ -504,153 +504,153 @@
 void fpu_init(void)
 {
-	uint64_t a = 0 ;
-
-	asm volatile (
-		"mov %0 = ar.fpsr ;;\n"
-		"or %0 = %0,%1 ;;\n"
-		"mov ar.fpsr = %0 ;;\n"
-		: "+r" (a)
-		: "r" (0x38)
-	);
-
-	asm volatile (
-		"mov f2 = f0\n"
-		"mov f3 = f0\n"
-		"mov f4 = f0\n"
-		"mov f5 = f0\n"
-		"mov f6 = f0\n"
-		"mov f7 = f0\n"
-		"mov f8 = f0\n"
-		"mov f9 = f0\n"
-
-		"mov f10 = f0\n"
-		"mov f11 = f0\n"
-		"mov f12 = f0\n"
-		"mov f13 = f0\n"
-		"mov f14 = f0\n"
-		"mov f15 = f0\n"
-		"mov f16 = f0\n"
-		"mov f17 = f0\n"
-		"mov f18 = f0\n"
-		"mov f19 = f0\n"
-
-		"mov f20 = f0\n"
-		"mov f21 = f0\n"
-		"mov f22 = f0\n"
-		"mov f23 = f0\n"
-		"mov f24 = f0\n"
-		"mov f25 = f0\n"
-		"mov f26 = f0\n"
-		"mov f27 = f0\n"
-		"mov f28 = f0\n"
-		"mov f29 = f0\n"
-
-		"mov f30 = f0\n"
-		"mov f31 = f0\n"
-		"mov f32 = f0\n"
-		"mov f33 = f0\n"
-		"mov f34 = f0\n"
-		"mov f35 = f0\n"
-		"mov f36 = f0\n"
-		"mov f37 = f0\n"
-		"mov f38 = f0\n"
-		"mov f39 = f0\n"
-
-		"mov f40 = f0\n"
-		"mov f41 = f0\n"
-		"mov f42 = f0\n"
-		"mov f43 = f0\n"
-		"mov f44 = f0\n"
-		"mov f45 = f0\n"
-		"mov f46 = f0\n"
-		"mov f47 = f0\n"
-		"mov f48 = f0\n"
-		"mov f49 = f0\n"
-
-		"mov f50 = f0\n"
-		"mov f51 = f0\n"
-		"mov f52 = f0\n"
-		"mov f53 = f0\n"
-		"mov f54 = f0\n"
-		"mov f55 = f0\n"
-		"mov f56 = f0\n"
-		"mov f57 = f0\n"
-		"mov f58 = f0\n"
-		"mov f59 = f0\n"
-
-		"mov f60 = f0\n"
-		"mov f61 = f0\n"
-		"mov f62 = f0\n"
-		"mov f63 = f0\n"
-		"mov f64 = f0\n"
-		"mov f65 = f0\n"
-		"mov f66 = f0\n"
-		"mov f67 = f0\n"
-		"mov f68 = f0\n"
-		"mov f69 = f0\n"
-
-		"mov f70 = f0\n"
-		"mov f71 = f0\n"
-		"mov f72 = f0\n"
-		"mov f73 = f0\n"
-		"mov f74 = f0\n"
-		"mov f75 = f0\n"
-		"mov f76 = f0\n"
-		"mov f77 = f0\n"
-		"mov f78 = f0\n"
-		"mov f79 = f0\n"
-
-		"mov f80 = f0\n"
-		"mov f81 = f0\n"
-		"mov f82 = f0\n"
-		"mov f83 = f0\n"
-		"mov f84 = f0\n"
-		"mov f85 = f0\n"
-		"mov f86 = f0\n"
-		"mov f87 = f0\n"
-		"mov f88 = f0\n"
-		"mov f89 = f0\n"
-
-		"mov f90 = f0\n"
-		"mov f91 = f0\n"
-		"mov f92 = f0\n"
-		"mov f93 = f0\n"
-		"mov f94 = f0\n"
-		"mov f95 = f0\n"
-		"mov f96 = f0\n"
-		"mov f97 = f0\n"
-		"mov f98 = f0\n"
-		"mov f99 = f0\n"
-
-		"mov f100 = f0\n"
-		"mov f101 = f0\n"
-		"mov f102 = f0\n"
-		"mov f103 = f0\n"
-		"mov f104 = f0\n"
-		"mov f105 = f0\n"
-		"mov f106 = f0\n"
-		"mov f107 = f0\n"
-		"mov f108 = f0\n"
-		"mov f109 = f0\n"
-
-		"mov f110 = f0\n"
-		"mov f111 = f0\n"
-		"mov f112 = f0\n"
-		"mov f113 = f0\n"
-		"mov f114 = f0\n"
-		"mov f115 = f0\n"
-		"mov f116 = f0\n"
-		"mov f117 = f0\n"
-		"mov f118 = f0\n"
-		"mov f119 = f0\n"
-
-		"mov f120 = f0\n"
-		"mov f121 = f0\n"
-		"mov f122 = f0\n"
-		"mov f123 = f0\n"
-		"mov f124 = f0\n"
-		"mov f125 = f0\n"
-		"mov f126 = f0\n"
-		"mov f127 = f0\n"
+	uint64_t a = 0;
+
+	asm volatile (
+	    "mov %0 = ar.fpsr ;;\n"
+	    "or %0 = %0,%1 ;;\n"
+	    "mov ar.fpsr = %0 ;;\n"
+	    : "+r" (a)
+	    : "r" (0x38)
+	);
+
+	asm volatile (
+	    "mov f2 = f0\n"
+	    "mov f3 = f0\n"
+	    "mov f4 = f0\n"
+	    "mov f5 = f0\n"
+	    "mov f6 = f0\n"
+	    "mov f7 = f0\n"
+	    "mov f8 = f0\n"
+	    "mov f9 = f0\n"
+
+	    "mov f10 = f0\n"
+	    "mov f11 = f0\n"
+	    "mov f12 = f0\n"
+	    "mov f13 = f0\n"
+	    "mov f14 = f0\n"
+	    "mov f15 = f0\n"
+	    "mov f16 = f0\n"
+	    "mov f17 = f0\n"
+	    "mov f18 = f0\n"
+	    "mov f19 = f0\n"
+
+	    "mov f20 = f0\n"
+	    "mov f21 = f0\n"
+	    "mov f22 = f0\n"
+	    "mov f23 = f0\n"
+	    "mov f24 = f0\n"
+	    "mov f25 = f0\n"
+	    "mov f26 = f0\n"
+	    "mov f27 = f0\n"
+	    "mov f28 = f0\n"
+	    "mov f29 = f0\n"
+
+	    "mov f30 = f0\n"
+	    "mov f31 = f0\n"
+	    "mov f32 = f0\n"
+	    "mov f33 = f0\n"
+	    "mov f34 = f0\n"
+	    "mov f35 = f0\n"
+	    "mov f36 = f0\n"
+	    "mov f37 = f0\n"
+	    "mov f38 = f0\n"
+	    "mov f39 = f0\n"
+
+	    "mov f40 = f0\n"
+	    "mov f41 = f0\n"
+	    "mov f42 = f0\n"
+	    "mov f43 = f0\n"
+	    "mov f44 = f0\n"
+	    "mov f45 = f0\n"
+	    "mov f46 = f0\n"
+	    "mov f47 = f0\n"
+	    "mov f48 = f0\n"
+	    "mov f49 = f0\n"
+
+	    "mov f50 = f0\n"
+	    "mov f51 = f0\n"
+	    "mov f52 = f0\n"
+	    "mov f53 = f0\n"
+	    "mov f54 = f0\n"
+	    "mov f55 = f0\n"
+	    "mov f56 = f0\n"
+	    "mov f57 = f0\n"
+	    "mov f58 = f0\n"
+	    "mov f59 = f0\n"
+
+	    "mov f60 = f0\n"
+	    "mov f61 = f0\n"
+	    "mov f62 = f0\n"
+	    "mov f63 = f0\n"
+	    "mov f64 = f0\n"
+	    "mov f65 = f0\n"
+	    "mov f66 = f0\n"
+	    "mov f67 = f0\n"
+	    "mov f68 = f0\n"
+	    "mov f69 = f0\n"
+
+	    "mov f70 = f0\n"
+	    "mov f71 = f0\n"
+	    "mov f72 = f0\n"
+	    "mov f73 = f0\n"
+	    "mov f74 = f0\n"
+	    "mov f75 = f0\n"
+	    "mov f76 = f0\n"
+	    "mov f77 = f0\n"
+	    "mov f78 = f0\n"
+	    "mov f79 = f0\n"
+
+	    "mov f80 = f0\n"
+	    "mov f81 = f0\n"
+	    "mov f82 = f0\n"
+	    "mov f83 = f0\n"
+	    "mov f84 = f0\n"
+	    "mov f85 = f0\n"
+	    "mov f86 = f0\n"
+	    "mov f87 = f0\n"
+	    "mov f88 = f0\n"
+	    "mov f89 = f0\n"
+
+	    "mov f90 = f0\n"
+	    "mov f91 = f0\n"
+	    "mov f92 = f0\n"
+	    "mov f93 = f0\n"
+	    "mov f94 = f0\n"
+	    "mov f95 = f0\n"
+	    "mov f96 = f0\n"
+	    "mov f97 = f0\n"
+	    "mov f98 = f0\n"
+	    "mov f99 = f0\n"
+
+	    "mov f100 = f0\n"
+	    "mov f101 = f0\n"
+	    "mov f102 = f0\n"
+	    "mov f103 = f0\n"
+	    "mov f104 = f0\n"
+	    "mov f105 = f0\n"
+	    "mov f106 = f0\n"
+	    "mov f107 = f0\n"
+	    "mov f108 = f0\n"
+	    "mov f109 = f0\n"
+
+	    "mov f110 = f0\n"
+	    "mov f111 = f0\n"
+	    "mov f112 = f0\n"
+	    "mov f113 = f0\n"
+	    "mov f114 = f0\n"
+	    "mov f115 = f0\n"
+	    "mov f116 = f0\n"
+	    "mov f117 = f0\n"
+	    "mov f118 = f0\n"
+	    "mov f119 = f0\n"
+
+	    "mov f120 = f0\n"
+	    "mov f121 = f0\n"
+	    "mov f122 = f0\n"
+	    "mov f123 = f0\n"
+	    "mov f124 = f0\n"
+	    "mov f125 = f0\n"
+	    "mov f126 = f0\n"
+	    "mov f127 = f0\n"
 	);
 
Index: kernel/arch/ia64/src/mm/tlb.c
===================================================================
--- kernel/arch/ia64/src/mm/tlb.c	(revision fd57745cd4811832fa23ba1cef7638038244f2b5)
+++ kernel/arch/ia64/src/mm/tlb.c	(revision 231c770580f4400a6e0e7612723b1efb16fd5390)
@@ -75,6 +75,6 @@
 		for (j = 0; j < count2; j++) {
 			asm volatile (
-				"ptc.e %[adr] ;;"
-				:: [adr] "r" (adr)
+			    "ptc.e %[adr] ;;"
+			    :: [adr] "r" (adr)
 			);
 			adr += stride2;
@@ -175,7 +175,7 @@
 	for (; va < (page + cnt * PAGE_SIZE); va += (1UL << ps))
 		asm volatile (
-			"ptc.l %[va], %[ps] ;;"
-			:: [va]"r" (va),
-			   [ps] "r" (ps << 2)
+		    "ptc.l %[va], %[ps] ;;"
+		    :: [va] "r" (va),
+		      [ps] "r" (ps << 2)
 		);
 
@@ -246,21 +246,21 @@
 
 	asm volatile (
-		"mov r8 = psr ;;\n"
-		"rsm %[mask] ;;\n"                 /* PSR_IC_MASK */
-		"srlz.d ;;\n"
-		"srlz.i ;;\n"
-		"mov cr.ifa = %[va]\n"             /* va */
-		"mov cr.itir = %[word1] ;;\n"      /* entry.word[1] */
-		"cmp.eq p6, p7 = %[dtc], r0 ;;\n"  /* decide between itc and dtc */
-		"(p6) itc.i %[word0] ;;\n"
-		"(p7) itc.d %[word0] ;;\n"
-		"mov psr.l = r8 ;;\n"
-		"srlz.d ;;\n"
-		:: [mask] "i" (PSR_IC_MASK),
-		   [va] "r" (va),
-		   [word0] "r" (entry.word[0]),
-		   [word1] "r" (entry.word[1]),
-		   [dtc] "r" (dtc)
-		: "p6", "p7", "r8"
+	    "mov r8 = psr ;;\n"
+	    "rsm %[mask] ;;\n"                 /* PSR_IC_MASK */
+	    "srlz.d ;;\n"
+	    "srlz.i ;;\n"
+	    "mov cr.ifa = %[va]\n"             /* va */
+	    "mov cr.itir = %[word1] ;;\n"      /* entry.word[1] */
+	    "cmp.eq p6, p7 = %[dtc], r0 ;;\n"  /* decide between itc and dtc */
+	    "(p6) itc.i %[word0] ;;\n"
+	    "(p7) itc.d %[word0] ;;\n"
+	    "mov psr.l = r8 ;;\n"
+	    "srlz.d ;;\n"
+	    :: [mask] "i" (PSR_IC_MASK),
+	      [va] "r" (va),
+	      [word0] "r" (entry.word[0]),
+	      [word1] "r" (entry.word[1]),
+	      [dtc] "r" (dtc)
+	    : "p6", "p7", "r8"
 	);
 
@@ -333,22 +333,22 @@
 
 	asm volatile (
-		"mov r8 = psr ;;\n"
-		"rsm %[mask] ;;\n"                       /* PSR_IC_MASK */
-		"srlz.d ;;\n"
-		"srlz.i ;;\n"
-		"mov cr.ifa = %[va]\n"                   /* va */
-		"mov cr.itir = %[word1] ;;\n"            /* entry.word[1] */
-		"cmp.eq p6, p7 = %[dtr], r0 ;;\n"        /* decide between itr and dtr */
-		"(p6) itr.i itr[%[tr]] = %[word0] ;;\n"
-		"(p7) itr.d dtr[%[tr]] = %[word0] ;;\n"
-		"mov psr.l = r8 ;;\n"
-		"srlz.d ;;\n"
-		:: [mask] "i" (PSR_IC_MASK),
-		   [va] "r" (va),
-		   [word1] "r" (entry.word[1]),
-		   [word0] "r" (entry.word[0]),
-		   [tr] "r" (tr),
-		   [dtr] "r" (dtr)
-		: "p6", "p7", "r8"
+	    "mov r8 = psr ;;\n"
+	    "rsm %[mask] ;;\n"                       /* PSR_IC_MASK */
+	    "srlz.d ;;\n"
+	    "srlz.i ;;\n"
+	    "mov cr.ifa = %[va]\n"                   /* va */
+	    "mov cr.itir = %[word1] ;;\n"            /* entry.word[1] */
+	    "cmp.eq p6, p7 = %[dtr], r0 ;;\n"        /* decide between itr and dtr */
+	    "(p6) itr.i itr[%[tr]] = %[word0] ;;\n"
+	    "(p7) itr.d dtr[%[tr]] = %[word0] ;;\n"
+	    "mov psr.l = r8 ;;\n"
+	    "srlz.d ;;\n"
+	    :: [mask] "i" (PSR_IC_MASK),
+	      [va] "r" (va),
+	      [word1] "r" (entry.word[1]),
+	      [word0] "r" (entry.word[0]),
+	      [tr] "r" (tr),
+	      [dtr] "r" (dtr)
+	    : "p6", "p7", "r8"
 	);
 
@@ -403,7 +403,7 @@
 {
 	asm volatile (
-		"ptr.d %[page], %[width]\n"
-		:: [page] "r" (page),
-		   [width] "r" (width << 2)
+	    "ptr.d %[page], %[width]\n"
+	    :: [page] "r" (page),
+	      [width] "r" (width << 2)
 	);
 }
Index: kernel/arch/ia64/src/mm/vhpt.c
===================================================================
--- kernel/arch/ia64/src/mm/vhpt.c	(revision fd57745cd4811832fa23ba1cef7638038244f2b5)
+++ kernel/arch/ia64/src/mm/vhpt.c	(revision 231c770580f4400a6e0e7612723b1efb16fd5390)
@@ -38,5 +38,5 @@
 #include <print.h>
 
-static vhpt_entry_t* vhpt_base;
+static vhpt_entry_t *vhpt_base;
 
 uintptr_t vhpt_set_up(void)
Index: kernel/arch/ia64/src/proc/scheduler.c
===================================================================
--- kernel/arch/ia64/src/proc/scheduler.c	(revision fd57745cd4811832fa23ba1cef7638038244f2b5)
+++ kernel/arch/ia64/src/proc/scheduler.c	(revision 231c770580f4400a6e0e7612723b1efb16fd5390)
@@ -65,5 +65,5 @@
 
 		/* purge DTR[TR_STACK1] and DTR[TR_STACK2] */
-		dtr_purge((uintptr_t) THREAD->kstack, PAGE_WIDTH+1);
+		dtr_purge((uintptr_t) THREAD->kstack, PAGE_WIDTH + 1);
 
 		/* insert DTR[TR_STACK1] and DTR[TR_STACK2] */
@@ -84,12 +84,12 @@
 	 */
 	asm volatile (
-		"bsw.0\n"
-		"mov r22 = %0\n"
-		"mov r23 = %1\n"
-		"bsw.1\n"
-		:
-		: "r" (&THREAD->kstack[STACK_SIZE / 2]),
-		  "r" (&THREAD->kstack[STACK_SIZE / 2])
-		);
+	    "bsw.0\n"
+	    "mov r22 = %0\n"
+	    "mov r23 = %1\n"
+	    "bsw.1\n"
+	    :
+	    : "r" (&THREAD->kstack[STACK_SIZE / 2]),
+	      "r" (&THREAD->kstack[STACK_SIZE / 2])
+	);
 }
 
Index: kernel/arch/mips32/include/arch/atomic.h
===================================================================
--- kernel/arch/mips32/include/arch/atomic.h	(revision fd57745cd4811832fa23ba1cef7638038244f2b5)
+++ kernel/arch/mips32/include/arch/atomic.h	(revision 231c770580f4400a6e0e7612723b1efb16fd5390)
@@ -62,16 +62,16 @@
 
 	asm volatile (
-		"1:\n"
-		"	ll %0, %1\n"
-		"	addu %0, %0, %3\n"  /* same as addi, but never traps on overflow */
-		"	move %2, %0\n"
-		"	sc %0, %1\n"
-		"	beq %0, %4, 1b\n"   /* if the atomic operation failed, try again */
-		"	nop\n"
-		: "=&r" (tmp),
-		  "+m" (val->count),
-		  "=&r" (v)
-		: "r" (i),
-		  "i" (0)
+	    "1:\n"
+	    "	ll %0, %1\n"
+	    "	addu %0, %0, %3\n"  /* same as addi, but never traps on overflow */
+	    "	move %2, %0\n"
+	    "	sc %0, %1\n"
+	    "	beq %0, %4, 1b\n"   /* if the atomic operation failed, try again */
+	    "	nop\n"
+	    : "=&r" (tmp),
+	      "+m" (val->count),
+	      "=&r" (v)
+	    : "r" (i),
+	      "i" (0)
 	);
 
@@ -85,16 +85,16 @@
 
 	asm volatile (
-		"1:\n"
-		"	ll %2, %1\n"
-		"	bnez %2, 2f\n"
-		"	li %0, %3\n"
-		"	sc %0, %1\n"
-		"	beqz %0, 1b\n"
-		"	nop\n"
-		"2:\n"
-		: "=&r" (tmp),
-		  "+m" (val->count),
-		  "=&r" (v)
-		: "i" (1)
+	    "1:\n"
+	    "	ll %2, %1\n"
+	    "	bnez %2, 2f\n"
+	    "	li %0, %3\n"
+	    "	sc %0, %1\n"
+	    "	beqz %0, 1b\n"
+	    "	nop\n"
+	    "2:\n"
+	    : "=&r" (tmp),
+	      "+m" (val->count),
+	      "=&r" (v)
+	    : "i" (1)
 	);
 
@@ -105,5 +105,6 @@
 {
 	do {
-		while (val->count);
+		while (val->count)
+			;
 	} while (test_and_set(val));
 }
Index: kernel/arch/mips32/src/cpu/cpu.c
===================================================================
--- kernel/arch/mips32/src/cpu/cpu.c	(revision fd57745cd4811832fa23ba1cef7638038244f2b5)
+++ kernel/arch/mips32/src/cpu/cpu.c	(revision 231c770580f4400a6e0e7612723b1efb16fd5390)
@@ -86,8 +86,8 @@
 static struct data_t imp_data80[] = {
 	{ "MIPS", "4Kc" },  /* 0x80 */
-	{"Invalid","Invalid"}, /* 0x81 */
-	{"Invalid","Invalid"}, /* 0x82 */
-	{"MIPS","4Km & 4Kp"}, /* 0x83 */
-	{ NULL, NULL}
+	{ "Invalid", "Invalid" }, /* 0x81 */
+	{ "Invalid", "Invalid" }, /* 0x82 */
+	{ "MIPS", "4Km & 4Kp" }, /* 0x83 */
+	{ NULL, NULL }
 };
 
@@ -129,6 +129,6 @@
 
 	printf("cpu%u: %s %s (rev=%d.%d, imp=%d)\n",
-		m->id, data->vendor, data->model, m->arch.rev_num >> 4,
-		m->arch.rev_num & 0x0f, m->arch.imp_num);
+	    m->id, data->vendor, data->model, m->arch.rev_num >> 4,
+	    m->arch.rev_num & 0x0f, m->arch.imp_num);
 }
 
Index: kernel/arch/mips32/src/mach/malta/malta.c
===================================================================
--- kernel/arch/mips32/src/mach/malta/malta.c	(revision fd57745cd4811832fa23ba1cef7638038244f2b5)
+++ kernel/arch/mips32/src/mach/malta/malta.c	(revision 231c770580f4400a6e0e7612723b1efb16fd5390)
@@ -84,7 +84,7 @@
 {
 
-        const char ch = (char) wch;
+	const char ch = (char) wch;
 
-        (*yamon_print_count)(0, &ch, 1);
+	(*yamon_print_count)(0, &ch, 1);
 }
 
Index: kernel/arch/mips32/src/mips32.c
===================================================================
--- kernel/arch/mips32/src/mips32.c	(revision fd57745cd4811832fa23ba1cef7638038244f2b5)
+++ kernel/arch/mips32/src/mips32.c	(revision 231c770580f4400a6e0e7612723b1efb16fd5390)
@@ -74,5 +74,5 @@
 
 /* Stack pointer saved when entering user mode */
-uintptr_t supervisor_sp __attribute__ ((section (".text")));
+uintptr_t supervisor_sp __attribute__((section(".text")));
 
 size_t cpu_count = 0;
@@ -172,5 +172,6 @@
 	    (uintptr_t) kernel_uarg->uspace_entry);
 
-	while (1);
+	while (1)
+		;
 }
 
@@ -194,5 +195,6 @@
 {
 	___halt();
-	while (1);
+	while (1)
+		;
 }
 
Index: kernel/arch/mips32/src/mm/frame.c
===================================================================
--- kernel/arch/mips32/src/mm/frame.c	(revision fd57745cd4811832fa23ba1cef7638038244f2b5)
+++ kernel/arch/mips32/src/mm/frame.c	(revision 231c770580f4400a6e0e7612723b1efb16fd5390)
@@ -290,5 +290,5 @@
 	for (i = 0; i < phys_regions_count; i++) {
 		printf("%#010x %10u\n",
-			PFN2ADDR(phys_regions[i].start), PFN2ADDR(phys_regions[i].count));
+		    PFN2ADDR(phys_regions[i].start), PFN2ADDR(phys_regions[i].count));
 	}
 }
Index: kernel/arch/ppc32/include/arch/asm.h
===================================================================
--- kernel/arch/ppc32/include/arch/asm.h	(revision fd57745cd4811832fa23ba1cef7638038244f2b5)
+++ kernel/arch/ppc32/include/arch/asm.h	(revision 231c770580f4400a6e0e7612723b1efb16fd5390)
@@ -47,6 +47,6 @@
 
 	asm volatile (
-		"mfmsr %[msr]\n"
-		: [msr] "=r" (msr)
+	    "mfmsr %[msr]\n"
+	    : [msr] "=r" (msr)
 	);
 
@@ -57,7 +57,7 @@
 {
 	asm volatile (
-		"mtmsr %[msr]\n"
-		"isync\n"
-		:: [msr] "r" (msr)
+	    "mtmsr %[msr]\n"
+	    "isync\n"
+	    :: [msr] "r" (msr)
 	);
 }
@@ -66,9 +66,9 @@
 {
 	asm volatile (
-		"mtsrin %[value], %[sr]\n"
-		"sync\n"
-		"isync\n"
-		:: [value] "r" ((flags << 16) + (asid << 4) + sr),
-		   [sr] "r" (sr << 28)
+	    "mtsrin %[value], %[sr]\n"
+	    "sync\n"
+	    "isync\n"
+	    :: [value] "r" ((flags << 16) + (asid << 4) + sr),
+	      [sr] "r" (sr << 28)
 	);
 }
@@ -79,7 +79,7 @@
 
 	asm volatile (
-		"mfsrin %[vsid], %[vaddr]\n"
-		: [vsid] "=r" (vsid)
-		: [vaddr] "r" (vaddr)
+	    "mfsrin %[vsid], %[vaddr]\n"
+	    : [vsid] "=r" (vsid)
+	    : [vaddr] "r" (vaddr)
 	);
 
@@ -92,6 +92,6 @@
 
 	asm volatile (
-		"mfsdr1 %[sdr1]\n"
-		: [sdr1] "=r" (sdr1)
+	    "mfsdr1 %[sdr1]\n"
+	    : [sdr1] "=r" (sdr1)
 	);
 
@@ -175,7 +175,7 @@
 
 	asm volatile (
-		"and %[base], %%sp, %[mask]\n"
-		: [base] "=r" (base)
-		: [mask] "r" (~(STACK_SIZE - 1))
+	    "and %[base], %%sp, %[mask]\n"
+	    : [base] "=r" (base)
+	    : [mask] "r" (~(STACK_SIZE - 1))
 	);
 
Index: kernel/arch/ppc32/include/arch/atomic.h
===================================================================
--- kernel/arch/ppc32/include/arch/atomic.h	(revision fd57745cd4811832fa23ba1cef7638038244f2b5)
+++ kernel/arch/ppc32/include/arch/atomic.h	(revision 231c770580f4400a6e0e7612723b1efb16fd5390)
@@ -43,14 +43,14 @@
 
 	asm volatile (
-		"1:\n"
-		"	lwarx %[tmp], 0, %[count_ptr]\n"
-		"	addic %[tmp], %[tmp], 1\n"
-		"	stwcx. %[tmp], 0, %[count_ptr]\n"
-		"	bne- 1b"
-		: [tmp] "=&r" (tmp),
-		  "=m" (val->count)
-		: [count_ptr] "r" (&val->count),
-		  "m" (val->count)
-		: "cc"
+	    "1:\n"
+	    "	lwarx %[tmp], 0, %[count_ptr]\n"
+	    "	addic %[tmp], %[tmp], 1\n"
+	    "	stwcx. %[tmp], 0, %[count_ptr]\n"
+	    "	bne- 1b"
+	    : [tmp] "=&r" (tmp),
+	      "=m" (val->count)
+	    : [count_ptr] "r" (&val->count),
+	      "m" (val->count)
+	    : "cc"
 	);
 }
@@ -61,14 +61,14 @@
 
 	asm volatile (
-		"1:\n"
-		"	lwarx %[tmp], 0, %[count_ptr]\n"
-		"	addic %[tmp], %[tmp], -1\n"
-		"	stwcx. %[tmp], 0, %[count_ptr]\n"
-		"	bne- 1b"
-		: [tmp] "=&r" (tmp),
-		  "=m" (val->count)
-		: [count_ptr] "r" (&val->count),
-		  "m" (val->count)
-		: "cc"
+	    "1:\n"
+	    "	lwarx %[tmp], 0, %[count_ptr]\n"
+	    "	addic %[tmp], %[tmp], -1\n"
+	    "	stwcx. %[tmp], 0, %[count_ptr]\n"
+	    "	bne- 1b"
+	    : [tmp] "=&r" (tmp),
+	      "=m" (val->count)
+	    : [count_ptr] "r" (&val->count),
+	      "m" (val->count)
+	    : "cc"
 	);
 }
Index: kernel/arch/ppc32/include/arch/barrier.h
===================================================================
--- kernel/arch/ppc32/include/arch/barrier.h	(revision fd57745cd4811832fa23ba1cef7638038244f2b5)
+++ kernel/arch/ppc32/include/arch/barrier.h	(revision 231c770580f4400a6e0e7612723b1efb16fd5390)
@@ -65,10 +65,10 @@
 {
 	asm volatile (
-		"dcbst 0, %[addr]\n"
-		"sync\n"
-		"icbi 0, %[addr]\n"
-		"sync\n"
-		"isync\n"
-		:: [addr] "r" (addr)
+	    "dcbst 0, %[addr]\n"
+	    "sync\n"
+	    "icbi 0, %[addr]\n"
+	    "sync\n"
+	    "isync\n"
+	    :: [addr] "r" (addr)
 	);
 }
@@ -80,6 +80,6 @@
 	for (i = 0; i < len; i += COHERENCE_INVAL_MIN)
 		asm volatile (
-			"dcbst 0, %[addr]\n"
-			:: [addr] "r" (addr + i)
+		    "dcbst 0, %[addr]\n"
+		    :: [addr] "r" (addr + i)
 		);
 
@@ -88,6 +88,6 @@
 	for (i = 0; i < len; i += COHERENCE_INVAL_MIN)
 		asm volatile (
-			"icbi 0, %[addr]\n"
-			:: [addr] "r" (addr + i)
+		    "icbi 0, %[addr]\n"
+		    :: [addr] "r" (addr + i)
 		);
 
Index: kernel/arch/ppc32/include/arch/cpu.h
===================================================================
--- kernel/arch/ppc32/include/arch/cpu.h	(revision fd57745cd4811832fa23ba1cef7638038244f2b5)
+++ kernel/arch/ppc32/include/arch/cpu.h	(revision 231c770580f4400a6e0e7612723b1efb16fd5390)
@@ -42,11 +42,11 @@
 	uint16_t version;
 	uint16_t revision;
-} __attribute__ ((packed)) cpu_arch_t;
+} __attribute__((packed)) cpu_arch_t;
 
 NO_TRACE static inline void cpu_version(cpu_arch_t *info)
 {
 	asm volatile (
-		"mfpvr %[cpu_info]\n"
-		: [cpu_info] "=r" (*info)
+	    "mfpvr %[cpu_info]\n"
+	    : [cpu_info] "=r" (*info)
 	);
 }
Index: kernel/arch/ppc32/include/arch/cycle.h
===================================================================
--- kernel/arch/ppc32/include/arch/cycle.h	(revision fd57745cd4811832fa23ba1cef7638038244f2b5)
+++ kernel/arch/ppc32/include/arch/cycle.h	(revision 231c770580f4400a6e0e7612723b1efb16fd5390)
@@ -46,10 +46,10 @@
 	do {
 		asm volatile (
-			"mftbu %[upper]\n"
-			"mftb %[lower]\n"
-			"mftbu %[tmp]\n"
-			: [upper] "=r" (upper),
-			  [lower] "=r" (lower),
-			  [tmp] "=r" (tmp)
+		    "mftbu %[upper]\n"
+		    "mftb %[lower]\n"
+		    "mftbu %[tmp]\n"
+		    : [upper] "=r" (upper),
+		      [lower] "=r" (lower),
+		      [tmp] "=r" (tmp)
 		);
 	} while (upper != tmp);
Index: kernel/arch/ppc32/include/arch/mm/frame.h
===================================================================
--- kernel/arch/ppc32/include/arch/mm/frame.h	(revision fd57745cd4811832fa23ba1cef7638038244f2b5)
+++ kernel/arch/ppc32/include/arch/mm/frame.h	(revision 231c770580f4400a6e0e7612723b1efb16fd5390)
@@ -51,6 +51,6 @@
 
 	asm volatile (
-		"mfsprg3 %[physmem]\n"
-		: [physmem] "=r" (physmem)
+	    "mfsprg3 %[physmem]\n"
+	    : [physmem] "=r" (physmem)
 	);
 
Index: kernel/arch/ppc32/include/arch/mm/page.h
===================================================================
--- kernel/arch/ppc32/include/arch/mm/page.h	(revision fd57745cd4811832fa23ba1cef7638038244f2b5)
+++ kernel/arch/ppc32/include/arch/mm/page.h	(revision 231c770580f4400a6e0e7612723b1efb16fd5390)
@@ -43,9 +43,9 @@
 
 #ifndef __ASSEMBLER__
-	#define KA2PA(x)  (((uintptr_t) (x)) - 0x80000000)
-	#define PA2KA(x)  (((uintptr_t) (x)) + 0x80000000)
+#define KA2PA(x)  (((uintptr_t) (x)) - 0x80000000)
+#define PA2KA(x)  (((uintptr_t) (x)) + 0x80000000)
 #else
-	#define KA2PA(x)  ((x) - 0x80000000)
-	#define PA2KA(x)  ((x) + 0x80000000)
+#define KA2PA(x)  ((x) - 0x80000000)
+#define PA2KA(x)  ((x) + 0x80000000)
 #endif
 
Index: kernel/arch/ppc32/src/cpu/cpu.c
===================================================================
--- kernel/arch/ppc32/src/cpu/cpu.c	(revision fd57745cd4811832fa23ba1cef7638038244f2b5)
+++ kernel/arch/ppc32/src/cpu/cpu.c	(revision 231c770580f4400a6e0e7612723b1efb16fd5390)
@@ -72,5 +72,5 @@
 	}
 
-	printf("cpu%u: version=%" PRIu16" (%s), revision=%" PRIu16 "\n", cpu->id,
+	printf("cpu%u: version=%" PRIu16 " (%s), revision=%" PRIu16 "\n", cpu->id,
 	    cpu->arch.version, name, cpu->arch.revision);
 }
Index: kernel/arch/ppc32/src/interrupt.c
===================================================================
--- kernel/arch/ppc32/src/interrupt.c	(revision fd57745cd4811832fa23ba1cef7638038244f2b5)
+++ kernel/arch/ppc32/src/interrupt.c	(revision 231c770580f4400a6e0e7612723b1efb16fd5390)
@@ -57,6 +57,6 @@
 {
 	asm volatile (
-		"mtdec %[dec]\n"
-		:: [dec] "r" (decrementer_value)
+	    "mtdec %[dec]\n"
+	    :: [dec] "r" (decrementer_value)
 	);
 }
Index: kernel/arch/ppc32/src/mm/tlb.c
===================================================================
--- kernel/arch/ppc32/src/mm/tlb.c	(revision fd57745cd4811832fa23ba1cef7638038244f2b5)
+++ kernel/arch/ppc32/src/mm/tlb.c	(revision 231c770580f4400a6e0e7612723b1efb16fd5390)
@@ -44,10 +44,10 @@
 
 	asm volatile (
-		"mfspr %[tlbmiss], 980\n"
-		"mfspr %[ptehi], 981\n"
-		"mfspr %[ptelo], 982\n"
-		: [tlbmiss] "=r" (tlbmiss),
-		  [ptehi] "=r" (ptehi),
-		  [ptelo] "=r" (ptelo)
+	    "mfspr %[tlbmiss], 980\n"
+	    "mfspr %[ptehi], 981\n"
+	    "mfspr %[ptelo], 982\n"
+	    : [tlbmiss] "=r" (tlbmiss),
+	      [ptehi] "=r" (ptehi),
+	      [ptelo] "=r" (ptelo)
 	);
 
@@ -64,11 +64,11 @@
 	uint32_t index = 0;
 	asm volatile (
-		"mtspr 981, %[ptehi]\n"
-		"mtspr 982, %[ptelo]\n"
-		"tlbld %[index]\n"
-		"tlbli %[index]\n"
-		: [index] "=r" (index)
-		: [ptehi] "r" (ptehi),
-		  [ptelo] "r" (ptelo)
+	    "mtspr 981, %[ptehi]\n"
+	    "mtspr 982, %[ptelo]\n"
+	    "tlbld %[index]\n"
+	    "tlbli %[index]\n"
+	    : [index] "=r" (index)
+	    : [ptehi] "r" (ptehi),
+	      [ptelo] "r" (ptelo)
 	);
 }
@@ -82,18 +82,18 @@
 {
 	asm volatile (
-		"sync\n"
+	    "sync\n"
 	);
 
 	for (unsigned int i = 0; i < 0x00040000; i += 0x00001000) {
 		asm volatile (
-			"tlbie %[i]\n"
-			:: [i] "r" (i)
+		    "tlbie %[i]\n"
+		    :: [i] "r" (i)
 		);
 	}
 
 	asm volatile (
-		"eieio\n"
-		"tlbsync\n"
-		"sync\n"
+	    "eieio\n"
+	    "tlbsync\n"
+	    "sync\n"
 	);
 }
Index: kernel/arch/ppc32/src/proc/scheduler.c
===================================================================
--- kernel/arch/ppc32/src/proc/scheduler.c	(revision fd57745cd4811832fa23ba1cef7638038244f2b5)
+++ kernel/arch/ppc32/src/proc/scheduler.c	(revision 231c770580f4400a6e0e7612723b1efb16fd5390)
@@ -54,6 +54,6 @@
 
 	asm volatile (
-		"mtsprg0 %[ksp]\n"
-		:: [ksp] "r" (KA2PA(&THREAD->kstack[STACK_SIZE]))
+	    "mtsprg0 %[ksp]\n"
+	    :: [ksp] "r" (KA2PA(&THREAD->kstack[STACK_SIZE]))
 	);
 }
Index: kernel/arch/riscv64/include/arch/asm.h
===================================================================
--- kernel/arch/riscv64/include/arch/asm.h	(revision fd57745cd4811832fa23ba1cef7638038244f2b5)
+++ kernel/arch/riscv64/include/arch/asm.h	(revision 231c770580f4400a6e0e7612723b1efb16fd5390)
@@ -47,6 +47,6 @@
 
 	asm volatile (
-		"csrrsi %[ipl], sstatus, " STRING(SSTATUS_SIE_MASK) "\n"
-		: [ipl] "=r" (ipl)
+	    "csrrsi %[ipl], sstatus, " STRING(SSTATUS_SIE_MASK) "\n"
+	    : [ipl] "=r" (ipl)
 	);
 
@@ -59,6 +59,6 @@
 
 	asm volatile (
-		"csrrci %[ipl], sstatus, " STRING(SSTATUS_SIE_MASK) "\n"
-		: [ipl] "=r" (ipl)
+	    "csrrci %[ipl], sstatus, " STRING(SSTATUS_SIE_MASK) "\n"
+	    : [ipl] "=r" (ipl)
 	);
 
@@ -79,6 +79,6 @@
 
 	asm volatile (
-		"csrr %[ipl], sstatus\n"
-		: [ipl] "=r" (ipl)
+	    "csrr %[ipl], sstatus\n"
+	    : [ipl] "=r" (ipl)
 	);
 
@@ -96,7 +96,7 @@
 
 	asm volatile (
-		"and %[base], sp, %[mask]\n"
-		: [base] "=r" (base)
-		: [mask] "r" (~(STACK_SIZE - 1))
+	    "and %[base], sp, %[mask]\n"
+	    : [base] "=r" (base)
+	    : [mask] "r" (~(STACK_SIZE - 1))
 	);
 
Index: kernel/arch/riscv64/include/arch/atomic.h
===================================================================
--- kernel/arch/riscv64/include/arch/atomic.h	(revision fd57745cd4811832fa23ba1cef7638038244f2b5)
+++ kernel/arch/riscv64/include/arch/atomic.h	(revision 231c770580f4400a6e0e7612723b1efb16fd5390)
@@ -41,7 +41,7 @@
 {
 	asm volatile (
-		"amoadd.d zero, %[inc], %[addr]\n"
-		: [addr] "+A" (val->count)
-		: [inc] "r" (1)
+	    "amoadd.d zero, %[inc], %[addr]\n"
+	    : [addr] "+A" (val->count)
+	    : [inc] "r" (1)
 	);
 }
@@ -50,7 +50,7 @@
 {
 	asm volatile (
-		"amoadd.d zero, %[inc], %[addr]\n"
-		: [addr] "+A" (val->count)
-		: [inc] "r" (-1)
+	    "amoadd.d zero, %[inc], %[addr]\n"
+	    : [addr] "+A" (val->count)
+	    : [inc] "r" (-1)
 	);
 }
@@ -61,7 +61,7 @@
 
 	asm volatile (
-		"amoadd.d %[orig], %[inc], %[addr]\n"
-		: [orig] "=r" (orig), [addr] "+A" (val->count)
-		: [inc] "r" (1)
+	    "amoadd.d %[orig], %[inc], %[addr]\n"
+	    : [orig] "=r" (orig), [addr] "+A" (val->count)
+	    : [inc] "r" (1)
 	);
 
@@ -74,7 +74,7 @@
 
 	asm volatile (
-		"amoadd.d %[orig], %[inc], %[addr]\n"
-		: [orig] "=r" (orig), [addr] "+A" (val->count)
-		: [inc] "r" (-1)
+	    "amoadd.d %[orig], %[inc], %[addr]\n"
+	    : [orig] "=r" (orig), [addr] "+A" (val->count)
+	    : [inc] "r" (-1)
 	);
 
@@ -87,7 +87,7 @@
 
 	asm volatile (
-		"amoadd.d %[orig], %[inc], %[addr]\n"
-		: [orig] "=r" (orig), [addr] "+A" (val->count)
-		: [inc] "r" (1)
+	    "amoadd.d %[orig], %[inc], %[addr]\n"
+	    : [orig] "=r" (orig), [addr] "+A" (val->count)
+	    : [inc] "r" (1)
 	);
 
@@ -100,7 +100,7 @@
 
 	asm volatile (
-		"amoadd.d %[orig], %[inc], %[addr]\n"
-		: [orig] "=r" (orig), [addr] "+A" (val->count)
-		: [inc] "r" (-1)
+	    "amoadd.d %[orig], %[inc], %[addr]\n"
+	    : [orig] "=r" (orig), [addr] "+A" (val->count)
+	    : [inc] "r" (-1)
 	);
 
Index: kernel/arch/riscv64/include/arch/cycle.h
===================================================================
--- kernel/arch/riscv64/include/arch/cycle.h	(revision fd57745cd4811832fa23ba1cef7638038244f2b5)
+++ kernel/arch/riscv64/include/arch/cycle.h	(revision 231c770580f4400a6e0e7612723b1efb16fd5390)
@@ -43,6 +43,6 @@
 
 	asm volatile (
-		"rdcycle %[cycle]\n"
-		: [cycle] "=r" (cycle)
+	    "rdcycle %[cycle]\n"
+	    : [cycle] "=r" (cycle)
 	);
 
Index: kernel/arch/riscv64/include/arch/istate.h
===================================================================
--- kernel/arch/riscv64/include/arch/istate.h	(revision fd57745cd4811832fa23ba1cef7638038244f2b5)
+++ kernel/arch/riscv64/include/arch/istate.h	(revision 231c770580f4400a6e0e7612723b1efb16fd5390)
@@ -39,7 +39,7 @@
 
 #ifdef KERNEL
-	#include <arch/istate_struct.h>
+#include <arch/istate_struct.h>
 #else
-	#include <libarch/istate_struct.h>
+#include <libarch/istate_struct.h>
 #endif
 
Index: kernel/arch/riscv64/include/arch/mm/page.h
===================================================================
--- kernel/arch/riscv64/include/arch/mm/page.h	(revision fd57745cd4811832fa23ba1cef7638038244f2b5)
+++ kernel/arch/riscv64/include/arch/mm/page.h	(revision 231c770580f4400a6e0e7612723b1efb16fd5390)
@@ -42,9 +42,9 @@
 
 #ifndef __ASSEMBLER__
-	#define KA2PA(x)  (((uintptr_t) (x)) - UINT64_C(0xffff800000000000))
-	#define PA2KA(x)  (((uintptr_t) (x)) + UINT64_C(0xffff800000000000))
+#define KA2PA(x)  (((uintptr_t) (x)) - UINT64_C(0xffff800000000000))
+#define PA2KA(x)  (((uintptr_t) (x)) + UINT64_C(0xffff800000000000))
 #else
-	#define KA2PA(x)  ((x) - 0xffff800000000000)
-	#define PA2KA(x)  ((x) + 0xffff800000000000)
+#define KA2PA(x)  ((x) - 0xffff800000000000)
+#define PA2KA(x)  ((x) + 0xffff800000000000)
 #endif
 
Index: kernel/arch/riscv64/src/mm/page.c
===================================================================
--- kernel/arch/riscv64/src/mm/page.c	(revision fd57745cd4811832fa23ba1cef7638038244f2b5)
+++ kernel/arch/riscv64/src/mm/page.c	(revision 231c770580f4400a6e0e7612723b1efb16fd5390)
@@ -86,6 +86,6 @@
 
 	asm volatile (
-		"csrw sptbr, %[satp]\n"
-		:: [satp] "r" (satp)
+	    "csrw sptbr, %[satp]\n"
+	    :: [satp] "r" (satp)
 	);
 }
Index: kernel/arch/riscv64/src/userspace.c
===================================================================
--- kernel/arch/riscv64/src/userspace.c	(revision fd57745cd4811832fa23ba1cef7638038244f2b5)
+++ kernel/arch/riscv64/src/userspace.c	(revision 231c770580f4400a6e0e7612723b1efb16fd5390)
@@ -39,5 +39,6 @@
 {
 	// FIXME
-	while (true);
+	while (true)
+		;
 }
 
Index: kernel/arch/sparc64/include/arch/atomic.h
===================================================================
--- kernel/arch/sparc64/include/arch/atomic.h	(revision fd57745cd4811832fa23ba1cef7638038244f2b5)
+++ kernel/arch/sparc64/include/arch/atomic.h	(revision 231c770580f4400a6e0e7612723b1efb16fd5390)
@@ -64,6 +64,6 @@
 
 		asm volatile (
-			"casx %0, %2, %1\n"
-			: "+m" (*((atomic_count_t *) ptr)),
+		    "casx %0, %2, %1\n"
+		    : "+m" (*((atomic_count_t *) ptr)),
 		      "+r" (b)
 		    : "r" (a)
@@ -110,6 +110,6 @@
 
 	asm volatile (
-		"casx %0, %2, %1\n"
-		: "+m" (*((atomic_count_t *) ptr)),
+	    "casx %0, %2, %1\n"
+	    : "+m" (*((atomic_count_t *) ptr)),
 	      "+r" (v)
 	    : "r" (0)
@@ -129,18 +129,18 @@
 
 	asm volatile (
-		"0:\n"
-			"casx %0, %3, %1\n"
-			"brz %1, 2f\n"
-			"nop\n"
-		"1:\n"
-			"ldx %0, %2\n"
-			"brz %2, 0b\n"
-			"nop\n"
-			"ba,a %%xcc, 1b\n"
-		"2:\n"
-		: "+m" (*((atomic_count_t *) ptr)),
-		  "+r" (tmp1),
-		  "+r" (tmp2)
-		: "r" (0)
+	    "0:\n"
+	    "casx %0, %3, %1\n"
+	    "brz %1, 2f\n"
+	    "nop\n"
+	    "1:\n"
+	    "ldx %0, %2\n"
+	    "brz %2, 0b\n"
+	    "nop\n"
+	    "ba,a %%xcc, 1b\n"
+	    "2:\n"
+	    : "+m" (*((atomic_count_t *) ptr)),
+	      "+r" (tmp1),
+	      "+r" (tmp2)
+	    : "r" (0)
 	);
 
Index: kernel/arch/sparc64/include/arch/barrier.h
===================================================================
--- kernel/arch/sparc64/include/arch/barrier.h	(revision fd57745cd4811832fa23ba1cef7638038244f2b5)
+++ kernel/arch/sparc64/include/arch/barrier.h	(revision 231c770580f4400a6e0e7612723b1efb16fd5390)
@@ -96,7 +96,7 @@
 
 	asm volatile (
-		"rd %%pc, %[pc]\n"
-		"flush %[pc]\n"
-		: [pc] "=&r" (pc)
+	    "rd %%pc, %[pc]\n"
+	    "flush %[pc]\n"
+	    : [pc] "=&r" (pc)
 	);
 }
@@ -106,5 +106,5 @@
 {
 	asm volatile (
-		"membar #Sync\n"
+	    "membar #Sync\n"
 	);
 }
Index: kernel/arch/sparc64/include/arch/cpu_family.h
===================================================================
--- kernel/arch/sparc64/include/arch/cpu_family.h	(revision fd57745cd4811832fa23ba1cef7638038244f2b5)
+++ kernel/arch/sparc64/include/arch/cpu_family.h	(revision 231c770580f4400a6e0e7612723b1efb16fd5390)
@@ -50,5 +50,5 @@
 	int impl = ((ver_reg_t) ver_read()).impl;
 	return (impl == IMPL_ULTRASPARCI) || (impl == IMPL_ULTRASPARCII) ||
-	       (impl == IMPL_ULTRASPARCII_I) ||  (impl == IMPL_ULTRASPARCII_E);
+	    (impl == IMPL_ULTRASPARCII_I) ||  (impl == IMPL_ULTRASPARCII_E);
 }
 
@@ -62,6 +62,6 @@
 	int impl = ((ver_reg_t) ver_read()).impl;
 	return (impl == IMPL_ULTRASPARCIII) ||
-	       (impl == IMPL_ULTRASPARCIII_PLUS) ||
-	       (impl == IMPL_ULTRASPARCIII_I);
+	    (impl == IMPL_ULTRASPARCIII_PLUS) ||
+	    (impl == IMPL_ULTRASPARCIII_I);
 }
 
Index: kernel/arch/sparc64/include/arch/drivers/niagara_buf.h
===================================================================
--- kernel/arch/sparc64/include/arch/drivers/niagara_buf.h	(revision fd57745cd4811832fa23ba1cef7638038244f2b5)
+++ kernel/arch/sparc64/include/arch/drivers/niagara_buf.h	(revision 231c770580f4400a6e0e7612723b1efb16fd5390)
@@ -50,5 +50,5 @@
 	uint64_t write_ptr;
 	char data[OUTPUT_BUFFER_SIZE];
-} __attribute__ ((packed)) niagara_output_buffer_t;
+} __attribute__((packed)) niagara_output_buffer_t;
 
 #define INPUT_BUFFER_SIZE  ((PAGE_SIZE) - 2 * 8)
@@ -58,5 +58,5 @@
 	uint64_t read_ptr;
 	char data[INPUT_BUFFER_SIZE];
-} __attribute__ ((packed)) niagara_input_buffer_t;
+} __attribute__((packed)) niagara_input_buffer_t;
 
 /** @}
Index: kernel/arch/sparc64/include/arch/mm/page.h
===================================================================
--- kernel/arch/sparc64/include/arch/mm/page.h	(revision fd57745cd4811832fa23ba1cef7638038244f2b5)
+++ kernel/arch/sparc64/include/arch/mm/page.h	(revision 231c770580f4400a6e0e7612723b1efb16fd5390)
@@ -68,5 +68,5 @@
 		uint64_t vpn : 51;		/**< Virtual Page Number. */
 		unsigned offset : 13;		/**< Offset. */
-	} __attribute__ ((packed));
+	} __attribute__((packed));
 } page_address_t;
 
Index: kernel/arch/sparc64/include/arch/mm/sun4u/as.h
===================================================================
--- kernel/arch/sparc64/include/arch/mm/sun4u/as.h	(revision fd57745cd4811832fa23ba1cef7638038244f2b5)
+++ kernel/arch/sparc64/include/arch/mm/sun4u/as.h	(revision 231c770580f4400a6e0e7612723b1efb16fd5390)
@@ -56,5 +56,5 @@
 		unsigned : 6;
 		uint64_t va_tag : 42;	/**< Virtual address bits <63:22>. */
-	} __attribute__ ((packed));
+	} __attribute__((packed));
 } tsb_tag_target_t;
 
@@ -63,5 +63,5 @@
 	tsb_tag_target_t tag;
 	tte_data_t data;
-} __attribute__ ((packed)) tsb_entry_t;
+} __attribute__((packed)) tsb_entry_t;
 
 typedef struct {
Index: kernel/arch/sparc64/include/arch/mm/sun4u/frame.h
===================================================================
--- kernel/arch/sparc64/include/arch/mm/sun4u/frame.h	(revision fd57745cd4811832fa23ba1cef7638038244f2b5)
+++ kernel/arch/sparc64/include/arch/mm/sun4u/frame.h	(revision 231c770580f4400a6e0e7612723b1efb16fd5390)
@@ -69,5 +69,5 @@
 #endif
 		unsigned offset : 13;		/**< Offset. */
-	} __attribute__ ((packed));
+	} __attribute__((packed));
 };
 
Index: kernel/arch/sparc64/include/arch/mm/sun4u/mmu.h
===================================================================
--- kernel/arch/sparc64/include/arch/mm/sun4u/mmu.h	(revision fd57745cd4811832fa23ba1cef7638038244f2b5)
+++ kernel/arch/sparc64/include/arch/mm/sun4u/mmu.h	(revision 231c770580f4400a6e0e7612723b1efb16fd5390)
@@ -112,5 +112,5 @@
 		unsigned ic : 1;	/**< I-Cache enable. */
 
-	} __attribute__ ((packed));
+	} __attribute__((packed));
 } lsu_cr_reg_t;
 #endif /* US */
Index: kernel/arch/sparc64/include/arch/mm/sun4u/tlb.h
===================================================================
--- kernel/arch/sparc64/include/arch/mm/sun4u/tlb.h	(revision fd57745cd4811832fa23ba1cef7638038244f2b5)
+++ kernel/arch/sparc64/include/arch/mm/sun4u/tlb.h	(revision 231c770580f4400a6e0e7612723b1efb16fd5390)
@@ -109,5 +109,5 @@
 		unsigned long : 51;
 		unsigned context : 13;		/**< Context/ASID. */
-	} __attribute__ ((packed));
+	} __attribute__((packed));
 };
 typedef union tlb_context_reg tlb_context_reg_t;
@@ -126,5 +126,5 @@
 		unsigned tlb_entry : 6;
 		unsigned : 3;
-	} __attribute__ ((packed));
+	} __attribute__((packed));
 };
 typedef union tlb_data_access_addr dtlb_data_access_addr_t;
@@ -155,5 +155,5 @@
 		unsigned local_tlb_entry : 9;
 		unsigned : 3;
-	} __attribute__ ((packed));
+	} __attribute__((packed));
 };
 typedef union dtlb_data_access_addr dtlb_data_access_addr_t;
@@ -169,5 +169,5 @@
 		unsigned local_tlb_entry : 7;
 		unsigned : 3;
-	} __attribute__ ((packed));
+	} __attribute__((packed));
 };
 typedef union itlb_data_access_addr itlb_data_access_addr_t;
@@ -182,5 +182,5 @@
 		uint64_t vpn : 51;	/**< Virtual Address bits 63:13. */
 		unsigned context : 13;	/**< Context identifier. */
-	} __attribute__ ((packed));
+	} __attribute__((packed));
 };
 typedef union tlb_tag_read_reg tlb_tag_read_reg_t;
@@ -192,5 +192,5 @@
 	uint64_t value;
 	struct {
-		uint64_t vpn: 51;	/**< Virtual Address bits 63:13. */
+		uint64_t vpn : 51;	/**< Virtual Address bits 63:13. */
 #if defined (US)
 		unsigned : 6;		/**< Ignored. */
@@ -198,9 +198,9 @@
 #elif defined (US3)
 		unsigned : 5;		/**< Ignored. */
-		unsigned type: 2;	/**< The type of demap operation. */
+		unsigned type : 2;	/**< The type of demap operation. */
 #endif
 		unsigned context : 2;	/**< Context register selection. */
 		unsigned : 4;		/**< Zero. */
-	} __attribute__ ((packed));
+	} __attribute__((packed));
 };
 typedef union tlb_demap_addr tlb_demap_addr_t;
@@ -229,5 +229,5 @@
 		unsigned ow : 1;	/**< Overwrite bit. */
 		unsigned fv : 1;	/**< Fault Valid bit. */
-	} __attribute__ ((packed));
+	} __attribute__((packed));
 };
 typedef union tlb_sfsr_reg tlb_sfsr_reg_t;
@@ -436,5 +436,5 @@
  */
 NO_TRACE static inline void itlb_data_access_write(int tlb, size_t entry,
-	uint64_t value)
+    uint64_t value)
 {
 	itlb_data_access_addr_t reg;
@@ -472,5 +472,5 @@
  */
 NO_TRACE static inline void dtlb_data_access_write(int tlb, size_t entry,
-	uint64_t value)
+    uint64_t value)
 {
 	dtlb_data_access_addr_t reg;
Index: kernel/arch/sparc64/include/arch/mm/sun4u/tsb.h
===================================================================
--- kernel/arch/sparc64/include/arch/mm/sun4u/tsb.h	(revision fd57745cd4811832fa23ba1cef7638038244f2b5)
+++ kernel/arch/sparc64/include/arch/mm/sun4u/tsb.h	(revision 231c770580f4400a6e0e7612723b1efb16fd5390)
@@ -75,5 +75,5 @@
 		unsigned size : 3;	/**< TSB size. Number of entries is
 					 * 512 * 2^size. */
-	} __attribute__ ((packed));
+	} __attribute__((packed));
 } tsb_base_reg_t;
 
Index: kernel/arch/sparc64/include/arch/mm/sun4u/tte.h
===================================================================
--- kernel/arch/sparc64/include/arch/mm/sun4u/tte.h	(revision fd57745cd4811832fa23ba1cef7638038244f2b5)
+++ kernel/arch/sparc64/include/arch/mm/sun4u/tte.h	(revision 231c770580f4400a6e0e7612723b1efb16fd5390)
@@ -63,5 +63,5 @@
 		unsigned : 6;		/**< Reserved. */
 		uint64_t va_tag : 42;	/**< Virtual Address Tag, bits 63:22. */
-	} __attribute__ ((packed));
+	} __attribute__((packed));
 };
 
@@ -92,5 +92,5 @@
 		unsigned w : 1;		/**< Writable. */
 		unsigned g : 1;		/**< Global. */
-	} __attribute__ ((packed));
+	} __attribute__((packed));
 };
 
Index: kernel/arch/sparc64/include/arch/mm/sun4v/as.h
===================================================================
--- kernel/arch/sparc64/include/arch/mm/sun4v/as.h	(revision fd57745cd4811832fa23ba1cef7638038244f2b5)
+++ kernel/arch/sparc64/include/arch/mm/sun4v/as.h	(revision 231c770580f4400a6e0e7612723b1efb16fd5390)
@@ -63,5 +63,5 @@
 		unsigned : 6;
 		uint64_t va_tag : 42;	/**< Virtual address bits <63:22>. */
-	} __attribute__ ((packed));
+	} __attribute__((packed));
 } tte_tag_t;
 
@@ -70,5 +70,5 @@
 	tte_tag_t tag;
 	tte_data_t data;
-} __attribute__ ((packed)) tsb_entry_t;
+} __attribute__((packed)) tsb_entry_t;
 
 typedef struct {
Index: kernel/arch/sparc64/include/arch/mm/sun4v/page.h
===================================================================
--- kernel/arch/sparc64/include/arch/mm/sun4v/page.h	(revision fd57745cd4811832fa23ba1cef7638038244f2b5)
+++ kernel/arch/sparc64/include/arch/mm/sun4v/page.h	(revision 231c770580f4400a6e0e7612723b1efb16fd5390)
@@ -60,5 +60,5 @@
 		uint64_t vpn : 51;		/**< Virtual Page Number. */
 		unsigned offset : 13;		/**< Offset. */
-	} __attribute__ ((packed));
+	} __attribute__((packed));
 } page_address_t;
 
Index: kernel/arch/sparc64/include/arch/mm/sun4v/tlb.h
===================================================================
--- kernel/arch/sparc64/include/arch/mm/sun4v/tlb.h	(revision fd57745cd4811832fa23ba1cef7638038244f2b5)
+++ kernel/arch/sparc64/include/arch/mm/sun4v/tlb.h	(revision 231c770580f4400a6e0e7612723b1efb16fd5390)
@@ -68,5 +68,5 @@
 	uint64_t dfc;		/**< Data fault context (DFC) */
 	uint8_t reserved2[0x28];
-} __attribute__ ((packed)) mmu_fault_status_area_t;
+} __attribute__((packed)) mmu_fault_status_area_t;
 
 #define DTLB_MAX_LOCKED_ENTRIES		8
@@ -126,5 +126,6 @@
  * @param mmu_flag	MMU_FLAG_DTLB, MMU_FLAG_ITLB or a combination of both
  */
-NO_TRACE static inline void mmu_demap_ctx(int context, int mmu_flag) {
+NO_TRACE static inline void mmu_demap_ctx(int context, int mmu_flag)
+{
 	__hypercall_fast4(MMU_DEMAP_CTX, 0, 0, context, mmu_flag);
 }
@@ -137,5 +138,6 @@
  * @param mmu_flag	MMU_FLAG_DTLB, MMU_FLAG_ITLB or a combination of both
  */
-NO_TRACE static inline void mmu_demap_page(uintptr_t vaddr, int context, int mmu_flag) {
+NO_TRACE static inline void mmu_demap_page(uintptr_t vaddr, int context, int mmu_flag)
+{
 	__hypercall_fast5(MMU_DEMAP_PAGE, 0, 0, vaddr, context, mmu_flag);
 }
Index: kernel/arch/sparc64/include/arch/mm/sun4v/tsb.h
===================================================================
--- kernel/arch/sparc64/include/arch/mm/sun4v/tsb.h	(revision fd57745cd4811832fa23ba1cef7638038244f2b5)
+++ kernel/arch/sparc64/include/arch/mm/sun4v/tsb.h	(revision 231c770580f4400a6e0e7612723b1efb16fd5390)
@@ -65,5 +65,5 @@
 	uint64_t tsb_base;	/**< Real address of TSB base. */
 	uint64_t reserved;
-} __attribute__ ((packed)) tsb_descr_t;
+} __attribute__((packed)) tsb_descr_t;
 
 
Index: kernel/arch/sparc64/include/arch/mm/sun4v/tte.h
===================================================================
--- kernel/arch/sparc64/include/arch/mm/sun4v/tte.h	(revision fd57745cd4811832fa23ba1cef7638038244f2b5)
+++ kernel/arch/sparc64/include/arch/mm/sun4v/tte.h	(revision 231c770580f4400a6e0e7612723b1efb16fd5390)
@@ -69,5 +69,5 @@
 		unsigned soft2 : 2;	/**< Software defined field. */
 		unsigned size : 4;	/**< Page size. */
-	} __attribute__ ((packed));
+	} __attribute__((packed));
 };
 
Index: kernel/arch/sparc64/include/arch/register.h
===================================================================
--- kernel/arch/sparc64/include/arch/register.h	(revision fd57745cd4811832fa23ba1cef7638038244f2b5)
+++ kernel/arch/sparc64/include/arch/register.h	(revision 231c770580f4400a6e0e7612723b1efb16fd5390)
@@ -50,5 +50,5 @@
 		unsigned : 3;
 		unsigned maxwin : 5;
-	} __attribute__ ((packed));
+	} __attribute__((packed));
 };
 typedef union ver_reg ver_reg_t;
@@ -70,5 +70,5 @@
 		unsigned ie : 1;	/**< Interrupt Enable. */
 		unsigned ag : 1;	/**< Alternate Globals*/
-	} __attribute__ ((packed));
+	} __attribute__((packed));
 };
 typedef union pstate_reg pstate_reg_t;
@@ -80,5 +80,5 @@
 		unsigned npt : 1;	/**< Non-privileged Trap enable. */
 		uint64_t counter : 63;	/**< Elapsed CPU clck cycle counter. */
-	} __attribute__ ((packed));
+	} __attribute__((packed));
 };
 typedef union tick_reg tick_reg_t;
@@ -90,5 +90,5 @@
 		unsigned int_dis : 1;		/**< TICK_INT interrupt disabled flag. */
 		uint64_t tick_cmpr : 63;	/**< Compare value for TICK interrupts. */
-	} __attribute__ ((packed));
+	} __attribute__((packed));
 };
 typedef union tick_compare_reg tick_compare_reg_t;
@@ -102,5 +102,5 @@
 		unsigned int_level : 15;
 		unsigned tick_int : 1;
-	} __attribute__ ((packed));
+	} __attribute__((packed));
 };
 typedef union softint_reg softint_reg_t;
@@ -114,5 +114,5 @@
 		unsigned du : 1;
 		unsigned dl : 1;
-	} __attribute__ ((packed));
+	} __attribute__((packed));
 };
 typedef union fprs_reg fprs_reg_t;
Index: kernel/arch/sparc64/include/arch/sun4u/asm.h
===================================================================
--- kernel/arch/sparc64/include/arch/sun4u/asm.h	(revision fd57745cd4811832fa23ba1cef7638038244f2b5)
+++ kernel/arch/sparc64/include/arch/sun4u/asm.h	(revision 231c770580f4400a6e0e7612723b1efb16fd5390)
@@ -48,6 +48,6 @@
 
 	asm volatile (
-		"rdpr %%ver, %[v]\n"
-		: [v] "=r" (v)
+	    "rdpr %%ver, %[v]\n"
+	    : [v] "=r" (v)
 	);
 
Index: kernel/arch/sparc64/include/arch/sun4v/hypercall.h
===================================================================
--- kernel/arch/sparc64/include/arch/sun4v/hypercall.h	(revision fd57745cd4811832fa23ba1cef7638038244f2b5)
+++ kernel/arch/sparc64/include/arch/sun4v/hypercall.h	(revision 231c770580f4400a6e0e7612723b1efb16fd5390)
@@ -152,5 +152,5 @@
  */
 static inline uint64_t
-__hypercall_fast(const uint64_t p1, const uint64_t p2, const uint64_t p3,
+    __hypercall_fast(const uint64_t p1, const uint64_t p2, const uint64_t p3,
     const uint64_t p4, const uint64_t p5, const uint64_t function_number)
 {
@@ -163,9 +163,9 @@
 
 	asm volatile (
-		"ta %7\n"
-		: "=r" (a1)
-		: "r" (a1), "r" (a2), "r" (a3), "r" (a4), "r" (a5), "r" (a6),
-		  "i" (FAST_TRAP)
-		: "memory"
+	    "ta %7\n"
+	    : "=r" (a1)
+	    : "r" (a1), "r" (a2), "r" (a3), "r" (a4), "r" (a5), "r" (a6),
+	      "i" (FAST_TRAP)
+	    : "memory"
 	);
 
@@ -187,5 +187,5 @@
  */
 static inline uint64_t
-__hypercall_fast_ret1(const uint64_t p1, const uint64_t p2, const uint64_t p3,
+    __hypercall_fast_ret1(const uint64_t p1, const uint64_t p2, const uint64_t p3,
     const uint64_t p4, const uint64_t p5, const uint64_t function_number,
     uint64_t *ret1)
@@ -199,9 +199,9 @@
 
 	asm volatile (
-		"ta %8\n"
-		: "=r" (a1), "=r" (a2)
-		: "r" (a1), "r" (a2), "r" (a3), "r" (a4), "r" (a5), "r" (a6),
-		  "i" (FAST_TRAP)
-		: "memory"
+	    "ta %8\n"
+	    : "=r" (a1), "=r" (a2)
+	    : "r" (a1), "r" (a2), "r" (a3), "r" (a4), "r" (a5), "r" (a6),
+	      "i" (FAST_TRAP)
+	    : "memory"
 	);
 
@@ -223,5 +223,5 @@
  */
 static inline uint64_t
-__hypercall_hyperfast(const uint64_t p1, const uint64_t p2, const uint64_t p3,
+    __hypercall_hyperfast(const uint64_t p1, const uint64_t p2, const uint64_t p3,
     const uint64_t p4, const uint64_t p5, const uint64_t sw_trap_number)
 {
@@ -233,9 +233,9 @@
 
 	asm volatile (
-		"ta %6\n"
-		: "=r" (a1)
-		: "r" (a1), "r" (a2), "r" (a3), "r" (a4), "r" (a5),
-		  "i" (sw_trap_number)
-		: "memory"
+	    "ta %6\n"
+	    : "=r" (a1)
+	    : "r" (a1), "r" (a2), "r" (a3), "r" (a4), "r" (a5),
+	      "i" (sw_trap_number)
+	    : "memory"
 	);
 
Index: kernel/arch/sparc64/include/arch/sun4v/register.h
===================================================================
--- kernel/arch/sparc64/include/arch/sun4v/register.h	(revision fd57745cd4811832fa23ba1cef7638038244f2b5)
+++ kernel/arch/sparc64/include/arch/sun4v/register.h	(revision 231c770580f4400a6e0e7612723b1efb16fd5390)
@@ -53,5 +53,5 @@
 		unsigned ie : 1;	/**< Interrupt Enable. */
 		unsigned : 1;
-	} __attribute__ ((packed));
+	} __attribute__((packed));
 };
 typedef union pstate_reg pstate_reg_t;
Index: kernel/arch/sparc64/src/cpu/sun4u/cpu.c
===================================================================
--- kernel/arch/sparc64/src/cpu/sun4u/cpu.c	(revision fd57745cd4811832fa23ba1cef7638038244f2b5)
+++ kernel/arch/sparc64/src/cpu/sun4u/cpu.c	(revision 231c770580f4400a6e0e7612723b1efb16fd5390)
@@ -99,9 +99,9 @@
 			int f;
 			f = find_cpu_frequency(
-				ofw_tree_find_child(node, "cpu@0"));
+			    ofw_tree_find_child(node, "cpu@0"));
 			if (f != -1)
 				clock_frequency = (uint32_t) f;
 			f = find_cpu_frequency(
-				ofw_tree_find_child(node, "cpu@1"));
+			    ofw_tree_find_child(node, "cpu@1"));
 			if (f != -1)
 				clock_frequency = (uint32_t) f;
@@ -140,5 +140,5 @@
 		break;
 	case MANUF_SUN:
-	    	manuf = "Sun";
+		manuf = "Sun";
 		break;
 	default:
@@ -184,5 +184,5 @@
 
 	printf("cpu%d: manuf=%s, impl=%s, mask=%d (%d MHz)\n", m->id, manuf,
-		impl, m->arch.ver.mask, m->arch.clock_frequency / 1000000);
+	    impl, m->arch.ver.mask, m->arch.clock_frequency / 1000000);
 }
 
Index: kernel/arch/sparc64/src/cpu/sun4v/cpu.c
===================================================================
--- kernel/arch/sparc64/src/cpu/sun4v/cpu.c	(revision fd57745cd4811832fa23ba1cef7638038244f2b5)
+++ kernel/arch/sparc64/src/cpu/sun4v/cpu.c	(revision 231c770580f4400a6e0e7612723b1efb16fd5390)
@@ -66,5 +66,5 @@
 			uint64_t clock_frequency = 0;
 			md_get_integer_property(node, "clock-frequency",
-				&clock_frequency);
+			    &clock_frequency);
 			CPU->arch.clock_frequency = clock_frequency;
 			break;
Index: kernel/arch/sparc64/src/debug/stacktrace.c
===================================================================
--- kernel/arch/sparc64/src/debug/stacktrace.c	(revision fd57745cd4811832fa23ba1cef7638038244f2b5)
+++ kernel/arch/sparc64/src/debug/stacktrace.c	(revision 231c770580f4400a6e0e7612723b1efb16fd5390)
@@ -98,5 +98,5 @@
 }
 
-bool uspace_return_address_get(stack_trace_context_t *ctx , uintptr_t *ra)
+bool uspace_return_address_get(stack_trace_context_t *ctx, uintptr_t *ra)
 {
 	return false;
Index: kernel/arch/sparc64/src/drivers/niagara.c
===================================================================
--- kernel/arch/sparc64/src/drivers/niagara.c	(revision fd57745cd4811832fa23ba1cef7638038244f2b5)
+++ kernel/arch/sparc64/src/drivers/niagara.c	(revision 231c770580f4400a6e0e7612723b1efb16fd5390)
@@ -82,5 +82,5 @@
  * buffer definition follows.
  */
-static volatile niagara_output_buffer_t __attribute__ ((aligned(PAGE_SIZE)))
+static volatile niagara_output_buffer_t __attribute__((aligned(PAGE_SIZE)))
     output_buffer;
 
@@ -90,5 +90,5 @@
  * Analogous to the output_buffer, see the previous definition.
  */
-static volatile niagara_input_buffer_t __attribute__ ((aligned(PAGE_SIZE)))
+static volatile niagara_input_buffer_t __attribute__((aligned(PAGE_SIZE)))
     input_buffer;
 
@@ -96,7 +96,9 @@
 
 /** Write a single character to the standard output. */
-static inline void do_putchar(const char c) {
+static inline void do_putchar(const char c)
+{
 	/* Repeat until the buffer is non-full */
-	while (__hypercall_fast1(CONS_PUTCHAR, c) == HV_EWOULDBLOCK);
+	while (__hypercall_fast1(CONS_PUTCHAR, c) == HV_EWOULDBLOCK)
+		;
 }
 
@@ -160,5 +162,6 @@
  *
  */
-static void kniagarapoll(void *arg) {
+static void kniagarapoll(void *arg)
+{
 	while (true) {
 		niagara_poll();
@@ -213,5 +216,5 @@
 	    PAGE_SIZE);
 	sysinfo_set_item_val("niagara.inbuf.datasize", NULL,
-	   INPUT_BUFFER_SIZE);
+	    INPUT_BUFFER_SIZE);
 
 	outbuf_parea.pbase = (uintptr_t) (KA2PA(&output_buffer));
Index: kernel/arch/sparc64/src/drivers/tick.c
===================================================================
--- kernel/arch/sparc64/src/drivers/tick.c	(revision fd57745cd4811832fa23ba1cef7638038244f2b5)
+++ kernel/arch/sparc64/src/drivers/tick.c	(revision 231c770580f4400a6e0e7612723b1efb16fd5390)
@@ -54,5 +54,5 @@
 	compare.int_dis = false;
 	compare.tick_cmpr = tick_counter_read() +
-		CPU->arch.clock_frequency / HZ;
+	    CPU->arch.clock_frequency / HZ;
 	CPU->arch.next_tick_cmpr = compare.tick_cmpr;
 	tick_compare_write(compare.value);
Index: kernel/arch/sparc64/src/mm/sun4v/tlb.c
===================================================================
--- kernel/arch/sparc64/src/mm/sun4v/tlb.c	(revision fd57745cd4811832fa23ba1cef7638038244f2b5)
+++ kernel/arch/sparc64/src/mm/sun4v/tlb.c	(revision 231c770580f4400a6e0e7612723b1efb16fd5390)
@@ -103,5 +103,5 @@
 	"unaligned access",
 	"invalid page size"
-	};
+};
 
 /** Array of MMU fault status areas. */
@@ -146,9 +146,9 @@
 	if (locked) {
 		__hypercall_fast4(
-			MMU_MAP_PERM_ADDR, page, 0, data.value, MMU_FLAG_DTLB);
+		    MMU_MAP_PERM_ADDR, page, 0, data.value, MMU_FLAG_DTLB);
 	} else {
 		__hypercall_hyperfast(
-			page, ASID_KERNEL, data.value, MMU_FLAG_DTLB, 0,
-			MMU_MAP_ADDR);
+		    page, ASID_KERNEL, data.value, MMU_FLAG_DTLB, 0,
+		    MMU_MAP_ADDR);
 	}
 }
@@ -180,5 +180,5 @@
 
 	__hypercall_hyperfast(
-		t->page, t->as->asid, data.value, MMU_FLAG_DTLB, 0, MMU_MAP_ADDR);
+	    t->page, t->as->asid, data.value, MMU_FLAG_DTLB, 0, MMU_MAP_ADDR);
 }
 
@@ -205,5 +205,5 @@
 
 	__hypercall_hyperfast(
-		t->page, t->as->asid, data.value, MMU_FLAG_ITLB, 0, MMU_MAP_ADDR);
+	    t->page, t->as->asid, data.value, MMU_FLAG_ITLB, 0, MMU_MAP_ADDR);
 }
 
@@ -349,5 +349,5 @@
 
 	printf("condition which caused the fault: %s\n",
-		fault_types[mmu_fsas[myid].dft]);
+	    fault_types[mmu_fsas[myid].dft]);
 }
 
@@ -356,5 +356,5 @@
 {
 	uint64_t errno =  __hypercall_fast3(MMU_DEMAP_ALL, 0, 0,
-		MMU_FLAG_DTLB | MMU_FLAG_ITLB);
+	    MMU_FLAG_DTLB | MMU_FLAG_ITLB);
 	if (errno != HV_EOK)
 		panic("Error code = %" PRIu64 ".\n", errno);
@@ -372,5 +372,5 @@
 
 	__hypercall_fast4(MMU_DEMAP_CTX, 0, 0, asid,
-		MMU_FLAG_ITLB | MMU_FLAG_DTLB);
+	    MMU_FLAG_ITLB | MMU_FLAG_DTLB);
 
 	nucleus_leave();
Index: kernel/arch/sparc64/src/proc/thread.c
===================================================================
--- kernel/arch/sparc64/src/proc/thread.c	(revision fd57745cd4811832fa23ba1cef7638038244f2b5)
+++ kernel/arch/sparc64/src/proc/thread.c	(revision 231c770580f4400a6e0e7612723b1efb16fd5390)
@@ -64,6 +64,5 @@
 void thread_create_arch(thread_t *t)
 {
-	if ((t->uspace) && (!t->arch.uspace_window_buffer))
-		{
+	if ((t->uspace) && (!t->arch.uspace_window_buffer)) {
 		/*
 		 * The thread needs userspace window buffer and the object
Index: kernel/arch/sparc64/src/smp/sun4u/ipi.c
===================================================================
--- kernel/arch/sparc64/src/smp/sun4u/ipi.c	(revision fd57745cd4811832fa23ba1cef7638038244f2b5)
+++ kernel/arch/sparc64/src/smp/sun4u/ipi.c	(revision 231c770580f4400a6e0e7612723b1efb16fd5390)
@@ -59,5 +59,5 @@
  * @param func value the first data item of the vector will be set to
  */
-static inline void set_intr_w_data(void (* func)(void))
+static inline void set_intr_w_data(void (*func)(void))
 {
 #if defined (US)
@@ -87,5 +87,5 @@
  * @param func Function to be invoked.
  */
-static void cross_call(int mid, void (* func)(void))
+static void cross_call(int mid, void (*func)(void))
 {
 	uint64_t status;
@@ -148,5 +148,5 @@
 	unsigned int i;
 
-	void (* func)(void);
+	void (*func)(void);
 
 	switch (ipi) {
Index: kernel/arch/sparc64/src/smp/sun4u/smp.c
===================================================================
--- kernel/arch/sparc64/src/smp/sun4u/smp.c	(revision fd57745cd4811832fa23ba1cef7638038244f2b5)
+++ kernel/arch/sparc64/src/smp/sun4u/smp.c	(revision 231c770580f4400a6e0e7612723b1efb16fd5390)
@@ -121,5 +121,5 @@
 		node = ofw_tree_find_child_by_device_type(cpus_parent(), "cpu");
 		for (i = 0; node;
-                     node = ofw_tree_find_peer_by_device_type(node, "cpu"), i++)
+		    node = ofw_tree_find_peer_by_device_type(node, "cpu"), i++)
 			wakeup_cpu(node);
 	} else if (is_us_iv()) {
Index: kernel/arch/sparc64/src/smp/sun4v/ipi.c
===================================================================
--- kernel/arch/sparc64/src/smp/sun4v/ipi.c	(revision fd57745cd4811832fa23ba1cef7638038244f2b5)
+++ kernel/arch/sparc64/src/smp/sun4v/ipi.c	(revision 231c770580f4400a6e0e7612723b1efb16fd5390)
@@ -45,5 +45,5 @@
 
 static uint64_t data[MAX_NUM_STRANDS][IPI_MESSAGE_SIZE]
-	__attribute__ ((aligned (64)));
+    __attribute__((aligned(64)));
 
 static uint16_t ipi_cpu_list[MAX_NUM_STRANDS][MAX_NUM_STRANDS];
@@ -60,5 +60,6 @@
  */
 uint64_t ipi_brodcast_to(void (*func)(void), uint16_t cpu_list[MAX_NUM_STRANDS],
-		uint64_t list_size) {
+    uint64_t list_size)
+{
 
 	data[CPU->arch.id][0] = (uint64_t) func;
@@ -70,5 +71,5 @@
 
 	return __hypercall_fast3(CPU_MONDO_SEND, list_size,
-		KA2PA(ipi_cpu_list[CPU->arch.id]), KA2PA(data[CPU->arch.id]));
+	    KA2PA(ipi_cpu_list[CPU->arch.id]), KA2PA(data[CPU->arch.id]));
 }
 
@@ -81,5 +82,6 @@
  * @return		error code returned by the CPU_MONDO_SEND hypercall
  */
-uint64_t ipi_unicast_to(void (*func)(void), uint16_t cpu_id) {
+uint64_t ipi_unicast_to(void (*func)(void), uint16_t cpu_id)
+{
 	ipi_cpu_list[CPU->arch.id][0] = cpu_id;
 	return ipi_brodcast_to(func, ipi_cpu_list[CPU->arch.id], 1);
@@ -95,5 +97,5 @@
 void ipi_broadcast_arch(int ipi)
 {
-	void (* func)(void);
+	void (*func)(void);
 
 	switch (ipi) {
Index: kernel/arch/sparc64/src/smp/sun4v/smp.c
===================================================================
--- kernel/arch/sparc64/src/smp/sun4v/smp.c	(revision fd57745cd4811832fa23ba1cef7638038244f2b5)
+++ kernel/arch/sparc64/src/smp/sun4v/smp.c	(revision 231c770580f4400a6e0e7612723b1efb16fd5390)
@@ -88,5 +88,6 @@
  * stored to the proposed_nrdy variable of the cpu_arch_t struture.
  */
-bool calculate_optimal_nrdy(exec_unit_t *exec_unit) {
+bool calculate_optimal_nrdy(exec_unit_t *exec_unit)
+{
 
 	/* calculate the number of threads the core will steal */
@@ -103,5 +104,5 @@
 	for (k = 0; k < exec_unit->strand_count; k++) {
 		exec_units->cpus[k]->arch.proposed_nrdy =
-			atomic_get(&(exec_unit->cpus[k]->nrdy));
+		    atomic_get(&(exec_unit->cpus[k]->nrdy));
 	}
 
@@ -112,13 +113,12 @@
 		unsigned int least_busy = 0;
 		unsigned int least_busy_nrdy =
-			exec_unit->cpus[0]->arch.proposed_nrdy;
+		    exec_unit->cpus[0]->arch.proposed_nrdy;
 
 		/* for each stolen thread, give it to the least busy CPU */
 		for (k = 0; k < exec_unit->strand_count; k++) {
-			if (exec_unit->cpus[k]->arch.proposed_nrdy
-					< least_busy_nrdy) {
+			if (exec_unit->cpus[k]->arch.proposed_nrdy < least_busy_nrdy) {
 				least_busy = k;
 				least_busy_nrdy =
-					exec_unit->cpus[k]->arch.proposed_nrdy;
+				    exec_unit->cpus[k]->arch.proposed_nrdy;
 			}
 		}
@@ -247,6 +247,6 @@
 			exec_units[i].strand_count++;
 			max_core_strands =
-				exec_units[i].strand_count > max_core_strands ?
-				exec_units[i].strand_count : max_core_strands;
+			    exec_units[i].strand_count > max_core_strands ?
+			    exec_units[i].strand_count : max_core_strands;
 
 		/* detecting execution unit failed */
Index: kernel/arch/sparc64/src/sun4u/sparc64.c
===================================================================
--- kernel/arch/sparc64/src/sun4u/sparc64.c	(revision fd57745cd4811832fa23ba1cef7638038244f2b5)
+++ kernel/arch/sparc64/src/sun4u/sparc64.c	(revision 231c770580f4400a6e0e7612723b1efb16fd5390)
@@ -169,5 +169,6 @@
 
 	/* Not reached */
-	while (1);
+	while (1)
+		;
 }
 
@@ -175,5 +176,6 @@
 {
 	// TODO
-	while (1);
+	while (1)
+		;
 }
 
Index: kernel/arch/sparc64/src/sun4v/sparc64.c
===================================================================
--- kernel/arch/sparc64/src/sun4v/sparc64.c	(revision fd57745cd4811832fa23ba1cef7638038244f2b5)
+++ kernel/arch/sparc64/src/sun4v/sparc64.c	(revision 231c770580f4400a6e0e7612723b1efb16fd5390)
@@ -167,5 +167,6 @@
 
 	/* Not reached */
-	while (1);
+	while (1)
+		;
 }
 
@@ -173,5 +174,6 @@
 {
 	// TODO
-	while (1);
+	while (1)
+		;
 }
 
Index: kernel/arch/sparc64/src/trap/sun4v/interrupt.c
===================================================================
--- kernel/arch/sparc64/src/trap/sun4v/interrupt.c	(revision fd57745cd4811832fa23ba1cef7638038244f2b5)
+++ kernel/arch/sparc64/src/trap/sun4v/interrupt.c	(revision 231c770580f4400a6e0e7612723b1efb16fd5390)
@@ -74,6 +74,5 @@
  */
 uint64_t cpu_mondo_queues[MAX_NUM_STRANDS][CPU_MONDO_QUEUE_SIZE]
-	__attribute__((aligned(
-	CPU_MONDO_QUEUE_SIZE * sizeof(uint64_t))));
+    __attribute__((aligned(CPU_MONDO_QUEUE_SIZE * sizeof(uint64_t))));
 
 /**
@@ -83,10 +82,10 @@
 {
 	if (__hypercall_fast3(
-		CPU_QCONF,
-		CPU_MONDO_QUEUE_ID,
-		KA2PA(cpu_mondo_queues[CPU->id]),
-		CPU_MONDO_NENTRIES) != HV_EOK)
-			panic("Initializing mondo queue failed on CPU %" PRIu64 ".\n",
-			    CPU->arch.id);
+	    CPU_QCONF,
+	    CPU_MONDO_QUEUE_ID,
+	    KA2PA(cpu_mondo_queues[CPU->id]),
+	    CPU_MONDO_NENTRIES) != HV_EOK)
+		panic("Initializing mondo queue failed on CPU %" PRIu64 ".\n",
+		    CPU->arch.id);
 }