Index: kernel/arch/sparc64/src/mm/tlb.c
===================================================================
--- kernel/arch/sparc64/src/mm/tlb.c	(revision ccb0cbc16c5693f21db6f0a461d981ada016aad6)
+++ kernel/arch/sparc64/src/mm/tlb.c	(revision 22f851e0167add5c092c4f0972647405189b12cf)
@@ -112,5 +112,7 @@
 	data.l = locked;
 	data.cp = cacheable;
+#ifdef CONFIG_VIRT_IDX_CACHE
 	data.cv = cacheable;
+#endif /* CONFIG_VIRT_IDX_CACHE */
 	data.p = true;
 	data.w = true;
@@ -147,5 +149,7 @@
 	data.l = false;
 	data.cp = t->c;
+#ifdef CONFIG_VIRT_IDX_CACHE
 	data.cv = t->c;
+#endif /* CONFIG_VIRT_IDX_CACHE */
 	data.p = t->k;		/* p like privileged */
 	data.w = ro ? false : t->w;
@@ -181,5 +185,7 @@
 	data.l = false;
 	data.cp = t->c;
+#ifdef CONFIG_VIRT_IDX_CACHE
 	data.cv = t->c;
+#endif /* CONFIG_VIRT_IDX_CACHE */
 	data.p = t->k;		/* p like privileged */
 	data.w = false;
Index: kernel/arch/sparc64/src/mm/tsb.c
===================================================================
--- kernel/arch/sparc64/src/mm/tsb.c	(revision ccb0cbc16c5693f21db6f0a461d981ada016aad6)
+++ kernel/arch/sparc64/src/mm/tsb.c	(revision 22f851e0167add5c092c4f0972647405189b12cf)
@@ -101,5 +101,7 @@
 	tsb->data.pfn = t->frame >> PAGE_WIDTH;
 	tsb->data.cp = t->c;
+#ifdef CONFIG_VIRT_IDX_CACHE
 	tsb->data.cv = t->c;
+#endif /* CONFIG_VIRT_IDX_CACHE */
 	tsb->data.p = t->k;		/* p as privileged */
 	tsb->data.v = t->p;
@@ -141,5 +143,7 @@
 	tsb->data.pfn = t->frame >> PAGE_WIDTH;
 	tsb->data.cp = t->c;
+#ifdef CONFIG_VIRT_IDX_CACHE
 	tsb->data.cv = t->c;
+#endif /* CONFIG_VIRT_IDX_CACHE */
 	tsb->data.p = t->k;		/* p as privileged */
 	tsb->data.w = ro ? false : t->w;
Index: kernel/arch/sparc64/src/start.S
===================================================================
--- kernel/arch/sparc64/src/start.S	(revision ccb0cbc16c5693f21db6f0a461d981ada016aad6)
+++ kernel/arch/sparc64/src/start.S	(revision 22f851e0167add5c092c4f0972647405189b12cf)
@@ -123,6 +123,12 @@
 	membar #Sync
 
+#ifdef CONFIG_VIRT_IDX_CACHE
+#define TTE_LOW_DATA(imm) 	(TTE_CP | TTE_CV | TTE_P | LMA | (imm))
+#else /* CONFIG_VIRT_IDX_CACHE */
+#define TTE_LOW_DATA(imm) 	(TTE_CP | TTE_P | LMA | (imm))
+#endif /* CONFIG_VIRT_IDX_CACHE */
+
 #define SET_TLB_DATA(r1, r2, imm) \
-	set TTE_CV | TTE_CP | TTE_P | LMA | imm, %r1; \
+	set TTE_LOW_DATA(imm), %r1; \
 	or %r1, %l5, %r1; \
 	mov PAGESIZE_4M, %r2; \
@@ -349,3 +355,7 @@
 .global kernel_8k_tlb_data_template
 kernel_8k_tlb_data_template:
-	.quad ((1 << TTE_V_SHIFT) | TTE_CV | TTE_CP | TTE_P | TTE_W)
+#ifdef CONFIG_VIRT_IDX_CACHE
+	.quad ((1 << TTE_V_SHIFT) | (PAGESIZE_8K << TTE_SIZE_SHIFT) | TTE_CP | TTE_CV | TTE_P | TTE_W)
+#else /* CONFIG_VIRT_IDX_CACHE */
+	.quad ((1 << TTE_V_SHIFT) | (PAGESIZE_8K << TTE_SIZE_SHIFT) | TTE_CP | TTE_P | TTE_W)
+#endif /* CONFIG_VIRT_IDX_CACHE */