Index: arch/amd64/include/asm.h
===================================================================
--- arch/amd64/include/asm.h	(revision 75eacab68dc113f30b4052b896fd86a2850ee834)
+++ arch/amd64/include/asm.h	(revision 22f776926d191e0d2eb1be9adfc28070c7ce11d4)
@@ -83,11 +83,13 @@
 }
 
-/** Set priority level low
+/** Enable interrupts.
  *
  * Enable interrupts and return previous
  * value of EFLAGS.
- */
-static inline pri_t cpu_priority_low(void) {
-	pri_t v;
+ *
+ * @return Old interrupt priority level.
+ */
+static inline ipl_t interrupts_enable(void) {
+	ipl_t v;
 	__asm__ volatile (
 		"pushfq\n"
@@ -99,11 +101,13 @@
 }
 
-/** Set priority level high
+/** Disable interrupts.
  *
  * Disable interrupts and return previous
  * value of EFLAGS.
- */
-static inline pri_t cpu_priority_high(void) {
-	pri_t v;
+ *
+ * @return Old interrupt priority level.
+ */
+static inline ipl_t interrupts_disable(void) {
+	ipl_t v;
 	__asm__ volatile (
 		"pushfq\n"
@@ -115,22 +119,26 @@
 }
 
-/** Restore priority level
+/** Restore interrupt priority level.
  *
  * Restore EFLAGS.
- */
-static inline void cpu_priority_restore(pri_t pri) {
+ *
+ * @param ipl Saved interrupt priority level.
+ */
+static inline void interrupts_restore(ipl_t ipl) {
 	__asm__ volatile (
 		"pushq %0\n"
 		"popfq\n"
-		: : "r" (pri)
-		);
-}
-
-/** Return raw priority level
+		: : "r" (ipl)
+		);
+}
+
+/** Return interrupt priority level.
  *
  * Return EFLAFS.
- */
-static inline pri_t cpu_priority_read(void) {
-	pri_t v;
+ *
+ * @return Current interrupt priority level.
+ */
+static inline ipl_t interrupts_read(void) {
+	ipl_t v;
 	__asm__ volatile (
 		"pushfq\n"
Index: arch/amd64/include/context.h
===================================================================
--- arch/amd64/include/context.h	(revision 75eacab68dc113f30b4052b896fd86a2850ee834)
+++ arch/amd64/include/context.h	(revision 22f776926d191e0d2eb1be9adfc28070c7ce11d4)
@@ -56,5 +56,5 @@
     __u64 r15;
 
-    pri_t pri;
+    ipl_t ipl;
 } __attribute__ ((packed));
 
Index: arch/amd64/include/types.h
===================================================================
--- arch/amd64/include/types.h	(revision 75eacab68dc113f30b4052b896fd86a2850ee834)
+++ arch/amd64/include/types.h	(revision 22f776926d191e0d2eb1be9adfc28070c7ce11d4)
@@ -41,6 +41,6 @@
 typedef __u64 __address;
 
-/* Flags of processor (return value of cpu_priority_high()) */
-typedef __u64 pri_t;
+/* Flags of processor (return value of interrupts_disable()) */
+typedef __u64 ipl_t;
 
 typedef __u64 __native;
Index: arch/amd64/src/interrupt.c
===================================================================
--- arch/amd64/src/interrupt.c	(revision 75eacab68dc113f30b4052b896fd86a2850ee834)
+++ arch/amd64/src/interrupt.c	(revision 22f776926d191e0d2eb1be9adfc28070c7ce11d4)
@@ -109,5 +109,5 @@
 /*
  * Called directly from the assembler code.
- * CPU is cpu_priority_high().
+ * CPU is interrupts_disable()'d.
  */
 void trap_dispatcher(__u8 n, __native stack[])
Index: arch/amd64/src/userspace.c
===================================================================
--- arch/amd64/src/userspace.c	(revision 75eacab68dc113f30b4052b896fd86a2850ee834)
+++ arch/amd64/src/userspace.c	(revision 22f776926d191e0d2eb1be9adfc28070c7ce11d4)
@@ -42,7 +42,7 @@
 void userspace(void)
 {
-	pri_t pri;
+	ipl_t ipl;
 	
-	pri = cpu_priority_high();
+	ipl = interrupts_disable();
 
 	__asm__ volatile (""
@@ -58,5 +58,5 @@
 			  "pushq %%rsi;"
 			  "iretq;"
-			  : : "i" (gdtselector(UDATA_DES) | PL_USER), "i" (USTACK_ADDRESS+THREAD_STACK_SIZE), "r" (pri), "i" (gdtselector(UTEXT_DES) | PL_USER), "i" (UTEXT_ADDRESS));
+			  : : "i" (gdtselector(UDATA_DES) | PL_USER), "i" (USTACK_ADDRESS+THREAD_STACK_SIZE), "r" (ipl), "i" (gdtselector(UTEXT_DES) | PL_USER), "i" (UTEXT_ADDRESS));
 	
 	/* Unreachable */
Index: arch/ia32/include/asm.h
===================================================================
--- arch/ia32/include/asm.h	(revision 75eacab68dc113f30b4052b896fd86a2850ee834)
+++ arch/ia32/include/asm.h	(revision 22f776926d191e0d2eb1be9adfc28070c7ce11d4)
@@ -132,11 +132,13 @@
 static inline __u32 inl(__u16 port) { __u32 val; __asm__ volatile ("inl %w1, %l0 \n" : "=a" (val) : "d" (port) ); return val; }
 
-/** Set priority level low
+/** Enable interrupts.
  *
  * Enable interrupts and return previous
  * value of EFLAGS.
- */
-static inline pri_t cpu_priority_low(void) {
-	pri_t v;
+ *
+ * @return Old interrupt priority level.
+ */
+static inline ipl_t interrupts_enable(void) {
+	ipl_t v;
 	__asm__ volatile (
 		"pushf\n\t"
@@ -148,11 +150,13 @@
 }
 
-/** Set priority level high
+/** Disable interrupts.
  *
  * Disable interrupts and return previous
  * value of EFLAGS.
- */
-static inline pri_t cpu_priority_high(void) {
-	pri_t v;
+ *
+ * @return Old interrupt priority level.
+ */
+static inline ipl_t interrupts_disable(void) {
+	ipl_t v;
 	__asm__ volatile (
 		"pushf\n\t"
@@ -164,22 +168,24 @@
 }
 
-/** Restore priority level
+/** Restore interrupt priority level.
  *
  * Restore EFLAGS.
- */
-static inline void cpu_priority_restore(pri_t pri) {
+ *
+ * @param ipl Saved interrupt priority level.
+ */
+static inline void interrupts_restore(ipl_t ipl) {
 	__asm__ volatile (
 		"pushl %0\n\t"
 		"popf\n"
-		: : "r" (pri)
-	);
-}
-
-/** Return raw priority level
- *
- * Return EFLAFS.
- */
-static inline pri_t cpu_priority_read(void) {
-	pri_t v;
+		: : "r" (ipl)
+	);
+}
+
+/** Return interrupt priority level.
+ *
+ * @return EFLAFS.
+ */
+static inline ipl_t interrupts_read(void) {
+	ipl_t v;
 	__asm__ volatile (
 		"pushf\n\t"
Index: arch/ia32/include/context.h
===================================================================
--- arch/ia32/include/context.h	(revision 75eacab68dc113f30b4052b896fd86a2850ee834)
+++ arch/ia32/include/context.h	(revision 22f776926d191e0d2eb1be9adfc28070c7ce11d4)
@@ -53,5 +53,5 @@
 	__u32 edi;
 	__u32 ebp;
-	__u32 pri;
+	ipl_t ipl;
 } __attribute__ ((packed));
 
Index: arch/ia32/include/types.h
===================================================================
--- arch/ia32/include/types.h	(revision 75eacab68dc113f30b4052b896fd86a2850ee834)
+++ arch/ia32/include/types.h	(revision 22f776926d191e0d2eb1be9adfc28070c7ce11d4)
@@ -41,5 +41,5 @@
 typedef __u32 __address;
 
-typedef __u32 pri_t;
+typedef __u32 ipl_t;
 
 typedef __u32 __native;
Index: arch/ia32/src/drivers/ega.c
===================================================================
--- arch/ia32/src/drivers/ega.c	(revision 75eacab68dc113f30b4052b896fd86a2850ee834)
+++ arch/ia32/src/drivers/ega.c	(revision 22f776926d191e0d2eb1be9adfc28070c7ce11d4)
@@ -81,7 +81,7 @@
 void ega_putchar(const char ch)
 {
-	pri_t pri;
+	ipl_t ipl;
 
-	pri = cpu_priority_high();
+	ipl = interrupts_disable();
 	spinlock_lock(&egalock);
 
@@ -102,5 +102,5 @@
 
 	spinlock_unlock(&egalock);
-	cpu_priority_restore(pri);
+	interrupts_restore(ipl);
 }
 
Index: arch/ia32/src/interrupt.c
===================================================================
--- arch/ia32/src/interrupt.c	(revision 75eacab68dc113f30b4052b896fd86a2850ee834)
+++ arch/ia32/src/interrupt.c	(revision 22f776926d191e0d2eb1be9adfc28070c7ce11d4)
@@ -80,5 +80,5 @@
 /*
  * Called directly from the assembler code.
- * CPU is cpu_priority_high().
+ * CPU is interrupts_disable()'d.
  */
 void trap_dispatcher(__u8 n, __native stack[])
Index: arch/ia32/src/userspace.c
===================================================================
--- arch/ia32/src/userspace.c	(revision 75eacab68dc113f30b4052b896fd86a2850ee834)
+++ arch/ia32/src/userspace.c	(revision 22f776926d191e0d2eb1be9adfc28070c7ce11d4)
@@ -42,7 +42,7 @@
 void userspace(void)
 {
-	pri_t pri;
+	ipl_t ipl;
 	
-	pri = cpu_priority_high();
+	ipl = interrupts_disable();
 
 	__asm__ volatile (
@@ -61,5 +61,5 @@
 		"iret"
 		: 
-		: "i" (selector(UDATA_DES) | PL_USER), "r" (USTACK_ADDRESS+(THREAD_STACK_SIZE)), "r" (pri), "i" (selector(UTEXT_DES) | PL_USER), "i" (UTEXT_ADDRESS)
+		: "i" (selector(UDATA_DES) | PL_USER), "r" (USTACK_ADDRESS+(THREAD_STACK_SIZE)), "r" (ipl), "i" (selector(UTEXT_DES) | PL_USER), "i" (UTEXT_ADDRESS)
 		: "eax");
 	
Index: arch/ia64/include/context.h
===================================================================
--- arch/ia64/include/context.h	(revision 75eacab68dc113f30b4052b896fd86a2850ee834)
+++ arch/ia64/include/context.h	(revision 22f776926d191e0d2eb1be9adfc28070c7ce11d4)
@@ -96,5 +96,5 @@
 	__u64 pr;
 	
-	pri_t pri;
+	ipl_t ipl;
 } __attribute__ ((packed));
 
Index: arch/ia64/include/types.h
===================================================================
--- arch/ia64/include/types.h	(revision 75eacab68dc113f30b4052b896fd86a2850ee834)
+++ arch/ia64/include/types.h	(revision 22f776926d191e0d2eb1be9adfc28070c7ce11d4)
@@ -41,5 +41,5 @@
 typedef __u64 __address;
 
-typedef __u64 pri_t;
+typedef __u64 ipl_t;
 
 typedef __u64 __native;
Index: arch/ia64/src/context.S
===================================================================
--- arch/ia64/src/context.S	(revision 75eacab68dc113f30b4052b896fd86a2850ee834)
+++ arch/ia64/src/context.S	(revision 22f776926d191e0d2eb1be9adfc28070c7ce11d4)
@@ -135,4 +135,5 @@
 	 */
 
+	/* TODO: ensure RSE lazy mode */
 	mov ar.bspstore = loc4
 	mov ar.rnat = loc5
Index: arch/ia64/src/dummy.s
===================================================================
--- arch/ia64/src/dummy.s	(revision 75eacab68dc113f30b4052b896fd86a2850ee834)
+++ arch/ia64/src/dummy.s	(revision 22f776926d191e0d2eb1be9adfc28070c7ce11d4)
@@ -36,8 +36,8 @@
 .global cpu_identify
 .global cpu_print_report
-.global cpu_priority_high
-.global cpu_priority_low
-.global cpu_priority_read
-.global cpu_priority_restore
+.global interrupts_disable
+.global interrupts_enable
+.global interrupts_read
+.global interrupts_restore
 .global cpu_sleep
 .global dummy
@@ -53,8 +53,8 @@
 cpu_identify:
 cpu_print_report:
-cpu_priority_high:
-cpu_priority_low:
-cpu_priority_read:
-cpu_priority_restore:
+interrupts_disable:
+interrupts_enable:
+interrupts_read:
+interrupts_restore:
 cpu_sleep:
 fpu_init:
Index: arch/mips32/include/context.h
===================================================================
--- arch/mips32/include/context.h	(revision 75eacab68dc113f30b4052b896fd86a2850ee834)
+++ arch/mips32/include/context.h	(revision 22f776926d191e0d2eb1be9adfc28070c7ce11d4)
@@ -63,5 +63,5 @@
 	__u32 gp;
 
-	__u32 pri;
+	ipl_t ipl;
 };
 
Index: arch/mips32/include/types.h
===================================================================
--- arch/mips32/include/types.h	(revision 75eacab68dc113f30b4052b896fd86a2850ee834)
+++ arch/mips32/include/types.h	(revision 22f776926d191e0d2eb1be9adfc28070c7ce11d4)
@@ -46,5 +46,5 @@
 typedef __u32 __address;
 
-typedef __u32 pri_t;
+typedef __u32 ipl_t;
 
 typedef __u32 __native;
Index: arch/mips32/src/drivers/arc.c
===================================================================
--- arch/mips32/src/drivers/arc.c	(revision 75eacab68dc113f30b4052b896fd86a2850ee834)
+++ arch/mips32/src/drivers/arc.c	(revision 22f776926d191e0d2eb1be9adfc28070c7ce11d4)
@@ -176,10 +176,10 @@
 {
 	__u32 cnt;
-	pri_t pri;
+	ipl_t ipl;
 
 	/* TODO: Should be spinlock? */
-	pri = cpu_priority_high();
+	ipl = interrupts_disable();
 	arc_entry->write(1, &ch, 1, &cnt);
-	cpu_priority_restore(pri);
+	interrupts_restore(ipl);
 	
 }
Index: arch/mips32/src/exception.c
===================================================================
--- arch/mips32/src/exception.c	(revision 75eacab68dc113f30b4052b896fd86a2850ee834)
+++ arch/mips32/src/exception.c	(revision 22f776926d191e0d2eb1be9adfc28070c7ce11d4)
@@ -47,9 +47,9 @@
 	 * NOTE ON OPERATION ORDERING
 	 *
-	 * On entry, cpu_priority_high() must be called before 
+	 * On entry, interrupts_disable() must be called before 
 	 * exception bit is cleared.
 	 */
 
-	cpu_priority_high();
+	interrupts_disable();
 	cp0_status_write(cp0_status_read() & ~ (cp0_status_exl_exception_bit |
 						cp0_status_um_bit));
Index: arch/mips32/src/interrupt.c
===================================================================
--- arch/mips32/src/interrupt.c	(revision 75eacab68dc113f30b4052b896fd86a2850ee834)
+++ arch/mips32/src/interrupt.c	(revision 22f776926d191e0d2eb1be9adfc28070c7ce11d4)
@@ -53,24 +53,40 @@
 }
 
-pri_t cpu_priority_high(void)
+/** Disable interrupts.
+ *
+ * @return Old interrupt priority level.
+ */
+ipl_t interrupts_disable(void)
 {
-	pri_t pri = (pri_t) cp0_status_read();
-	cp0_status_write(pri & ~cp0_status_ie_enabled_bit);
-	return pri;
+	ipl_t ipl = (ipl_t) cp0_status_read();
+	cp0_status_write(ipl & ~cp0_status_ie_enabled_bit);
+	return ipl;
 }
 
-pri_t cpu_priority_low(void)
+/** Enable interrupts.
+ *
+ * @return Old interrupt priority level.
+ */
+ipl_t interrupts_enable(void)
 {
-	pri_t pri = (pri_t) cp0_status_read();
-	cp0_status_write(pri | cp0_status_ie_enabled_bit);
-	return pri;
+	ipl_t ipl = (ipl_t) cp0_status_read();
+	cp0_status_write(ipl | cp0_status_ie_enabled_bit);
+	return ipl;
 }
 
-void cpu_priority_restore(pri_t pri)
+/** Restore interrupt priority level.
+ *
+ * @param ipl Saved interrupt priority level.
+ */
+void interrupts_restore(ipl_t ipl)
 {
-	cp0_status_write(cp0_status_read() | (pri & cp0_status_ie_enabled_bit));
+	cp0_status_write(cp0_status_read() | (ipl & cp0_status_ie_enabled_bit));
 }
 
-pri_t cpu_priority_read(void)
+/** Read interrupt priority level.
+ *
+ * @return Current interrupt priority level.
+ */
+ipl_t interrupts_read(void)
 {
 	return cp0_status_read();
Index: arch/mips32/src/mips32.c
===================================================================
--- arch/mips32/src/mips32.c	(revision 75eacab68dc113f30b4052b896fd86a2850ee834)
+++ arch/mips32/src/mips32.c	(revision 22f776926d191e0d2eb1be9adfc28070c7ce11d4)
@@ -53,5 +53,5 @@
 {
 	/* It is not assumed by default */
-	cpu_priority_high();
+	interrupts_disable();
 
 	init_arc();
Index: arch/mips32/src/mm/asid.c
===================================================================
--- arch/mips32/src/mm/asid.c	(revision 75eacab68dc113f30b4052b896fd86a2850ee834)
+++ arch/mips32/src/mm/asid.c	(revision 22f776926d191e0d2eb1be9adfc28070c7ce11d4)
@@ -45,5 +45,5 @@
 asid_t asid_get(void)
 {
-	pri_t pri;
+	ipl_t ipl;
 	int i, j;
 	count_t min;
@@ -51,5 +51,5 @@
 	min = (unsigned) -1;
 	
-	pri = cpu_priority_high();
+	ipl = interrupts_disable();
 	spinlock_lock(&asid_usage_lock);
 	
@@ -66,5 +66,5 @@
 
 	spinlock_unlock(&asid_usage_lock);
-	cpu_priority_restore(pri);
+	interrupts_restore(ipl);
 
 	return i;
@@ -79,7 +79,7 @@
 void asid_put(asid_t asid)
 {
-	pri_t pri;
+	ipl_t ipl;
 
-	pri = cpu_priority_high();
+	ipl = interrupts_disable();
 	spinlock_lock(&asid_usage_lock);
 
@@ -90,5 +90,5 @@
 
 	spinlock_unlock(&asid_usage_lock);
-	cpu_priority_restore(pri);
+	interrupts_restore(ipl);
 }
 
@@ -104,9 +104,9 @@
 {
 	bool has_conflicts = false;
-	pri_t pri;
+	ipl_t ipl;
 
 	ASSERT(asid != ASID_INVALID);
 
-	pri = cpu_priority_high();
+	ipl = interrupts_disable();
 	spinlock_lock(&asid_usage_lock);
 
@@ -115,5 +115,5 @@
 
 	spinlock_unlock(&asid_usage_lock);
-	cpu_priority_restore(pri);
+	interrupts_restore(ipl);
 
 	return has_conflicts;
Index: arch/mips32/src/mm/tlb.c
===================================================================
--- arch/mips32/src/mm/tlb.c	(revision 75eacab68dc113f30b4052b896fd86a2850ee834)
+++ arch/mips32/src/mm/tlb.c	(revision 22f776926d191e0d2eb1be9adfc28070c7ce11d4)
@@ -316,10 +316,10 @@
 {
 	entry_hi_t hi;
-	pri_t pri;
+	ipl_t ipl;
 	int i;	
 	
 	ASSERT(asid != ASID_INVALID);
 
-	pri = cpu_priority_high();
+	ipl = interrupts_disable();
 	
 	for (i = 0; i < TLB_SIZE; i++) {
@@ -337,5 +337,5 @@
 	}
 	
-	cpu_priority_restore(pri);
+	interrupts_restore(ipl);
 }
 
Index: arch/mips32/src/mm/vm.c
===================================================================
--- arch/mips32/src/mm/vm.c	(revision 75eacab68dc113f30b4052b896fd86a2850ee834)
+++ arch/mips32/src/mm/vm.c	(revision 22f776926d191e0d2eb1be9adfc28070c7ce11d4)
@@ -42,13 +42,13 @@
 {
 	entry_hi_t hi;
-	pri_t pri;
+	ipl_t ipl;
 	
 	hi.value = cp0_entry_hi_read();
 
-	pri = cpu_priority_high();
+	ipl = interrupts_disable();
 	spinlock_lock(&vm->lock);
 	hi.asid = vm->asid;
 	cp0_entry_hi_write(hi.value);	
 	spinlock_lock(&vm->unlock);
-	cpu_priority_restore(pri);
+	interrupts_restore(ipl);
 }
Index: arch/ppc32/include/asm.h
===================================================================
--- arch/ppc32/include/asm.h	(revision 75eacab68dc113f30b4052b896fd86a2850ee834)
+++ arch/ppc32/include/asm.h	(revision 22f776926d191e0d2eb1be9adfc28070c7ce11d4)
@@ -33,12 +33,14 @@
 #include <config.h>
 
-/** Set priority level low
+/** Enable interrupts.
  *
  * Enable interrupts and return previous
  * value of EE.
+ *
+ * @return Old interrupt priority level.
  */
-static inline pri_t cpu_priority_low(void) {
-	pri_t v;
-	pri_t tmp;
+static inline ipl_t interrupts_enable(void) {
+	ipl_t v;
+	ipl_t tmp;
 	
 	__asm__ volatile (
@@ -52,12 +54,14 @@
 }
 
-/** Set priority level high
+/** Disable interrupts.
  *
  * Disable interrupts and return previous
  * value of EE.
+ *
+ * @return Old interrupt priority level.
  */
-static inline pri_t cpu_priority_high(void) {
-	pri_t v;
-	pri_t tmp;
+static inline ipl_t interrupts_disable(void) {
+	ipl_t v;
+	ipl_t tmp;
 	
 	__asm__ volatile (
@@ -71,10 +75,12 @@
 }
 
-/** Restore priority level
+/** Restore interrupt priority level.
  *
  * Restore EE.
+ *
+ * @param ipl Saved interrupt priority level.
  */
-static inline void cpu_priority_restore(pri_t pri) {
-	pri_t tmp;
+static inline void interrupts_restore(ipl_t ipl) {
+	ipl_t tmp;
 	
 	__asm__ volatile (
@@ -85,15 +91,17 @@
 		"mtmsr %0\n"
 		"0:\n"
-		: "=r" (pri), "=r" (tmp)
-		: "0" (pri)
+		: "=r" (ipl), "=r" (tmp)
+		: "0" (ipl)
 	);
 }
 
-/** Return raw priority level
+/** Return interrupt priority level.
  *
  * Return EE.
+ *
+ * @return Current interrupt priority level.
  */
-static inline pri_t cpu_priority_read(void) {
-	pri_t v;
+static inline ipl_t interrupts_read(void) {
+	ipl_t v;
 	__asm__ volatile (
 		"mfmsr %0\n"
Index: arch/ppc32/include/context.h
===================================================================
--- arch/ppc32/include/context.h	(revision 75eacab68dc113f30b4052b896fd86a2850ee834)
+++ arch/ppc32/include/context.h	(revision 22f776926d191e0d2eb1be9adfc28070c7ce11d4)
@@ -68,5 +68,5 @@
 	__u32 r31;
 	__u32 pc;
-	pri_t pri;
+	ipl_t ipl;
 } __attribute__ ((packed));
 
Index: arch/ppc32/include/types.h
===================================================================
--- arch/ppc32/include/types.h	(revision 75eacab68dc113f30b4052b896fd86a2850ee834)
+++ arch/ppc32/include/types.h	(revision 22f776926d191e0d2eb1be9adfc28070c7ce11d4)
@@ -41,5 +41,5 @@
 typedef __u32 __address;
 
-typedef __u32 pri_t;
+typedef __u32 ipl_t;
 
 typedef __u32 __native;
Index: include/arch.h
===================================================================
--- include/arch.h	(revision 75eacab68dc113f30b4052b896fd86a2850ee834)
+++ include/arch.h	(revision 22f776926d191e0d2eb1be9adfc28070c7ce11d4)
@@ -47,5 +47,5 @@
 #endif /* early_mapping */
 
-/*
+/**
  * For each possible kernel stack, structure
  * of the following type will be placed at
@@ -53,9 +53,9 @@
  */
 struct the {
-	int preemption_disabled;
-	thread_t *thread;		/* current thread */
-	task_t *task;			/* current task */
-	cpu_t *cpu;			/* executing cpu */
-	vm_t *vm;			/* current vm */
+	int preemption_disabled;	/**< Preemption disabled counter. */
+	thread_t *thread;		/**< Current thread. */
+	task_t *task;			/**< Current task. */
+	cpu_t *cpu;			/**< Executing cpu. */
+	vm_t *vm;			/**< Current vm. */
 };
 
@@ -70,8 +70,8 @@
 extern void calibrate_delay_loop(void);
 
-extern pri_t cpu_priority_high(void);
-extern pri_t cpu_priority_low(void);
-extern void cpu_priority_restore(pri_t pri);
-extern pri_t cpu_priority_read(void);
+extern ipl_t interrupts_disable(void); 
+extern ipl_t interrupts_enable(void);
+extern void interrupts_restore(ipl_t ipl);
+extern ipl_t interrupts_read(void);
 
 #endif
Index: include/proc/thread.h
===================================================================
--- include/proc/thread.h	(revision 75eacab68dc113f30b4052b896fd86a2850ee834)
+++ include/proc/thread.h	(revision 22f776926d191e0d2eb1be9adfc28070c7ce11d4)
@@ -101,5 +101,5 @@
 	__u64 ticks;				/**< Ticks before preemption. */
 
-	int pri;				/**< Thread's priority. Implemented as index of run queue. */
+	int priority;				/**< Thread's priority. Implemented as index to CPU->rq */
 	__u32 tid;				/**< Thread ID. */
 	
Index: src/debug/print.c
===================================================================
--- src/debug/print.c	(revision 75eacab68dc113f30b4052b896fd86a2850ee834)
+++ src/debug/print.c	(revision 22f776926d191e0d2eb1be9adfc28070c7ce11d4)
@@ -286,5 +286,5 @@
 	va_start(ap, fmt);
 
-	irqpri = cpu_priority_high();
+	irqpri = interrupts_disable();
 	spinlock_lock(&printflock);
 
@@ -401,5 +401,5 @@
 out:
 	spinlock_unlock(&printflock);
-	cpu_priority_restore(irqpri);
+	interrupts_restore(irqpri);
 	
 	va_end(ap);
Index: src/lib/func.c
===================================================================
--- src/lib/func.c	(revision 75eacab68dc113f30b4052b896fd86a2850ee834)
+++ src/lib/func.c	(revision 22f776926d191e0d2eb1be9adfc28070c7ce11d4)
@@ -44,5 +44,5 @@
 {
 	haltstate = 1;
-	cpu_priority_high();
+	interrupts_disable();
 	if (CPU)
 		printf("cpu%d: halted\n", CPU->id);
Index: src/main/kinit.c
===================================================================
--- src/main/kinit.c	(revision 75eacab68dc113f30b4052b896fd86a2850ee834)
+++ src/main/kinit.c	(revision 22f776926d191e0d2eb1be9adfc28070c7ce11d4)
@@ -65,5 +65,5 @@
 	int i;
 
-	cpu_priority_high();
+	interrupts_disable();
 
 #ifdef __SMP__		 	
@@ -116,5 +116,5 @@
 #endif /* __SMP__ */
 
-	cpu_priority_low();
+	interrupts_enable();
 
 #ifdef __USERSPACE__
Index: src/main/main.c
===================================================================
--- src/main/main.c	(revision 75eacab68dc113f30b4052b896fd86a2850ee834)
+++ src/main/main.c	(revision 22f776926d191e0d2eb1be9adfc28070c7ce11d4)
@@ -110,5 +110,5 @@
  * Initializes the kernel by bootstrap CPU.
  *
- * Assuming cpu_priority_high().
+ * Assuming interrupts_disable().
  *
  */
@@ -209,5 +209,5 @@
  * is at ctx.sp which was set during BP boot.
  *
- * Assuming  cpu_priority_high().
+ * Assuming interrupts_disable()'d.
  *
  */
Index: src/mm/frame.c
===================================================================
--- src/mm/frame.c	(revision 75eacab68dc113f30b4052b896fd86a2850ee834)
+++ src/mm/frame.c	(revision 22f776926d191e0d2eb1be9adfc28070c7ce11d4)
@@ -69,5 +69,5 @@
 __address frame_alloc(int flags)
 {
-	pri_t pri;
+	ipl_t ipl;
 	link_t *cur, *tmp;
 	zone_t *z;
@@ -77,5 +77,5 @@
 	
 loop:
-	pri = cpu_priority_high();
+	ipl = interrupts_disable();
 	spinlock_lock(&zone_head_lock);
 	
@@ -105,5 +105,5 @@
 		 */
 		spinlock_unlock(&zone_head_lock);
-		cpu_priority_restore(pri);
+		interrupts_restore(ipl);
 
 		panic("Sleep not implemented.\n");
@@ -127,5 +127,5 @@
 	
 	spinlock_unlock(&zone_head_lock);
-	cpu_priority_restore(pri);
+	interrupts_restore(ipl);
 	
 	return v;
@@ -142,5 +142,5 @@
 void frame_free(__address addr)
 {
-	pri_t pri;
+	ipl_t ipl;
 	link_t *cur;
 	zone_t *z;
@@ -150,5 +150,5 @@
 	ASSERT(addr % FRAME_SIZE == 0);
 	
-	pri = cpu_priority_high();
+	ipl = interrupts_disable();
 	spinlock_lock(&zone_head_lock);
 	
@@ -188,5 +188,5 @@
 	
 	spinlock_unlock(&zone_head_lock);
-	cpu_priority_restore(pri);
+	interrupts_restore(ipl);
 }
 
@@ -200,5 +200,5 @@
 void frame_not_free(__address addr)
 {
-	pri_t pri;
+	ipl_t ipl;
 	link_t *cur;
 	zone_t *z;
@@ -208,5 +208,5 @@
 	ASSERT(addr % FRAME_SIZE == 0);
 	
-	pri = cpu_priority_high();
+	ipl = interrupts_disable();
 	spinlock_lock(&zone_head_lock);
 	
@@ -247,5 +247,5 @@
 	
 	spinlock_unlock(&zone_head_lock);
-	cpu_priority_restore(pri);
+	interrupts_restore(ipl);
 }
 
@@ -336,7 +336,7 @@
 void zone_attach(zone_t *zone)
 {
-	pri_t pri;
-	
-	pri = cpu_priority_high();
+	ipl_t ipl;
+	
+	ipl = interrupts_disable();
 	spinlock_lock(&zone_head_lock);
 	
@@ -344,5 +344,5 @@
 	
 	spinlock_unlock(&zone_head_lock);
-	cpu_priority_restore(pri);
+	interrupts_restore(ipl);
 }
 
Index: src/mm/heap.c
===================================================================
--- src/mm/heap.c	(revision 75eacab68dc113f30b4052b896fd86a2850ee834)
+++ src/mm/heap.c	(revision 22f776926d191e0d2eb1be9adfc28070c7ce11d4)
@@ -61,5 +61,5 @@
 void *early_malloc(size_t size)
 {
-	pri_t pri;
+	ipl_t ipl;
 	chunk_t *x, *y, *z;
 
@@ -68,5 +68,5 @@
 		
 	x = chunk0;
-	pri = cpu_priority_high();
+	ipl = interrupts_disable();
 	spinlock_lock(&heaplock);		
 	while (x) {
@@ -85,5 +85,5 @@
 		if (x->size < size + sizeof(chunk_t) + 1) {
 			spinlock_unlock(&heaplock);
-			cpu_priority_restore(pri);
+			interrupts_restore(ipl);
 			return &x->data[0];
 		}
@@ -106,10 +106,10 @@
 		x->next = y;
 		spinlock_unlock(&heaplock);
-		cpu_priority_restore(pri);
+		interrupts_restore(ipl);
 
 		return &x->data[0];
 	}
 	spinlock_unlock(&heaplock);
-	cpu_priority_restore(pri);
+	interrupts_restore(ipl);
 	return NULL;
 }
@@ -117,5 +117,5 @@
 void early_free(void *ptr)
 {
-	pri_t pri;
+	ipl_t ipl;
 	chunk_t *x, *y, *z;
 
@@ -128,5 +128,5 @@
 		panic("freeing unused/damaged chunk");
 
-	pri = cpu_priority_high();
+	ipl = interrupts_disable();
 	spinlock_lock(&heaplock);
 	x = y->prev;
@@ -151,4 +151,4 @@
 	y->used = 0;
 	spinlock_unlock(&heaplock);
-	cpu_priority_restore(pri);
+	interrupts_restore(ipl);
 }
Index: src/mm/vm.c
===================================================================
--- src/mm/vm.c	(revision 75eacab68dc113f30b4052b896fd86a2850ee834)
+++ src/mm/vm.c	(revision 22f776926d191e0d2eb1be9adfc28070c7ce11d4)
@@ -90,5 +90,5 @@
 vm_area_t *vm_area_create(vm_t *m, vm_type_t type, size_t size, __address addr)
 {
-	pri_t pri;
+	ipl_t ipl;
 	vm_area_t *a;
 	
@@ -96,5 +96,5 @@
 		panic("addr not aligned to a page boundary");
 	
-	pri = cpu_priority_high();
+	ipl = interrupts_disable();
 	spinlock_lock(&m->lock);
 	
@@ -111,5 +111,5 @@
 			free(a);
 			spinlock_unlock(&m->lock);
-			cpu_priority_restore(pri);
+			interrupts_restore(ipl);
 			return NULL;
 		}
@@ -130,5 +130,5 @@
 
 	spinlock_unlock(&m->lock);
-	cpu_priority_restore(pri);
+	interrupts_restore(ipl);
 	
 	return a;
@@ -142,7 +142,7 @@
 {
 	int i, flags;
-	pri_t pri;
-	
-	pri = cpu_priority_high();
+	ipl_t ipl;
+	
+	ipl = interrupts_disable();
 	spinlock_lock(&m->lock);
 	spinlock_lock(&a->lock);
@@ -166,5 +166,5 @@
 	spinlock_unlock(&a->lock);
 	spinlock_unlock(&m->lock);
-	cpu_priority_restore(pri);
+	interrupts_restore(ipl);
 }
 
@@ -172,7 +172,7 @@
 {
 	int i;
-	pri_t pri;
-	
-	pri = cpu_priority_high();
+	ipl_t ipl;
+	
+	ipl = interrupts_disable();
 	spinlock_lock(&m->lock);
 	spinlock_lock(&a->lock);
@@ -184,5 +184,5 @@
 	spinlock_unlock(&a->lock);
 	spinlock_unlock(&m->lock);
-	cpu_priority_restore(pri);
+	interrupts_restore(ipl);
 }
 
@@ -190,7 +190,7 @@
 {
 	link_t *l;
-	pri_t pri;
-	
-	pri = cpu_priority_high();
+	ipl_t ipl;
+	
+	ipl = interrupts_disable();
 
 	tlb_shootdown_start();
@@ -203,5 +203,5 @@
 	tlb_shootdown_finalize();
 
-	cpu_priority_restore(pri);
+	interrupts_restore(ipl);
 
 	vm_install_arch(m);
Index: src/proc/scheduler.c
===================================================================
--- src/proc/scheduler.c	(revision 75eacab68dc113f30b4052b896fd86a2850ee834)
+++ src/proc/scheduler.c	(revision 22f776926d191e0d2eb1be9adfc28070c7ce11d4)
@@ -126,5 +126,5 @@
 
 loop:
-	cpu_priority_high();
+	interrupts_disable();
 
 	spinlock_lock(&CPU->lock);
@@ -132,5 +132,5 @@
 	spinlock_unlock(&CPU->lock);
 
-	cpu_priority_low();
+	interrupts_enable();
 	
 	if (n == 0) {
@@ -156,5 +156,5 @@
 	}
 
-	cpu_priority_high();
+	interrupts_disable();
 	
 	i = 0;
@@ -197,5 +197,5 @@
 
 		t->ticks = us2ticks((i+1)*10000);
-		t->pri = i;	/* eventually correct rq index */
+		t->priority = i;	/* eventually correct rq index */
 
 		/*
@@ -262,9 +262,9 @@
 void scheduler(void)
 {
-	volatile pri_t pri;
+	volatile ipl_t ipl;
 
 	ASSERT(CPU != NULL);
 
-	pri = cpu_priority_high();
+	ipl = interrupts_disable();
 
 	if (haltstate)
@@ -282,14 +282,14 @@
 			before_thread_runs();
 			spinlock_unlock(&THREAD->lock);
-			cpu_priority_restore(THREAD->saved_context.pri);
+			interrupts_restore(THREAD->saved_context.ipl);
 			return;
 		}
 
 		/*
-		 * CPU priority of preempted thread is recorded here
-		 * to facilitate scheduler() invocations from
-		 * cpu_priority_high()'ed code (e.g. waitq_sleep_timeout()). 
-		 */
-		THREAD->saved_context.pri = pri;
+		 * Interrupt priority level of preempted thread is recorded here
+		 * to facilitate scheduler() invocations from interrupts_disable()'d
+		 * code (e.g. waitq_sleep_timeout()). 
+		 */
+		THREAD->saved_context.ipl = ipl;
 	}
 
@@ -372,5 +372,5 @@
 			 * Prefer the thread after it's woken up.
 			 */
-			THREAD->pri = -1;
+			THREAD->priority = -1;
 
 			/*
@@ -407,5 +407,5 @@
 	
 	spinlock_lock(&THREAD->lock);
-	priority = THREAD->pri;
+	priority = THREAD->priority;
 	spinlock_unlock(&THREAD->lock);	
 
@@ -447,5 +447,5 @@
 
 	#ifdef SCHEDULER_VERBOSE
-	printf("cpu%d: tid %d (pri=%d,ticks=%d,nrdy=%d)\n", CPU->id, THREAD->tid, THREAD->pri, THREAD->ticks, CPU->nrdy);
+	printf("cpu%d: tid %d (priority=%d,ticks=%d,nrdy=%d)\n", CPU->id, THREAD->tid, THREAD->priority, THREAD->ticks, CPU->nrdy);
 	#endif	
 
@@ -473,5 +473,5 @@
 	thread_t *t;
 	int count, i, j, k = 0;
-	pri_t pri;
+	ipl_t ipl;
 
 loop:
@@ -487,10 +487,10 @@
 	 * passes. Each time get the most up to date counts.
 	 */
-	pri = cpu_priority_high();
+	ipl = interrupts_disable();
 	spinlock_lock(&CPU->lock);
 	count = nrdy / config.cpu_active;
 	count -= CPU->nrdy;
 	spinlock_unlock(&CPU->lock);
-	cpu_priority_restore(pri);
+	interrupts_restore(ipl);
 
 	if (count <= 0)
@@ -515,10 +515,10 @@
 				continue;				
 
-restart:		pri = cpu_priority_high();
+restart:		ipl = interrupts_disable();
 			r = &cpu->rq[j];
 			spinlock_lock(&r->lock);
 			if (r->n == 0) {
 				spinlock_unlock(&r->lock);
-				cpu_priority_restore(pri);
+				interrupts_restore(ipl);
 				continue;
 			}
@@ -549,5 +549,5 @@
 						/* Release all locks and try again. */ 
 						spinlock_unlock(&r->lock);
-						cpu_priority_restore(pri);
+						interrupts_restore(ipl);
 						goto restart;
 					}
@@ -581,5 +581,5 @@
 				thread_ready(t);
 
-				cpu_priority_restore(pri);
+				interrupts_restore(ipl);
 	
 				if (--count == 0)
@@ -593,5 +593,5 @@
 				continue;
 			}
-			cpu_priority_restore(pri);
+			interrupts_restore(ipl);
 		}
 	}
Index: src/proc/task.c
===================================================================
--- src/proc/task.c	(revision 75eacab68dc113f30b4052b896fd86a2850ee834)
+++ src/proc/task.c	(revision 22f776926d191e0d2eb1be9adfc28070c7ce11d4)
@@ -65,5 +65,5 @@
 task_t *task_create(vm_t *m)
 {
-	pri_t pri;
+	ipl_t ipl;
 	task_t *ta;
 	
@@ -75,9 +75,9 @@
 		ta->vm = m;
 		
-		pri = cpu_priority_high();
+		ipl = interrupts_disable();
 		spinlock_lock(&tasks_lock);
 		list_append(&ta->tasks_link, &tasks_head);
 		spinlock_unlock(&tasks_lock);
-		cpu_priority_restore(pri);
+		interrupts_restore(ipl);
 	}
 	return ta;
Index: src/proc/thread.c
===================================================================
--- src/proc/thread.c	(revision 75eacab68dc113f30b4052b896fd86a2850ee834)
+++ src/proc/thread.c	(revision 22f776926d191e0d2eb1be9adfc28070c7ce11d4)
@@ -68,5 +68,5 @@
  * function returns.
  *
- * cpu_priority_high() is assumed.
+ * interrupts_disable() is assumed.
  *
  */
@@ -80,5 +80,5 @@
 
 	spinlock_unlock(&THREAD->lock);
-	cpu_priority_low();
+	interrupts_enable();
 
 	f(arg);
@@ -113,12 +113,12 @@
 	cpu_t *cpu;
 	runq_t *r;
-	pri_t pri;
+	ipl_t ipl;
 	int i, avg, send_ipi = 0;
 
-	pri = cpu_priority_high();
+	ipl = interrupts_disable();
 
 	spinlock_lock(&t->lock);
 
-	i = (t->pri < RQ_COUNT -1) ? ++t->pri : t->pri;
+	i = (t->priority < RQ_COUNT -1) ? ++t->priority : t->priority;
 	
 	cpu = CPU;
@@ -149,5 +149,5 @@
 	spinlock_unlock(&cpu->lock);
 
-	cpu_priority_restore(pri);
+	interrupts_restore(ipl);
 }
 
@@ -172,5 +172,5 @@
 	t = (thread_t *) malloc(sizeof(thread_t));
 	if (t) {
-		pri_t pri;
+		ipl_t ipl;
 	
 		spinlock_initialize(&t->lock);
@@ -181,9 +181,9 @@
 		}
 
-		pri = cpu_priority_high();
+		ipl = interrupts_disable();
 		spinlock_lock(&tidlock);
 		t->tid = ++last_tid;
 		spinlock_unlock(&tidlock);
-		cpu_priority_restore(pri);
+		interrupts_restore(ipl);
 		
 		memsetb(frame_ks, THREAD_STACK_SIZE, 0);
@@ -200,12 +200,12 @@
 		the_initialize((the_t *) t->kstack);
 
-		pri = cpu_priority_high();
-		t->saved_context.pri = cpu_priority_read();
-		cpu_priority_restore(pri);
+		ipl = interrupts_disable();
+		t->saved_context.ipl = interrupts_read();
+		interrupts_restore(ipl);
 		
 		t->thread_code = func;
 		t->thread_arg = arg;
 		t->ticks = -1;
-		t->pri = -1;		/* start in rq[0] */
+		t->priority = -1;		/* start in rq[0] */
 		t->cpu = NULL;
 		t->flags = 0;
@@ -228,5 +228,5 @@
 		 * Register this thread in the system-wide list.
 		 */
-		pri = cpu_priority_high();		
+		ipl = interrupts_disable();		
 		spinlock_lock(&threads_lock);
 		list_append(&t->threads_link, &threads_head);
@@ -240,5 +240,5 @@
 		spinlock_unlock(&task->lock);
 
-		cpu_priority_restore(pri);
+		interrupts_restore(ipl);
 	}
 
@@ -255,12 +255,12 @@
 void thread_exit(void)
 {
-	pri_t pri;
+	ipl_t ipl;
 
 restart:
-	pri = cpu_priority_high();
+	ipl = interrupts_disable();
 	spinlock_lock(&THREAD->lock);
 	if (THREAD->timeout_pending) { /* busy waiting for timeouts in progress */
 		spinlock_unlock(&THREAD->lock);
-		cpu_priority_restore(pri);
+		interrupts_restore(ipl);
 		goto restart;
 	}
@@ -312,11 +312,11 @@
 void thread_register_call_me(void (* call_me)(void *), void *call_me_with)
 {
-	pri_t pri;
-	
-	pri = cpu_priority_high();
+	ipl_t ipl;
+	
+	ipl = interrupts_disable();
 	spinlock_lock(&THREAD->lock);
 	THREAD->call_me = call_me;
 	THREAD->call_me_with = call_me_with;
 	spinlock_unlock(&THREAD->lock);
-	cpu_priority_restore(pri);
-}
+	interrupts_restore(ipl);
+}
Index: src/synch/rwlock.c
===================================================================
--- src/synch/rwlock.c	(revision 75eacab68dc113f30b4052b896fd86a2850ee834)
+++ src/synch/rwlock.c	(revision 22f776926d191e0d2eb1be9adfc28070c7ce11d4)
@@ -97,12 +97,12 @@
 int _rwlock_write_lock_timeout(rwlock_t *rwl, __u32 usec, int trylock)
 {
-	pri_t pri;
+	ipl_t ipl;
 	int rc;
 	
-	pri = cpu_priority_high();
+	ipl = interrupts_disable();
 	spinlock_lock(&THREAD->lock);
 	THREAD->rwlock_holder_type = RWLOCK_WRITER;
 	spinlock_unlock(&THREAD->lock);	
-	cpu_priority_restore(pri);
+	interrupts_restore(ipl);
 
 	/*
@@ -119,5 +119,5 @@
 		 */
 		 
-		pri = cpu_priority_high();
+		ipl = interrupts_disable();
 		spinlock_lock(&rwl->lock);
 		/*
@@ -129,5 +129,5 @@
 			let_others_in(rwl, ALLOW_READERS_ONLY);
 		spinlock_unlock(&rwl->lock);
-		cpu_priority_restore(pri);
+		interrupts_restore(ipl);
 	}
 	
@@ -152,7 +152,7 @@
 {
 	int rc;
-	pri_t pri;
-	
-	pri = cpu_priority_high();
+	ipl_t ipl;
+	
+	ipl = interrupts_disable();
 	spinlock_lock(&THREAD->lock);
 	THREAD->rwlock_holder_type = RWLOCK_READER;
@@ -205,5 +205,5 @@
 				/*
 				 * The sleep timeouted.
-				 * We just restore the cpu priority.
+				 * We just restore interrupt priority level.
 				 */
 			case ESYNCH_OK_BLOCKED:		
@@ -216,5 +216,5 @@
 				 * rwl->lock is held.)
 				 */
-				cpu_priority_restore(pri);
+				interrupts_restore(ipl);
 				break;
 			case ESYNCH_OK_ATOMIC:
@@ -237,5 +237,5 @@
 	
 	spinlock_unlock(&rwl->lock);
-	cpu_priority_restore(pri);
+	interrupts_restore(ipl);
 
 	return ESYNCH_OK_ATOMIC;
@@ -252,11 +252,11 @@
 void rwlock_write_unlock(rwlock_t *rwl)
 {
-	pri_t pri;
-	
-	pri = cpu_priority_high();
+	ipl_t ipl;
+	
+	ipl = interrupts_disable();
 	spinlock_lock(&rwl->lock);
 	let_others_in(rwl, ALLOW_ALL);
 	spinlock_unlock(&rwl->lock);
-	cpu_priority_restore(pri);
+	interrupts_restore(ipl);
 	
 }
@@ -273,12 +273,12 @@
 void rwlock_read_unlock(rwlock_t *rwl)
 {
-	pri_t pri;
-
-	pri = cpu_priority_high();
+	ipl_t ipl;
+
+	ipl = interrupts_disable();
 	spinlock_lock(&rwl->lock);
 	if (!--rwl->readers_in)
 		let_others_in(rwl, ALLOW_ALL);
 	spinlock_unlock(&rwl->lock);
-	cpu_priority_restore(pri);
+	interrupts_restore(ipl);
 }
 
@@ -290,5 +290,5 @@
  *
  * Must be called with rwl->lock locked.
- * Must be called with cpu_priority_high'ed.
+ * Must be called with interrupts_disable()'d.
  *
  * @param rwl Reader/Writer lock.
Index: src/synch/semaphore.c
===================================================================
--- src/synch/semaphore.c	(revision 75eacab68dc113f30b4052b896fd86a2850ee834)
+++ src/synch/semaphore.c	(revision 22f776926d191e0d2eb1be9adfc28070c7ce11d4)
@@ -43,9 +43,9 @@
 void semaphore_initialize(semaphore_t *s, int val)
 {
-	pri_t pri;
+	ipl_t ipl;
 	
 	waitq_initialize(&s->wq);
 	
-	pri = cpu_priority_high();
+	ipl = interrupts_disable();
 
 	spinlock_lock(&s->wq.lock);
@@ -53,5 +53,5 @@
 	spinlock_unlock(&s->wq.lock);
 
-	cpu_priority_restore(pri);
+	interrupts_restore(ipl);
 }
 
Index: src/synch/waitq.c
===================================================================
--- src/synch/waitq.c	(revision 75eacab68dc113f30b4052b896fd86a2850ee834)
+++ src/synch/waitq.c	(revision 22f776926d191e0d2eb1be9adfc28070c7ce11d4)
@@ -138,9 +138,9 @@
 int waitq_sleep_timeout(waitq_t *wq, __u32 usec, int nonblocking)
 {
-	volatile pri_t pri; /* must be live after context_restore() */
+	volatile ipl_t ipl; /* must be live after context_restore() */
 	
 	
 restart:
-	pri = cpu_priority_high();
+	ipl = interrupts_disable();
 	
 	/*
@@ -154,5 +154,5 @@
 	if (THREAD->timeout_pending) {
 		spinlock_unlock(&THREAD->lock);
-		cpu_priority_restore(pri);		
+		interrupts_restore(ipl);		
 		goto restart;
 	}
@@ -165,5 +165,5 @@
 		wq->missed_wakeups--;
 		spinlock_unlock(&wq->lock);
-		cpu_priority_restore(pri);
+		interrupts_restore(ipl);
 		return ESYNCH_OK_ATOMIC;
 	}
@@ -172,5 +172,5 @@
 			/* return immediatelly instead of going to sleep */
 			spinlock_unlock(&wq->lock);
-			cpu_priority_restore(pri);
+			interrupts_restore(ipl);
 			return ESYNCH_WOULD_BLOCK;
 		}
@@ -190,5 +190,5 @@
 			before_thread_runs();
 			spinlock_unlock(&THREAD->lock);
-			cpu_priority_restore(pri);
+			interrupts_restore(ipl);
 			return ESYNCH_TIMEOUT;
 		}
@@ -208,5 +208,5 @@
 
 	scheduler(); 	/* wq->lock is released in scheduler_separated_stack() */
-	cpu_priority_restore(pri);
+	interrupts_restore(ipl);
 	
 	return ESYNCH_OK_BLOCKED;
@@ -229,7 +229,7 @@
 void waitq_wakeup(waitq_t *wq, int all)
 {
-	pri_t pri;
-
-	pri = cpu_priority_high();
+	ipl_t ipl;
+
+	ipl = interrupts_disable();
 	spinlock_lock(&wq->lock);
 
@@ -237,5 +237,5 @@
 
 	spinlock_unlock(&wq->lock);	
-	cpu_priority_restore(pri);	
+	interrupts_restore(ipl);	
 }
 
Index: src/time/clock.c
===================================================================
--- src/time/clock.c	(revision 75eacab68dc113f30b4052b896fd86a2850ee834)
+++ src/time/clock.c	(revision 22f776926d191e0d2eb1be9adfc28070c7ce11d4)
@@ -45,5 +45,5 @@
  *
  * Clock routine executed from clock interrupt handler
- * (assuming cpu_priority_high()). Runs expired timeouts
+ * (assuming interrupts_disable()'d). Runs expired timeouts
  * and preemptive scheduling.
  *
Index: src/time/delay.c
===================================================================
--- src/time/delay.c	(revision 75eacab68dc113f30b4052b896fd86a2850ee834)
+++ src/time/delay.c	(revision 22f776926d191e0d2eb1be9adfc28070c7ce11d4)
@@ -43,11 +43,14 @@
 void delay(__u32 usec)
 {
-	pri_t pri;
+	ipl_t ipl;
 	
-	/* The delay loop is calibrated for each and every
-	   CPU in the system. Therefore it is necessary to
-	   cpu_priority_high() before calling the asm_delay_loop(). */
-	pri = cpu_priority_high();
+	/* 
+	 * The delay loop is calibrated for each and every
+	 * CPU in the system. Therefore it is necessary to
+	 * call interrupts_disable() before calling the
+	 * asm_delay_loop().
+	 */
+	ipl = interrupts_disable();
 	asm_delay_loop(usec * CPU->delay_loop_const);
-	cpu_priority_restore(pri);
+	interrupts_restore(ipl);
 }
Index: src/time/timeout.c
===================================================================
--- src/time/timeout.c	(revision 75eacab68dc113f30b4052b896fd86a2850ee834)
+++ src/time/timeout.c	(revision 22f776926d191e0d2eb1be9adfc28070c7ce11d4)
@@ -101,8 +101,8 @@
 	timeout_t *hlp;
 	link_t *l, *m;
-	pri_t pri;
+	ipl_t ipl;
 	__u64 sum;
 
-	pri = cpu_priority_high();
+	ipl = interrupts_disable();
 	spinlock_lock(&CPU->timeoutlock);
 	spinlock_lock(&t->lock);
@@ -153,5 +153,5 @@
 	spinlock_unlock(&t->lock);
 	spinlock_unlock(&CPU->timeoutlock);
-	cpu_priority_restore(pri);
+	interrupts_restore(ipl);
 }
 
@@ -169,17 +169,17 @@
 	timeout_t *hlp;
 	link_t *l;
-	pri_t pri;
+	ipl_t ipl;
 
 grab_locks:
-	pri = cpu_priority_high();
+	ipl = interrupts_disable();
 	spinlock_lock(&t->lock);
 	if (!t->cpu) {
 		spinlock_unlock(&t->lock);
-		cpu_priority_restore(pri);
+		interrupts_restore(ipl);
 		return false;
 	}
 	if (!spinlock_trylock(&t->cpu->timeoutlock)) {
 		spinlock_unlock(&t->lock);
-		cpu_priority_restore(pri);		
+		interrupts_restore(ipl);		
 		goto grab_locks;
 	}
@@ -204,5 +204,5 @@
 	spinlock_unlock(&t->lock);
 
-	cpu_priority_restore(pri);
+	interrupts_restore(ipl);
 	return true;
 }
Index: test/synch/rwlock4/test.c
===================================================================
--- test/synch/rwlock4/test.c	(revision 75eacab68dc113f30b4052b896fd86a2850ee834)
+++ test/synch/rwlock4/test.c	(revision 22f776926d191e0d2eb1be9adfc28070c7ce11d4)
@@ -61,5 +61,5 @@
 {
 	__u32 rc;
-	pri_t pri;
+	ipl_t ipl;
 
 	spinlock_lock(&lock);	
Index: tools/amd64/gencontext.c
===================================================================
--- tools/amd64/gencontext.c	(revision 75eacab68dc113f30b4052b896fd86a2850ee834)
+++ tools/amd64/gencontext.c	(revision 22f776926d191e0d2eb1be9adfc28070c7ce11d4)
@@ -3,5 +3,5 @@
 
 typedef long long __u64;
-typedef __u64 pri_t;
+typedef __u64 ipl_t;
 
 #define __amd64_TYPES_H__
@@ -32,5 +32,5 @@
 	fprintf(f,"#define OFFSET_R14 0x%x\n",((int)&pctx->r14) - (int )pctx);
 	fprintf(f,"#define OFFSET_R15 0x%x\n",((int)&pctx->r15) - (int )pctx);
-	fprintf(f,"#define OFFSET_PRI 0x%x\n",((int)&pctx->pri) - (int )pctx);
+	fprintf(f,"#define OFFSET_IPL 0x%x\n",((int)&pctx->ipl) - (int )pctx);
 	fclose(f);
 
Index: tools/mips32/gencontext.c
===================================================================
--- tools/mips32/gencontext.c	(revision 75eacab68dc113f30b4052b896fd86a2850ee834)
+++ tools/mips32/gencontext.c	(revision 22f776926d191e0d2eb1be9adfc28070c7ce11d4)
@@ -3,5 +3,5 @@
 
 typedef unsigned int __u32;
-typedef __u32 pri_t;
+typedef __u32 ipl_t;
 
 #define __mips32_TYPES_H__