Changeset 22f7769 in mainline for arch/amd64

Timestamp:

2005-10-17T23:31:41Z (20 years ago)

Author:

Jakub Jermar <jakub@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

4b2c872d

Parents:

75eacab

Message:

Rename cpu_priority_{high|low|restore|read} functions to interrupts_{disable|enable|restore|read}.
Rename pri_t to ipl_t (Interrupt Priority Level).
Rename thread_t::pri to thread_t::priority.

Location:

arch/amd64

Files:

• include/asm.h (modified) (3 diffs)
• include/context.h (modified) (1 diff)
• include/types.h (modified) (1 diff)
• src/interrupt.c (modified) (1 diff)
• src/userspace.c (modified) (2 diffs)

arch/amd64/include/asm.h

@@ -83 +83 @@
 }
 
-/** Set priority level low
+/** Enable interrupts.
  *
  * Enable interrupts and return previous
  * value of EFLAGS.
- */
-static inline pri_t cpu_priority_low(void) {
-        pri_t v;
+ *
+ * @return Old interrupt priority level.
+ */
+static inline ipl_t interrupts_enable(void) {
+        ipl_t v;
         __asm__ volatile (
                 "pushfq\n"
@@ -99 +101 @@
 }
 
-/** Set priority level high
+/** Disable interrupts.
  *
  * Disable interrupts and return previous
  * value of EFLAGS.
- */
-static inline pri_t cpu_priority_high(void) {
-        pri_t v;
+ *
+ * @return Old interrupt priority level.
+ */
+static inline ipl_t interrupts_disable(void) {
+        ipl_t v;
         __asm__ volatile (
                 "pushfq\n"
@@ -115 +119 @@
 }
 
-/** Restore priority level
+/** Restore interrupt priority level.
  *
  * Restore EFLAGS.
- */
-static inline void cpu_priority_restore(pri_t pri) {
+ *
+ * @param ipl Saved interrupt priority level.
+ */
+static inline void interrupts_restore(ipl_t ipl) {
         __asm__ volatile (
                 "pushq %0\n"
                 "popfq\n"
-                : : "r" (pri)
-                );
-}
-
-/** Return raw priority level
+                : : "r" (ipl)
+                );
+}
+
+/** Return interrupt priority level.
  *
  * Return EFLAFS.
- */
-static inline pri_t cpu_priority_read(void) {
-        pri_t v;
+ *
+ * @return Current interrupt priority level.
+ */
+static inline ipl_t interrupts_read(void) {
+        ipl_t v;
         __asm__ volatile (
                 "pushfq\n"

arch/amd64/include/context.h

@@ -56 +56 @@
     __u64 r15;
 
-    pri_t pri;
+    ipl_t ipl;
 } __attribute__ ((packed));
 

arch/amd64/include/types.h

@@ -41 +41 @@
 typedef __u64 __address;
 
-/* Flags of processor (return value of cpu_priority_high()) */
-typedef __u64 pri_t;
+/* Flags of processor (return value of interrupts_disable()) */
+typedef __u64 ipl_t;
 
 typedef __u64 __native;

arch/amd64/src/interrupt.c

@@ -109 +109 @@
 /*
  * Called directly from the assembler code.
- * CPU is cpu_priority_high().
+ * CPU is interrupts_disable()'d.
  */
 void trap_dispatcher(__u8 n, __native stack[])

arch/amd64/src/userspace.c

@@ -42 +42 @@
 void userspace(void)
 {
-        pri_t pri;
+        ipl_t ipl;
         
-        pri = cpu_priority_high();
+        ipl = interrupts_disable();
 
         __asm__ volatile (""
@@ -58 +58 @@
                           "pushq %%rsi;"
                           "iretq;"
-                          : : "i" (gdtselector(UDATA_DES) | PL_USER), "i" (USTACK_ADDRESS+THREAD_STACK_SIZE), "r" (pri), "i" (gdtselector(UTEXT_DES) | PL_USER), "i" (UTEXT_ADDRESS));
+                          : : "i" (gdtselector(UDATA_DES) | PL_USER), "i" (USTACK_ADDRESS+THREAD_STACK_SIZE), "r" (ipl), "i" (gdtselector(UTEXT_DES) | PL_USER), "i" (UTEXT_ADDRESS));
         
         /* Unreachable */