Index: kernel/arch/amd64/include/asm.h =================================================================== --- kernel/arch/amd64/include/asm.h (revision e3038b41e1f6e1ef905bbc80916933e18d3e3008) +++ kernel/arch/amd64/include/asm.h (revision 22c3444da12c77181be739f433e57e2eb2ec3b70) @@ -39,7 +39,5 @@ #include #include - -extern void asm_delay_loop(uint32_t t); -extern void asm_fake_loop(uint32_t t); +#include /** Return base address of current stack. @@ -50,5 +48,5 @@ * */ -static inline uintptr_t get_stack_base(void) +NO_TRACE static inline uintptr_t get_stack_base(void) { uintptr_t v; @@ -57,5 +55,5 @@ "andq %%rsp, %[v]\n" : [v] "=r" (v) - : "0" (~((uint64_t) STACK_SIZE-1)) + : "0" (~((uint64_t) STACK_SIZE - 1)) ); @@ -63,10 +61,12 @@ } -static inline void cpu_sleep(void) -{ - asm volatile ("hlt\n"); -} - -static inline void __attribute__((noreturn)) cpu_halt(void) +NO_TRACE static inline void cpu_sleep(void) +{ + asm volatile ( + "hlt\n" + ); +} + +NO_TRACE static inline void __attribute__((noreturn)) cpu_halt(void) { while (true) { @@ -77,5 +77,4 @@ } - /** Byte from port * @@ -86,5 +85,5 @@ * */ -static inline uint8_t pio_read_8(ioport8_t *port) +NO_TRACE static inline uint8_t pio_read_8(ioport8_t *port) { uint8_t val; @@ -107,5 +106,5 @@ * */ -static inline uint16_t pio_read_16(ioport16_t *port) +NO_TRACE static inline uint16_t pio_read_16(ioport16_t *port) { uint16_t val; @@ -128,5 +127,5 @@ * */ -static inline uint32_t pio_read_32(ioport32_t *port) +NO_TRACE static inline uint32_t pio_read_32(ioport32_t *port) { uint32_t val; @@ -149,9 +148,10 @@ * */ -static inline void pio_write_8(ioport8_t *port, uint8_t val) +NO_TRACE static inline void pio_write_8(ioport8_t *port, uint8_t val) { asm volatile ( "outb %b[val], %w[port]\n" - :: [val] "a" (val), [port] "d" (port) + :: [val] "a" (val), + [port] "d" (port) ); } @@ -165,9 +165,10 @@ * */ -static inline void pio_write_16(ioport16_t *port, uint16_t val) +NO_TRACE static inline void pio_write_16(ioport16_t *port, uint16_t val) { asm volatile ( "outw %w[val], %w[port]\n" - :: [val] "a" (val), [port] "d" (port) + :: [val] "a" (val), + [port] "d" (port) ); } @@ -181,16 +182,19 @@ * */ -static inline void pio_write_32(ioport32_t *port, uint32_t val) +NO_TRACE static inline void pio_write_32(ioport32_t *port, uint32_t val) { asm volatile ( "outl %[val], %w[port]\n" - :: [val] "a" (val), [port] "d" (port) + :: [val] "a" (val), + [port] "d" (port) ); } /** Swap Hidden part of GS register with visible one */ -static inline void swapgs(void) -{ - asm volatile("swapgs"); +NO_TRACE static inline void swapgs(void) +{ + asm volatile ( + "swapgs" + ); } @@ -203,5 +207,5 @@ * */ -static inline ipl_t interrupts_enable(void) { +NO_TRACE static inline ipl_t interrupts_enable(void) { ipl_t v; @@ -224,5 +228,5 @@ * */ -static inline ipl_t interrupts_disable(void) { +NO_TRACE static inline ipl_t interrupts_disable(void) { ipl_t v; @@ -244,5 +248,5 @@ * */ -static inline void interrupts_restore(ipl_t ipl) { +NO_TRACE static inline void interrupts_restore(ipl_t ipl) { asm volatile ( "pushq %[ipl]\n" @@ -259,5 +263,5 @@ * */ -static inline ipl_t interrupts_read(void) { +NO_TRACE static inline ipl_t interrupts_read(void) { ipl_t v; @@ -276,5 +280,5 @@ * */ -static inline bool interrupts_disabled(void) +NO_TRACE static inline bool interrupts_disabled(void) { ipl_t v; @@ -289,7 +293,6 @@ } - /** Write to MSR */ -static inline void write_msr(uint32_t msr, uint64_t value) +NO_TRACE static inline void write_msr(uint32_t msr, uint64_t value) { asm volatile ( @@ -301,5 +304,5 @@ } -static inline unative_t read_msr(uint32_t msr) +NO_TRACE static inline unative_t read_msr(uint32_t msr) { uint32_t ax, dx; @@ -314,5 +317,4 @@ } - /** Enable local APIC * @@ -320,5 +322,5 @@ * */ -static inline void enable_l_apic_in_msr() +NO_TRACE static inline void enable_l_apic_in_msr() { asm volatile ( @@ -328,5 +330,5 @@ "orl $(0xfee00000),%%eax\n" "wrmsr\n" - ::: "%eax","%ecx","%edx" + ::: "%eax", "%ecx", "%edx" ); } @@ -337,5 +339,5 @@ * */ -static inline void invlpg(uintptr_t addr) +NO_TRACE static inline void invlpg(uintptr_t addr) { asm volatile ( @@ -350,5 +352,5 @@ * */ -static inline void gdtr_load(ptr_16_64_t *gdtr_reg) +NO_TRACE static inline void gdtr_load(ptr_16_64_t *gdtr_reg) { asm volatile ( @@ -363,5 +365,5 @@ * */ -static inline void gdtr_store(ptr_16_64_t *gdtr_reg) +NO_TRACE static inline void gdtr_store(ptr_16_64_t *gdtr_reg) { asm volatile ( @@ -376,5 +378,5 @@ * */ -static inline void idtr_load(ptr_16_64_t *idtr_reg) +NO_TRACE static inline void idtr_load(ptr_16_64_t *idtr_reg) { asm volatile ( @@ -388,5 +390,5 @@ * */ -static inline void tr_load(uint16_t sel) +NO_TRACE static inline void tr_load(uint16_t sel) { asm volatile ( @@ -396,5 +398,5 @@ } -#define GEN_READ_REG(reg) static inline unative_t read_ ##reg (void) \ +#define GEN_READ_REG(reg) NO_TRACE static inline unative_t read_ ##reg (void) \ { \ unative_t res; \ @@ -406,5 +408,5 @@ } -#define GEN_WRITE_REG(reg) static inline void write_ ##reg (unative_t regn) \ +#define GEN_WRITE_REG(reg) NO_TRACE static inline void write_ ##reg (unative_t regn) \ { \ asm volatile ( \ @@ -436,4 +438,7 @@ extern void interrupt_handlers(void); +extern void asm_delay_loop(uint32_t); +extern void asm_fake_loop(uint32_t); + #endif Index: kernel/arch/amd64/include/atomic.h =================================================================== --- kernel/arch/amd64/include/atomic.h (revision e3038b41e1f6e1ef905bbc80916933e18d3e3008) +++ kernel/arch/amd64/include/atomic.h (revision 22c3444da12c77181be739f433e57e2eb2ec3b70) @@ -39,6 +39,7 @@ #include #include +#include -static inline void atomic_inc(atomic_t *val) +NO_TRACE static inline void atomic_inc(atomic_t *val) { #ifdef CONFIG_SMP @@ -55,5 +56,5 @@ } -static inline void atomic_dec(atomic_t *val) +NO_TRACE static inline void atomic_dec(atomic_t *val) { #ifdef CONFIG_SMP @@ -70,5 +71,5 @@ } -static inline atomic_count_t atomic_postinc(atomic_t *val) +NO_TRACE static inline atomic_count_t atomic_postinc(atomic_t *val) { atomic_count_t r = 1; @@ -83,5 +84,5 @@ } -static inline atomic_count_t atomic_postdec(atomic_t *val) +NO_TRACE static inline atomic_count_t atomic_postdec(atomic_t *val) { atomic_count_t r = -1; @@ -99,5 +100,5 @@ #define atomic_predec(val) (atomic_postdec(val) - 1) -static inline atomic_count_t test_and_set(atomic_t *val) +NO_TRACE static inline atomic_count_t test_and_set(atomic_t *val) { atomic_count_t v = 1; @@ -113,5 +114,5 @@ /** amd64 specific fast spinlock */ -static inline void atomic_lock_arch(atomic_t *val) +NO_TRACE static inline void atomic_lock_arch(atomic_t *val) { atomic_count_t tmp; @@ -120,13 +121,13 @@ asm volatile ( "0:\n" - "pause\n" - "mov %[count], %[tmp]\n" - "testq %[tmp], %[tmp]\n" - "jnz 0b\n" /* lightweight looping on locked spinlock */ + " pause\n" + " mov %[count], %[tmp]\n" + " testq %[tmp], %[tmp]\n" + " jnz 0b\n" /* lightweight looping on locked spinlock */ - "incq %[tmp]\n" /* now use the atomic operation */ - "xchgq %[count], %[tmp]\n" - "testq %[tmp], %[tmp]\n" - "jnz 0b\n" + " incq %[tmp]\n" /* now use the atomic operation */ + " xchgq %[count], %[tmp]\n" + " testq %[tmp], %[tmp]\n" + " jnz 0b\n" : [count] "+m" (val->count), [tmp] "=&r" (tmp) Index: kernel/arch/amd64/include/cycle.h =================================================================== --- kernel/arch/amd64/include/cycle.h (revision e3038b41e1f6e1ef905bbc80916933e18d3e3008) +++ kernel/arch/amd64/include/cycle.h (revision 22c3444da12c77181be739f433e57e2eb2ec3b70) @@ -36,5 +36,7 @@ #define KERN_amd64_CYCLE_H_ -static inline uint64_t get_cycle(void) +#include + +NO_TRACE static inline uint64_t get_cycle(void) { uint32_t lower; Index: kernel/arch/amd64/include/interrupt.h =================================================================== --- kernel/arch/amd64/include/interrupt.h (revision e3038b41e1f6e1ef905bbc80916933e18d3e3008) +++ kernel/arch/amd64/include/interrupt.h (revision 22c3444da12c77181be739f433e57e2eb2ec3b70) @@ -38,24 +38,25 @@ #include #include +#include -#define IVT_ITEMS IDT_ITEMS -#define IVT_FIRST 0 +#define IVT_ITEMS IDT_ITEMS +#define IVT_FIRST 0 -#define EXC_COUNT 32 -#define IRQ_COUNT 16 +#define EXC_COUNT 32 +#define IRQ_COUNT 16 -#define IVT_EXCBASE 0 -#define IVT_IRQBASE (IVT_EXCBASE + EXC_COUNT) -#define IVT_FREEBASE (IVT_IRQBASE + IRQ_COUNT) +#define IVT_EXCBASE 0 +#define IVT_IRQBASE (IVT_EXCBASE + EXC_COUNT) +#define IVT_FREEBASE (IVT_IRQBASE + IRQ_COUNT) -#define IRQ_CLK 0 -#define IRQ_KBD 1 -#define IRQ_PIC1 2 -#define IRQ_PIC_SPUR 7 -#define IRQ_MOUSE 12 -#define IRQ_DP8390 9 +#define IRQ_CLK 0 +#define IRQ_KBD 1 +#define IRQ_PIC1 2 +#define IRQ_PIC_SPUR 7 +#define IRQ_MOUSE 12 +#define IRQ_DP8390 9 -/* this one must have four least significant bits set to ones */ -#define VECTOR_APIC_SPUR (IVT_ITEMS - 1) +/* This one must have four least significant bits set to ones */ +#define VECTOR_APIC_SPUR (IVT_ITEMS - 1) #if (((VECTOR_APIC_SPUR + 1) % 16) || VECTOR_APIC_SPUR >= IVT_ITEMS) @@ -63,10 +64,10 @@ #endif -#define VECTOR_DEBUG 1 -#define VECTOR_CLK (IVT_IRQBASE + IRQ_CLK) -#define VECTOR_PIC_SPUR (IVT_IRQBASE + IRQ_PIC_SPUR) -#define VECTOR_SYSCALL IVT_FREEBASE -#define VECTOR_TLB_SHOOTDOWN_IPI (IVT_FREEBASE + 1) -#define VECTOR_DEBUG_IPI (IVT_FREEBASE + 2) +#define VECTOR_DEBUG 1 +#define VECTOR_CLK (IVT_IRQBASE + IRQ_CLK) +#define VECTOR_PIC_SPUR (IVT_IRQBASE + IRQ_PIC_SPUR) +#define VECTOR_SYSCALL IVT_FREEBASE +#define VECTOR_TLB_SHOOTDOWN_IPI (IVT_FREEBASE + 1) +#define VECTOR_DEBUG_IPI (IVT_FREEBASE + 2) /** This is passed to interrupt handlers */ @@ -86,33 +87,36 @@ uint64_t cs; uint64_t rflags; - uint64_t stack[]; /* Additional data on stack */ + uint64_t stack[]; /* Additional data on stack */ } istate_t; /** Return true if exception happened while in userspace */ -static inline int istate_from_uspace(istate_t *istate) +NO_TRACE static inline int istate_from_uspace(istate_t *istate) { return !(istate->rip & 0x8000000000000000); } -static inline void istate_set_retaddr(istate_t *istate, uintptr_t retaddr) +NO_TRACE static inline void istate_set_retaddr(istate_t *istate, + uintptr_t retaddr) { istate->rip = retaddr; } -static inline unative_t istate_get_pc(istate_t *istate) + +NO_TRACE static inline unative_t istate_get_pc(istate_t *istate) { return istate->rip; } -static inline unative_t istate_get_fp(istate_t *istate) + +NO_TRACE static inline unative_t istate_get_fp(istate_t *istate) { return istate->rbp; } -extern void (* disable_irqs_function)(uint16_t irqmask); -extern void (* enable_irqs_function)(uint16_t irqmask); +extern void (* disable_irqs_function)(uint16_t); +extern void (* enable_irqs_function)(uint16_t); extern void (* eoi_function)(void); extern void interrupt_init(void); -extern void trap_virtual_enable_irqs(uint16_t irqmask); -extern void trap_virtual_disable_irqs(uint16_t irqmask); +extern void trap_virtual_enable_irqs(uint16_t); +extern void trap_virtual_disable_irqs(uint16_t); #endif Index: kernel/arch/amd64/include/mm/frame.h =================================================================== --- kernel/arch/amd64/include/mm/frame.h (revision e3038b41e1f6e1ef905bbc80916933e18d3e3008) +++ kernel/arch/amd64/include/mm/frame.h (revision 22c3444da12c77181be739f433e57e2eb2ec3b70) @@ -36,16 +36,18 @@ #define KERN_amd64_FRAME_H_ -#ifndef __ASM__ -#include -#endif /* __ASM__ */ - #define FRAME_WIDTH 12 /* 4K */ #define FRAME_SIZE (1 << FRAME_WIDTH) +#ifdef KERNEL #ifndef __ASM__ + +#include + extern uintptr_t last_frame; extern void frame_arch_init(void); extern void physmem_print(void); + #endif /* __ASM__ */ +#endif /* KERNEL */ #endif Index: kernel/arch/amd64/include/mm/page.h =================================================================== --- kernel/arch/amd64/include/mm/page.h (revision e3038b41e1f6e1ef905bbc80916933e18d3e3008) +++ kernel/arch/amd64/include/mm/page.h (revision 22c3444da12c77181be739f433e57e2eb2ec3b70) @@ -46,4 +46,5 @@ #include +#include #define PAGE_WIDTH FRAME_WIDTH @@ -187,5 +188,5 @@ } __attribute__ ((packed)) pte_t; -static inline unsigned int get_pt_flags(pte_t *pt, size_t i) +NO_TRACE static inline unsigned int get_pt_flags(pte_t *pt, size_t i) { pte_t *p = &pt[i]; @@ -200,5 +201,5 @@ } -static inline void set_pt_addr(pte_t *pt, size_t i, uintptr_t a) +NO_TRACE static inline void set_pt_addr(pte_t *pt, size_t i, uintptr_t a) { pte_t *p = &pt[i]; @@ -208,5 +209,5 @@ } -static inline void set_pt_flags(pte_t *pt, size_t i, int flags) +NO_TRACE static inline void set_pt_flags(pte_t *pt, size_t i, int flags) { pte_t *p = &pt[i];