Index: arch/ia64/include/mm/tlb.h
===================================================================
--- arch/ia64/include/mm/tlb.h	(revision 22870b22ce137c9f0fdbeb382497554f86dd86e5)
+++ arch/ia64/include/mm/tlb.h	(revision 208259c514adf11c285a7d79075e2270b2d64f47)
@@ -80,4 +80,5 @@
 
 extern void dtlb_kernel_mapping_insert(__address page, __address frame, bool dtr, index_t tr);
+extern void dtr_purge(__address page, count_t width);
 
 extern void dtc_pte_copy(pte_t *t);
Index: arch/ia64/src/mm/tlb.c
===================================================================
--- arch/ia64/src/mm/tlb.c	(revision 22870b22ce137c9f0fdbeb382497554f86dd86e5)
+++ arch/ia64/src/mm/tlb.c	(revision 208259c514adf11c285a7d79075e2270b2d64f47)
@@ -190,5 +190,4 @@
 }
 
-
 /** Insert data into data translation cache.
  *
@@ -342,7 +341,6 @@
 /** Insert data into DTLB.
  *
- * @param va Virtual page address.
- * @param asid Address space identifier.
- * @param entry The rest of TLB entry as required by TLB insertion format.
+ * @param page Virtual page address including VRN bits.
+ * @param frame Physical frame address.
  * @param dtr If true, insert into data translation register, use data translation cache otherwise.
  * @param tr Translation register if dtr is true, ignored otherwise.
@@ -369,4 +367,17 @@
 		dtc_mapping_insert(page, ASID_KERNEL, entry);
 }
+
+/** Purge kernel entries from DTR.
+ *
+ * Purge DTR entries used by the kernel.
+ *
+ * @param page Virtual page address including VRN bits.
+ * @param width Width of the purge in bits.
+ */
+void dtr_purge(__address page, count_t width)
+{
+	__asm__ volatile ("ptr.d %0, %1\n" : : "r" (page), "r" (width<<2));
+}
+
 
 /** Copy content of PTE into data translation cache.
Index: arch/ia64/src/proc/scheduler.c
===================================================================
--- arch/ia64/src/proc/scheduler.c	(revision 22870b22ce137c9f0fdbeb382497554f86dd86e5)
+++ arch/ia64/src/proc/scheduler.c	(revision 208259c514adf11c285a7d79075e2270b2d64f47)
@@ -54,4 +54,9 @@
 		 * Use DTR[TR_KSTACK1] and DTR[TR_KSTACK2] to map it.
 		 */
+		 
+		/* purge DTR[TR_STACK1] and DTR[TR_STACK2] */
+		dtr_purge((__address) THREAD->kstack, PAGE_WIDTH+1);
+		
+		/* insert DTR[TR_STACK1] and DTR[TR_STACK2] */
 		dtlb_kernel_mapping_insert((__address) THREAD->kstack, KA2PA(THREAD->kstack), true, DTR_KSTACK1);
 		dtlb_kernel_mapping_insert((__address) THREAD->kstack + PAGE_SIZE, KA2PA(THREAD->kstack) + FRAME_SIZE, true, DTR_KSTACK2);