Changeset 1f7cb3a in mainline
- Timestamp:
- 2009-02-14T20:14:38Z (16 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- 74bcf5e
- Parents:
- 6c1f763
- Files:
-
- 10 edited
Legend:
- Unmodified
- Added
- Removed
-
HelenOS.config
r6c1f763 r1f7cb3a 334 334 % Watchpoint on rewriting AS with zero 335 335 ! [CONFIG_DEBUG=y&(PLATFORM=amd64|PLATFORM=ia32)] CONFIG_DEBUG_AS_WATCHPOINT (y/n) 336 337 % Save all interrupt registers338 ! [CONFIG_DEBUG=y&(PLATFORM=amd64|PLATFORM=mips32|PLATFORM=ia32)] CONFIG_DEBUG_ALLREGS (y/n)339 336 340 337 % Compile kernel tests -
kernel/arch/amd64/include/interrupt.h
r6c1f763 r1f7cb3a 72 72 typedef struct { 73 73 uint64_t rax; 74 uint64_t rbx;75 74 uint64_t rcx; 76 75 uint64_t rdx; … … 81 80 uint64_t r10; 82 81 uint64_t r11; 83 uint64_t r12;84 uint64_t r13;85 uint64_t r14;86 uint64_t r15;87 uint64_t rbp;88 82 uint64_t error_word; 89 83 uint64_t rip; -
kernel/arch/amd64/src/asm_utils.S
r6c1f763 r1f7cb3a 27 27 # 28 28 29 #define IREGISTER_SPACE 120 30 31 #define IOFFSET_RAX 0x0 32 #define IOFFSET_RBX 0x8 33 #define IOFFSET_RCX 0x10 34 #define IOFFSET_RDX 0x18 35 #define IOFFSET_RSI 0x20 36 #define IOFFSET_RDI 0x28 37 #define IOFFSET_R8 0x30 38 #define IOFFSET_R9 0x38 39 #define IOFFSET_R10 0x40 40 #define IOFFSET_R11 0x48 41 #define IOFFSET_R12 0x50 42 #define IOFFSET_R13 0x58 43 #define IOFFSET_R14 0x60 44 #define IOFFSET_R15 0x68 45 #define IOFFSET_RBP 0x70 29 #define IREGISTER_SPACE 72 30 31 #define IOFFSET_RAX 0x0 32 #define IOFFSET_RCX 0x8 33 #define IOFFSET_RDX 0x10 34 #define IOFFSET_RSI 0x18 35 #define IOFFSET_RDI 0x20 36 #define IOFFSET_R8 0x28 37 #define IOFFSET_R9 0x30 38 #define IOFFSET_R10 0x38 39 #define IOFFSET_R11 0x40 46 40 47 41 # Mask for interrupts 0 - 31 (bits 0 - 31) where 0 means that int has no error word … … 174 168 ret 175 169 176 # Push all general purpose registers on stack except %rbp, %rsp170 # Push all volatile general purpose registers on stack 177 171 .macro save_all_gpr 178 172 movq %rax, IOFFSET_RAX(%rsp) … … 185 179 movq %r10, IOFFSET_R10(%rsp) 186 180 movq %r11, IOFFSET_R11(%rsp) 187 #ifdef CONFIG_DEBUG_ALLREGS188 movq %rbx, IOFFSET_RBX(%rsp)189 movq %rbp, IOFFSET_RBP(%rsp)190 movq %r12, IOFFSET_R12(%rsp)191 movq %r13, IOFFSET_R13(%rsp)192 movq %r14, IOFFSET_R14(%rsp)193 movq %r15, IOFFSET_R15(%rsp)194 #endif195 181 .endm 196 182 … … 205 191 movq IOFFSET_R10(%rsp), %r10 206 192 movq IOFFSET_R11(%rsp), %r11 207 #ifdef CONFIG_DEBUG_ALLREGS208 movq IOFFSET_RBX(%rsp), %rbx209 movq IOFFSET_RBP(%rsp), %rbp210 movq IOFFSET_R12(%rsp), %r12211 movq IOFFSET_R13(%rsp), %r13212 movq IOFFSET_R14(%rsp), %r14213 movq IOFFSET_R15(%rsp), %r15214 #endif215 193 .endm 216 194 217 #ifdef CONFIG_DEBUG_ALLREGS 218 # define INTERRUPT_ALIGN 256 219 #else 220 # define INTERRUPT_ALIGN 128 221 #endif 195 #define INTERRUPT_ALIGN 128 222 196 223 197 ## Declare interrupt handlers -
kernel/arch/amd64/src/interrupt.c
r6c1f763 r1f7cb3a 81 81 printf("%%r9=%#llx, %%r10=%#llx, %%r11=%#llx\n", istate->r9, 82 82 istate->r10, istate->r11); 83 #ifdef CONFIG_DEBUG_ALLREGS84 printf("%%r12=%#llx, %%r13=%#llx, %%r14=%#llx\n", istate->r12,85 istate->r13, istate->r14);86 printf("%%r15=%#llx, %%rbx=%#llx, %%rbp=%#llx\n", istate->r15,87 istate->rbx, &istate->rbp);88 #endif89 83 printf("%%rsp=%#llx\n", &istate->stack[0]); 90 84 } -
kernel/arch/ia32/include/interrupt.h
r6c1f763 r1f7cb3a 73 73 uint32_t ecx; 74 74 uint32_t edx; 75 uint32_t esi;76 uint32_t edi;77 uint32_t ebp;78 uint32_t ebx;79 75 80 76 uint32_t gs; -
kernel/arch/ia32/src/asm.S
r6c1f763 r1f7cb3a 269 269 pushl %gs 270 270 271 #ifdef CONFIG_DEBUG_ALLREGS272 pushl %ebx273 pushl %ebp274 pushl %edi275 pushl %esi276 #else277 subl $16, %esp278 #endif279 271 pushl %edx 280 272 pushl %ecx … … 298 290 popl %ecx 299 291 popl %edx 300 #ifdef CONFIG_DEBUG_ALLREGS301 popl %esi302 popl %edi303 popl %ebp304 popl %ebx305 #else306 addl $16, %esp307 #endif308 292 309 293 popl %gs -
kernel/arch/ia32/src/interrupt.c
r6c1f763 r1f7cb3a 78 78 printf("%%cs=%#lx,flags=%#lx\n", istate->cs, istate->eflags); 79 79 printf("%%eax=%#lx, %%ecx=%#lx, %%edx=%#lx, %%esp=%p\n", istate->eax, istate->ecx, istate->edx, &istate->stack[0]); 80 #ifdef CONFIG_DEBUG_ALLREGS81 printf("%%esi=%#lx, %%edi=%#lx, %%ebp=%#lx, %%ebx=%#lx\n", istate->esi, istate->edi, istate->ebp, istate->ebx);82 #endif83 80 printf("stack: %#lx, %#lx, %#lx, %#lx\n", istate->stack[0], istate->stack[1], istate->stack[2], istate->stack[3]); 84 81 printf(" %#lx, %#lx, %#lx, %#lx\n", istate->stack[4], istate->stack[5], istate->stack[6], istate->stack[7]); -
kernel/arch/mips32/include/context_offset.h
r6c1f763 r1f7cb3a 77 77 #define EOFFSET_T6 0x34 78 78 #define EOFFSET_T7 0x38 79 #define EOFFSET_S0 0x3c 80 #define EOFFSET_S1 0x40 81 #define EOFFSET_S2 0x44 82 #define EOFFSET_S3 0x48 83 #define EOFFSET_S4 0x4c 84 #define EOFFSET_S5 0x50 85 #define EOFFSET_S6 0x54 86 #define EOFFSET_S7 0x58 87 #define EOFFSET_T8 0x5c 88 #define EOFFSET_T9 0x60 89 #define EOFFSET_GP 0x64 90 #define EOFFSET_SP 0x68 91 #define EOFFSET_S8 0x6c 92 #define EOFFSET_RA 0x70 93 #define EOFFSET_LO 0x74 94 #define EOFFSET_HI 0x78 95 #define EOFFSET_STATUS 0x7c 96 #define EOFFSET_EPC 0x80 97 #define EOFFSET_K1 0x84 98 #define REGISTER_SPACE 136 79 #define EOFFSET_T8 0x3c 80 #define EOFFSET_T9 0x40 81 #define EOFFSET_GP 0x44 82 #define EOFFSET_SP 0x48 83 #define EOFFSET_RA 0x4c 84 #define EOFFSET_LO 0x50 85 #define EOFFSET_HI 0x54 86 #define EOFFSET_STATUS 0x58 87 #define EOFFSET_EPC 0x5c 88 #define EOFFSET_K1 0x60 89 #define REGISTER_SPACE 100 99 90 100 91 #ifdef __ASM__ -
kernel/arch/mips32/include/exception.h
r6c1f763 r1f7cb3a 74 74 uint32_t t6; 75 75 uint32_t t7; 76 uint32_t s0;77 uint32_t s1;78 uint32_t s2;79 uint32_t s3;80 uint32_t s4;81 uint32_t s5;82 uint32_t s6;83 uint32_t s7;84 76 uint32_t t8; 85 77 uint32_t t9; 86 78 uint32_t gp; 87 79 uint32_t sp; 88 uint32_t s8;89 80 uint32_t ra; 90 81 -
kernel/arch/mips32/src/start.S
r6c1f763 r1f7cb3a 76 76 sw $at, EOFFSET_HI(\r) 77 77 78 #ifdef CONFIG_DEBUG_ALLREGS79 sw $s0, EOFFSET_S0(\r)80 sw $s1, EOFFSET_S1(\r)81 sw $s2, EOFFSET_S2(\r)82 sw $s3, EOFFSET_S3(\r)83 sw $s4, EOFFSET_S4(\r)84 sw $s5, EOFFSET_S5(\r)85 sw $s6, EOFFSET_S6(\r)86 sw $s7, EOFFSET_S7(\r)87 sw $s8, EOFFSET_S8(\r)88 #endif89 90 78 sw $gp, EOFFSET_GP(\r) 91 79 sw $ra, EOFFSET_RA(\r) … … 133 121 lw $t9, EOFFSET_T9(\r) 134 122 135 #ifdef CONFIG_DEBUG_ALLREGS136 lw $s0, EOFFSET_S0(\r)137 lw $s1, EOFFSET_S1(\r)138 lw $s2, EOFFSET_S2(\r)139 lw $s3, EOFFSET_S3(\r)140 lw $s4, EOFFSET_S4(\r)141 lw $s5, EOFFSET_S5(\r)142 lw $s6, EOFFSET_S6(\r)143 lw $s7, EOFFSET_S7(\r)144 lw $s8, EOFFSET_S8(\r)145 #endif146 123 lw $gp, EOFFSET_GP(\r) 147 124 lw $ra, EOFFSET_RA(\r)
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