Index: kernel/arch/sparc64/include/barrier.h
===================================================================
--- kernel/arch/sparc64/include/barrier.h	(revision 9a8baed2206157ee870432337f1815001239ff8a)
+++ kernel/arch/sparc64/include/barrier.h	(revision 1ecdbb0a73519ade1b15b6c908b07dfce755b6cc)
@@ -37,14 +37,24 @@
 
 /*
- * We assume TSO memory model in which only reads can pass earlier stores
- * (but not earlier reads). Therefore, CS_ENTER_BARRIER() and CS_LEAVE_BARRIER()
- * can be empty.
+ * Our critical section barriers are prepared for the weakest RMO memory model.
  */
-#define CS_ENTER_BARRIER()	__asm__ volatile ("" ::: "memory")
-#define CS_LEAVE_BARRIER()	__asm__ volatile ("" ::: "memory")
+#define CS_ENTER_BARRIER() 				\
+	__asm__ volatile (				\
+		"membar #LoadLoad | #LoadStore\n"	\
+		::: "memory"				\
+	)
+#define CS_LEAVE_BARRIER()				\
+	__asm__ volatile ( 				\
+		"membar #StoreStore\n"			\
+		"membar #LoadStore\n"			\
+		::: "memory"				\
+	)
 
-#define memory_barrier()	__asm__ volatile ("membar #LoadLoad | #StoreStore\n" ::: "memory")
-#define read_barrier()		__asm__ volatile ("membar #LoadLoad\n" ::: "memory")
-#define write_barrier()		__asm__ volatile ("membar #StoreStore\n" ::: "memory")
+#define memory_barrier()	\
+	__asm__ volatile ("membar #LoadLoad | #StoreStore\n" ::: "memory")
+#define read_barrier()		\
+	__asm__ volatile ("membar #LoadLoad\n" ::: "memory")
+#define write_barrier()		\
+	__asm__ volatile ("membar #StoreStore\n" ::: "memory")
 
 /** Flush Instruction Memory instruction. */