Index: uspace/drv/bus/isa/isa.c
===================================================================
--- uspace/drv/bus/isa/isa.c	(revision b2dca8de8634dcb5e4d4674aa9007210da4bc6a4)
+++ uspace/drv/bus/isa/isa.c	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -739,5 +739,5 @@
 		    "for the device.");
 		return rc;
-	}	
+	}
 
 	/* Make the bus device more visible. Does not do anything. */
Index: uspace/drv/bus/pci/pciintel/pci.c
===================================================================
--- uspace/drv/bus/pci/pciintel/pci.c	(revision b2dca8de8634dcb5e4d4674aa9007210da4bc6a4)
+++ uspace/drv/bus/pci/pciintel/pci.c	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -539,5 +539,5 @@
 		return addr + (addrw64 ? 8 : 4);
 
-	mask &= bar;	
+	mask &= bar;
 
 	/* Restore the original value. */
@@ -599,5 +599,5 @@
  * @param bus_num	Bus number
  */
-void pci_bus_scan(pci_bus_t *bus, int bus_num) 
+void pci_bus_scan(pci_bus_t *bus, int bus_num)
 {
 	pci_fun_t *fun;
Index: uspace/drv/bus/pci/pciintel/pci.h
===================================================================
--- uspace/drv/bus/pci/pciintel/pci.h	(revision b2dca8de8634dcb5e4d4674aa9007210da4bc6a4)
+++ uspace/drv/bus/pci/pciintel/pci.h	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -40,5 +40,5 @@
 #include "pci_regs.h"
 
-#define PCI_MAX_HW_RES 10 
+#define PCI_MAX_HW_RES 10
 
 typedef struct pciintel_bus {
Index: uspace/drv/bus/usb/ohci/ohci_batch.c
===================================================================
--- uspace/drv/bus/usb/ohci/ohci_batch.c	(revision b2dca8de8634dcb5e4d4674aa9007210da4bc6a4)
+++ uspace/drv/bus/usb/ohci/ohci_batch.c	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -199,5 +199,5 @@
 			assert((ohci_ep->ed->td_head & ED_TDHEAD_HALTED_FLAG) != 0);
 
-			/* We don't care where the processing stopped, we just 
+			/* We don't care where the processing stopped, we just
 			 * need to make sure it's not using any of the TDs owned
 			 * by the transfer.