Index: kernel/arch/abs32le/include/arch/stack.h
===================================================================
--- kernel/arch/abs32le/include/arch/stack.h	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/abs32le/include/arch/stack.h	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -27,5 +27,5 @@
  */
 
-/** @addtogroup abs32le	
+/** @addtogroup abs32le
  * @{
  */
Index: kernel/arch/abs32le/src/smp/smp_call.c
===================================================================
--- kernel/arch/abs32le/src/smp/smp_call.c	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/abs32le/src/smp/smp_call.c	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -27,5 +27,5 @@
  */
 
-/** @addtogroup abs32le 
+/** @addtogroup abs32le
  * @{
  */
Index: kernel/arch/amd64/include/arch/asm.h
===================================================================
--- kernel/arch/amd64/include/arch/asm.h	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/amd64/include/arch/asm.h	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -165,5 +165,5 @@
 			"outb %b[val], %w[port]\n"
 			:: [val] "a" (val), [port] "d" (port)
-		);	
+		);
 	} else
 		*port = val;
Index: kernel/arch/amd64/include/arch/atomic.h
===================================================================
--- kernel/arch/amd64/include/arch/atomic.h	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/amd64/include/arch/atomic.h	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -232,7 +232,7 @@
 
 #ifndef local_atomic_exchange
-/* 
+/*
  * Issuing a xchg instruction always implies lock prefix semantics.
- * Therefore, it is cheaper to use a cmpxchg without a lock prefix 
+ * Therefore, it is cheaper to use a cmpxchg without a lock prefix
  * in a loop.
  */
Index: kernel/arch/amd64/include/arch/context_struct.ag
===================================================================
--- kernel/arch/amd64/include/arch/context_struct.ag	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/amd64/include/arch/context_struct.ag	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -1,3 +1,3 @@
-# Copyright (c) 2014 Jakub Jermar 
+# Copyright (c) 2014 Jakub Jermar
 # All rights reserved.
 #
Index: kernel/arch/amd64/include/arch/istate_struct.ag
===================================================================
--- kernel/arch/amd64/include/arch/istate_struct.ag	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/amd64/include/arch/istate_struct.ag	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -1,3 +1,3 @@
-# Copyright (c) 2014 Jakub Jermar 
+# Copyright (c) 2014 Jakub Jermar
 # All rights reserved.
 #
Index: kernel/arch/amd64/include/arch/kseg.h
===================================================================
--- kernel/arch/amd64/include/arch/kseg.h	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/amd64/include/arch/kseg.h	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -27,5 +27,5 @@
  */
 
-/** @addtogroup amd64 
+/** @addtogroup amd64
  * @{
  */
Index: kernel/arch/amd64/include/arch/kseg_struct.ag
===================================================================
--- kernel/arch/amd64/include/arch/kseg_struct.ag	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/amd64/include/arch/kseg_struct.ag	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -1,3 +1,3 @@
-# Copyright (c) 2016 Jakub Jermar 
+# Copyright (c) 2016 Jakub Jermar
 # All rights reserved.
 #
Index: kernel/arch/amd64/include/arch/pm.h
===================================================================
--- kernel/arch/amd64/include/arch/pm.h	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/amd64/include/arch/pm.h	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -115,5 +115,5 @@
 	unsigned : 2;
 	unsigned granularity : 1;
-	unsigned base_24_31: 8;	
+	unsigned base_24_31: 8;
 	unsigned base_32_63 : 32;
 	unsigned  : 32;
Index: kernel/arch/amd64/include/arch/vreg.h
===================================================================
--- kernel/arch/amd64/include/arch/vreg.h	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/amd64/include/arch/vreg.h	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -27,5 +27,5 @@
  */
 
-/** @addtogroup amd64 
+/** @addtogroup amd64
  * @{
  */
Index: kernel/arch/amd64/src/asm.S
===================================================================
--- kernel/arch/amd64/src/asm.S	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/amd64/src/asm.S	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -263,5 +263,5 @@
 SYMBOL(interrupt_handlers)
 .irp cnt, LIST_0_63
-	handler \cnt 
+	handler \cnt
 .endr
 
@@ -307,5 +307,5 @@
 	movq %rcx, ISTATE_OFFSET_RCX(%rsp)  /* userspace RIP */
 	movq %rdx, ISTATE_OFFSET_RDX(%rsp)  /* 3rd argument, observability */
-	movq %rsi, ISTATE_OFFSET_RSI(%rsp)  /* 2nd argument, observability */ 
+	movq %rsi, ISTATE_OFFSET_RSI(%rsp)  /* 2nd argument, observability */
 	movq %rdi, ISTATE_OFFSET_RDI(%rsp)  /* 1st argument, observability */
 	movq %rbp, ISTATE_OFFSET_RBP(%rsp)  /* need to preserve userspace RBP */
@@ -361,5 +361,5 @@
 	 */
 	testw $0xffff, ISTATE_OFFSET_RIP+6(%rsp)
-	jnz bad_rip 
+	jnz bad_rip
 
 	cli
Index: kernel/arch/amd64/src/cpu/cpu.c
===================================================================
--- kernel/arch/amd64/src/cpu/cpu.c	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/amd64/src/cpu/cpu.c	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -81,5 +81,5 @@
 /** Set the TS flag to 1.
  *
- * If a thread accesses coprocessor, exception is run, which 
+ * If a thread accesses coprocessor, exception is run, which
  * does a lazy fpu context switch.
  *
Index: kernel/arch/amd64/src/interrupt.c
===================================================================
--- kernel/arch/amd64/src/interrupt.c	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/amd64/src/interrupt.c	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -230,5 +230,5 @@
 	exc_register(VECTOR_TLB_SHOOTDOWN_IPI, "tlb_shootdown", true,
 	    (iroutine_t) tlb_shootdown_ipi);
-	exc_register(VECTOR_SMP_CALL_IPI, "smp_call", true, 
+	exc_register(VECTOR_SMP_CALL_IPI, "smp_call", true,
 		(iroutine_t) arch_smp_call_ipi_recv);
 #endif
Index: kernel/arch/amd64/src/kseg.c
===================================================================
--- kernel/arch/amd64/src/kseg.c	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/amd64/src/kseg.c	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -27,5 +27,5 @@
  */
 
-/** @addtogroup amd64 
+/** @addtogroup amd64
  * @{
  */
Index: kernel/arch/amd64/src/proc/scheduler.c
===================================================================
--- kernel/arch/amd64/src/proc/scheduler.c	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/amd64/src/proc/scheduler.c	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -58,5 +58,5 @@
 	CPU->arch.tss->rsp0 = (uintptr_t) &THREAD->kstack[STACK_SIZE];
 
-	kseg_t *kseg = (kseg_t *) read_msr(AMD_MSR_GS_KERNEL);	
+	kseg_t *kseg = (kseg_t *) read_msr(AMD_MSR_GS_KERNEL);
 	kseg->kstack_rsp = THREAD->arch.kstack_rsp;
 }
Index: kernel/arch/amd64/src/syscall.c
===================================================================
--- kernel/arch/amd64/src/syscall.c	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/amd64/src/syscall.c	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -60,5 +60,5 @@
 	    ((uint64_t) (GDT_SELECTOR(KTEXT_DES) | PL_KERNEL) << 32));
 	write_msr(AMD_MSR_LSTAR, (uint64_t)syscall_entry);
-	/* Mask RFLAGS on syscall 
+	/* Mask RFLAGS on syscall
 	 * - disable interrupts, until we exchange the stack register
 	 *   (mask the IF bit)
Index: kernel/arch/amd64/src/vreg.c
===================================================================
--- kernel/arch/amd64/src/vreg.c	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/amd64/src/vreg.c	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -27,5 +27,5 @@
  */
 
-/** @addtogroup amd64 
+/** @addtogroup amd64
  * @{
  */
@@ -71,5 +71,5 @@
 	write_msr(AMD_MSR_FS, (uintptr_t) page);
 
-	vreg_ptr = NULL; 
+	vreg_ptr = NULL;
 }
 
Index: kernel/arch/arm32/include/arch/asm.h
===================================================================
--- kernel/arch/arm32/include/arch/asm.h	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/arm32/include/arch/asm.h	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -107,5 +107,5 @@
 	
 	asm volatile (
-		"and %[v], sp, %[size]\n" 
+		"and %[v], sp, %[size]\n"
 		: [v] "=r" (v)
 		: [size] "r" (~(STACK_SIZE - 1))
Index: kernel/arch/arm32/include/arch/barrier.h
===================================================================
--- kernel/arch/arm32/include/arch/barrier.h	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/arm32/include/arch/barrier.h	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -78,5 +78,5 @@
 #define memory_barrier()  CP15DSB_write(0)
 #endif
-#define read_barrier()    CP15DSB_write(0) 
+#define read_barrier()    CP15DSB_write(0)
 #define write_barrier()   read_barrier()
 #if defined(PROCESSOR_ARCH_armv6) || defined(PROCESSOR_ARCH_armv7_a)
Index: kernel/arch/arm32/include/arch/context_struct.ag
===================================================================
--- kernel/arch/arm32/include/arch/context_struct.ag	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/arm32/include/arch/context_struct.ag	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -1,3 +1,3 @@
-# Copyright (c) 2014 Jakub Jermar 
+# Copyright (c) 2014 Jakub Jermar
 # All rights reserved.
 #
Index: kernel/arch/arm32/include/arch/fpu_context.h
===================================================================
--- kernel/arch/arm32/include/arch/fpu_context.h	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/arm32/include/arch/fpu_context.h	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -27,5 +27,5 @@
  */
 
-/** @addtogroup arm32	
+/** @addtogroup arm32
  * @{
  */
Index: kernel/arch/arm32/include/arch/istate_struct.ag
===================================================================
--- kernel/arch/arm32/include/arch/istate_struct.ag	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/arm32/include/arch/istate_struct.ag	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -1,3 +1,3 @@
-# Copyright (c) 2014 Jakub Jermar 
+# Copyright (c) 2014 Jakub Jermar
 # All rights reserved.
 #
Index: kernel/arch/arm32/include/arch/mm/as.h
===================================================================
--- kernel/arch/arm32/include/arch/mm/as.h	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/arm32/include/arch/mm/as.h	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -27,5 +27,5 @@
  */
 
-/** @addtogroup arm32mm	
+/** @addtogroup arm32mm
  * @{
  */
Index: kernel/arch/arm32/include/arch/mm/asid.h
===================================================================
--- kernel/arch/arm32/include/arch/mm/asid.h	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/arm32/include/arch/mm/asid.h	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -27,5 +27,5 @@
  */
 
-/** @addtogroup arm32mm	
+/** @addtogroup arm32mm
  * @{
  */
@@ -51,5 +51,5 @@
 #define asid_get()		(ASID_START + 1)
 
-#define asid_put(asid) 
+#define asid_put(asid)
 
 #endif
Index: kernel/arch/arm32/include/arch/stack.h
===================================================================
--- kernel/arch/arm32/include/arch/stack.h	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/arm32/include/arch/stack.h	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -27,5 +27,5 @@
  */
 
-/** @addtogroup arm32	
+/** @addtogroup arm32
  * @{
  */
Index: kernel/arch/arm32/src/atomic.c
===================================================================
--- kernel/arch/arm32/src/atomic.c	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/arm32/src/atomic.c	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -46,5 +46,5 @@
 void * __sync_val_compare_and_swap_4(void **ptr, void *expected, void *new_val)
 {
-	/* 
+	/*
 	 * Using an interrupt disabling spinlock might still lead to deadlock
 	 * if CAS() is used in an exception handler. Eg. if a CAS() results
Index: kernel/arch/arm32/src/context.S
===================================================================
--- kernel/arch/arm32/src/context.S	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/arm32/src/context.S	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -29,5 +29,5 @@
 #include <abi/asmtool.h>
 
-.text   
+.text
 
 FUNCTION_BEGIN(context_save_arch)
Index: kernel/arch/arm32/src/exc_handler.S
===================================================================
--- kernel/arch/arm32/src/exc_handler.S	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/arm32/src/exc_handler.S	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -29,5 +29,5 @@
 #include <abi/asmtool.h>
 
-.text   
+.text
 
 # Switches to kernel stack and saves all registers there.
Index: kernel/arch/arm32/src/interrupt.c
===================================================================
--- kernel/arch/arm32/src/interrupt.c	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/arm32/src/interrupt.c	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -73,5 +73,5 @@
 {
 	current_status_reg_control_write(
-	    (current_status_reg_read() & ~STATUS_REG_IRQ_DISABLED_BIT) | 
+	    (current_status_reg_read() & ~STATUS_REG_IRQ_DISABLED_BIT) |
 	    (ipl & STATUS_REG_IRQ_DISABLED_BIT));
 }
Index: kernel/arch/arm32/src/mach/integratorcp/integratorcp.c
===================================================================
--- kernel/arch/arm32/src/mach/integratorcp/integratorcp.c	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/arm32/src/mach/integratorcp/integratorcp.c	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -113,5 +113,5 @@
 
 /** Masks interrupt.
- * 
+ *
  * @param irq interrupt number
  */
@@ -123,5 +123,5 @@
 
 /** Unmasks interrupt.
- * 
+ *
  * @param irq interrupt number
  */
Index: kernel/arch/arm32/src/mm/as.c
===================================================================
--- kernel/arch/arm32/src/mm/as.c	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/arm32/src/mm/as.c	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -43,5 +43,5 @@
 
 /** Architecture dependent address space init.
- *  
+ *
  *  Since ARM supports page tables, #as_pt_operations are used.
  */
Index: kernel/arch/arm32/src/mm/tlb.c
===================================================================
--- kernel/arch/arm32/src/mm/tlb.c	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/arm32/src/mm/tlb.c	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -27,5 +27,5 @@
  */
 
-/** @addtogroup arm32mm	
+/** @addtogroup arm32mm
  * @{
  */
Index: kernel/arch/arm32/src/ras.c
===================================================================
--- kernel/arch/arm32/src/ras.c	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/arm32/src/ras.c	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -59,5 +59,5 @@
 	    PAGE_SIZE, PAGE_READ | PAGE_WRITE | PAGE_USER | PAGE_CACHEABLE);
 	
-	memsetb(ras_page, PAGE_SIZE, 0); 
+	memsetb(ras_page, PAGE_SIZE, 0);
 	ras_page[RAS_START] = 0;
 	ras_page[RAS_END] = 0xffffffff;
Index: kernel/arch/ia32/include/arch/asm.h
===================================================================
--- kernel/arch/ia32/include/arch/asm.h	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/ia32/include/arch/asm.h	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -119,5 +119,5 @@
 			"outb %b[val], %w[port]\n"
 			:: [val] "a" (val), [port] "d" (port)
-		);	
+		);
 	} else
 		*port = val;
@@ -417,5 +417,5 @@
 {
 	asm volatile (
-		"lidtl %[idtr_reg]\n" 
+		"lidtl %[idtr_reg]\n"
 		:: [idtr_reg] "m" (*idtr_reg)
 	);
Index: kernel/arch/ia32/include/arch/atomic.h
===================================================================
--- kernel/arch/ia32/include/arch/atomic.h	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/ia32/include/arch/atomic.h	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -220,7 +220,7 @@
 
 #ifndef local_atomic_exchange
-/* 
+/*
  * Issuing a xchg instruction always implies lock prefix semantics.
- * Therefore, it is cheaper to use a cmpxchg without a lock prefix 
+ * Therefore, it is cheaper to use a cmpxchg without a lock prefix
  * in a loop.
  */
Index: kernel/arch/ia32/include/arch/boot/memmap_struct.ag
===================================================================
--- kernel/arch/ia32/include/arch/boot/memmap_struct.ag	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/ia32/include/arch/boot/memmap_struct.ag	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -1,3 +1,3 @@
-# Copyright (c) 2016 Jakub Jermar 
+# Copyright (c) 2016 Jakub Jermar
 # All rights reserved.
 #
Index: kernel/arch/ia32/include/arch/context_struct.ag
===================================================================
--- kernel/arch/ia32/include/arch/context_struct.ag	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/ia32/include/arch/context_struct.ag	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -1,3 +1,3 @@
-# Copyright (c) 2014 Jakub Jermar 
+# Copyright (c) 2014 Jakub Jermar
 # All rights reserved.
 #
Index: kernel/arch/ia32/include/arch/cpu.h
===================================================================
--- kernel/arch/ia32/include/arch/cpu.h	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/ia32/include/arch/cpu.h	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -43,5 +43,5 @@
 #define EFLAGS_ID	(1 << 21)
 
-#define CR0_PE		(1 << 0) 
+#define CR0_PE		(1 << 0)
 #define CR0_TS		(1 << 3)
 #define CR0_AM		(1 << 18)
Index: kernel/arch/ia32/include/arch/istate_struct.ag
===================================================================
--- kernel/arch/ia32/include/arch/istate_struct.ag	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/ia32/include/arch/istate_struct.ag	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -1,3 +1,3 @@
-# Copyright (c) 2014 Jakub Jermar 
+# Copyright (c) 2014 Jakub Jermar
 # All rights reserved.
 #
Index: kernel/arch/ia32/include/arch/mm/page.h
===================================================================
--- kernel/arch/ia32/include/arch/mm/page.h	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/ia32/include/arch/mm/page.h	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -161,5 +161,5 @@
 #define PFERR_CODE_US		(1 << 2)
 
-/** When bit on this position is 1, a reserved bit was set in page directory. */ 
+/** When bit on this position is 1, a reserved bit was set in page directory. */
 #define PFERR_CODE_RSVD		(1 << 3)
 
Index: kernel/arch/ia32/src/asm.S
===================================================================
--- kernel/arch/ia32/src/asm.S	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/ia32/src/asm.S	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -139,5 +139,5 @@
  * and without the error word.
  */
-#define ISTATE_SOFT_SIZE	ISTATE_SIZE - (6 * 4) 
+#define ISTATE_SOFT_SIZE	ISTATE_SIZE - (6 * 4)
 
 /*
@@ -329,5 +329,5 @@
 	.else
 		/*
-		 * Interrupt: fake up an error word 
+		 * Interrupt: fake up an error word
 		 */
 		subl $(ISTATE_SOFT_SIZE + 4), %esp
@@ -433,5 +433,5 @@
 
 interrupt_handlers:
-.irp cnt, LIST_0_63 
+.irp cnt, LIST_0_63
 	handler \cnt
 .endr
Index: kernel/arch/ia32/src/atomic.S
===================================================================
--- kernel/arch/ia32/src/atomic.S	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/ia32/src/atomic.S	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -34,5 +34,5 @@
 
 #
-# This is a bus-and-hyperthreading-friendly implementation of spinlock 
+# This is a bus-and-hyperthreading-friendly implementation of spinlock
 #
 FUNCTION_BEGIN(spinlock_arch)
@@ -42,5 +42,5 @@
 	movl 12(%esp),%ebx
 
-0:	
+0:
 	pause			# Pentium 4's with HT love this instruction
 	movl (%ebx),%eax
Index: kernel/arch/ia32/src/context.S
===================================================================
--- kernel/arch/ia32/src/context.S	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/ia32/src/context.S	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -39,6 +39,6 @@
 #
 FUNCTION_BEGIN(context_save_arch)
-	movl 0(%esp), %eax	# save pc value into eax	
-	movl 4(%esp), %edx	# address of the context variable to save context to 
+	movl 0(%esp), %eax	# save pc value into eax
+	movl 4(%esp), %edx	# address of the context variable to save context to
 
 	# save registers to given structure
Index: kernel/arch/ia32/src/cpu/cpu.c
===================================================================
--- kernel/arch/ia32/src/cpu/cpu.c	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/ia32/src/cpu/cpu.c	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -72,10 +72,10 @@
 void fpu_disable(void)
 {
-	write_cr0(read_cr0() & ~CR0_TS); 
+	write_cr0(read_cr0() & ~CR0_TS);
 }
 
 void fpu_enable(void)
 {
-	write_cr0(read_cr0() | CR0_TS); 
+	write_cr0(read_cr0() | CR0_TS);
 }
 
@@ -150,5 +150,5 @@
 void cpu_print_report(cpu_t* cpu)
 {
-	printf("cpu%u: (%s family=%u model=%u stepping=%u apicid=%u) %" PRIu16 
+	printf("cpu%u: (%s family=%u model=%u stepping=%u apicid=%u) %" PRIu16
 		" MHz\n", cpu->id, vendor_str[cpu->arch.vendor], cpu->arch.family,
 		cpu->arch.model, cpu->arch.stepping, cpu->arch.id, cpu->frequency_mhz);
Index: kernel/arch/ia32/src/smp/ap.S
===================================================================
--- kernel/arch/ia32/src/smp/ap.S	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/ia32/src/smp/ap.S	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -47,5 +47,5 @@
 KDATA=16
 
-/* 
+/*
  * This piece of code is real-mode and is meant to be aligned at 4K boundary.
  * The requirement for such an alignment comes from MP Specification's
Index: kernel/arch/ia32/src/smp/smp.c
===================================================================
--- kernel/arch/ia32/src/smp/smp.c	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/ia32/src/smp/smp.c	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -106,5 +106,5 @@
 
 	/*
-	 * SMP initialized, cpus array allocated. Assign each CPU its 
+	 * SMP initialized, cpus array allocated. Assign each CPU its
 	 * physical APIC ID.
 	 */
Index: kernel/arch/ia32/src/vreg.c
===================================================================
--- kernel/arch/ia32/src/vreg.c	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/ia32/src/vreg.c	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -75,5 +75,5 @@
 	gs_load(GDT_SELECTOR(VREG_DES));
 
-	vreg_ptr = NULL; 
+	vreg_ptr = NULL;
 }
 
Index: kernel/arch/ia64/include/arch/barrier.h
===================================================================
--- kernel/arch/ia64/include/arch/barrier.h	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/ia64/include/arch/barrier.h	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -27,5 +27,5 @@
  */
 
-/** @addtogroup ia64	
+/** @addtogroup ia64
  * @{
  */
@@ -52,5 +52,5 @@
 
 #define fc_i(a)			\
-	asm volatile ("fc.i %0\n" :: "r" ((a)) : "memory")  
+	asm volatile ("fc.i %0\n" :: "r" ((a)) : "memory")
 #define sync_i()		\
 	asm volatile (";; sync.i\n" ::: "memory")
Index: kernel/arch/ia64/include/arch/context_struct.ag
===================================================================
--- kernel/arch/ia64/include/arch/context_struct.ag	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/ia64/include/arch/context_struct.ag	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -1,3 +1,3 @@
-# Copyright (c) 2014 Jakub Jermar 
+# Copyright (c) 2014 Jakub Jermar
 # All rights reserved.
 #
Index: kernel/arch/ia64/include/arch/drivers/it.h
===================================================================
--- kernel/arch/ia64/include/arch/drivers/it.h	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/ia64/include/arch/drivers/it.h	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -27,5 +27,5 @@
  */
 
-/** @addtogroup ia64	
+/** @addtogroup ia64
  * @{
  */
Index: kernel/arch/ia64/include/arch/drivers/kbd.h
===================================================================
--- kernel/arch/ia64/include/arch/drivers/kbd.h	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/ia64/include/arch/drivers/kbd.h	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -27,5 +27,5 @@
  */
 
-/** @addtogroup ia6464	
+/** @addtogroup ia6464
  * @{
  */
Index: kernel/arch/ia64/include/arch/fpu_context.h
===================================================================
--- kernel/arch/ia64/include/arch/fpu_context.h	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/ia64/include/arch/fpu_context.h	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -27,5 +27,5 @@
  */
 
-/** @addtogroup ia64	
+/** @addtogroup ia64
  * @{
  */
Index: kernel/arch/ia64/include/arch/interrupt.h
===================================================================
--- kernel/arch/ia64/include/arch/interrupt.h	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/ia64/include/arch/interrupt.h	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -58,5 +58,5 @@
 #define INR_COUNT  256
 
-#define IVT_ITEMS  128 
+#define IVT_ITEMS  128
 #define IVT_FIRST  0
 
Index: kernel/arch/ia64/include/arch/istate_struct.ag
===================================================================
--- kernel/arch/ia64/include/arch/istate_struct.ag	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/ia64/include/arch/istate_struct.ag	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -1,3 +1,3 @@
-# Copyright (c) 2014 Jakub Jermar 
+# Copyright (c) 2014 Jakub Jermar
 # All rights reserved.
 #
Index: kernel/arch/ia64/include/arch/legacyio.h
===================================================================
--- kernel/arch/ia64/include/arch/legacyio.h	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/ia64/include/arch/legacyio.h	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -41,5 +41,5 @@
 
 /* Legacy I/O space - static uspace address, FIXME */
-#define LEGACYIO_USER_BASE	0x0001000000000000ULL 
+#define LEGACYIO_USER_BASE	0x0001000000000000ULL
 
 #define LEGACYIO_PAGE_WIDTH		26	/* 64M */
Index: kernel/arch/ia64/include/arch/mm/asid.h
===================================================================
--- kernel/arch/ia64/include/arch/mm/asid.h	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/ia64/include/arch/mm/asid.h	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -27,5 +27,5 @@
  */
 
-/** @addtogroup ia64mm	
+/** @addtogroup ia64mm
  * @{
  */
@@ -48,5 +48,5 @@
  * Number of ia64 RIDs (Region Identifiers) per kernel ASID.
  * Note that some architectures may support more bits,
- * but those extra bits are not used by the kernel. 
+ * but those extra bits are not used by the kernel.
  */
 #define RIDS_PER_ASID		8
Index: kernel/arch/ia64/include/arch/mm/vhpt.h
===================================================================
--- kernel/arch/ia64/include/arch/mm/vhpt.h	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/ia64/include/arch/mm/vhpt.h	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -27,5 +27,5 @@
  */
 
-/** @addtogroup ia64mm	
+/** @addtogroup ia64mm
  * @{
  */
@@ -41,5 +41,5 @@
 uintptr_t vhpt_set_up(void);
 
-static inline vhpt_entry_t tlb_entry_t2vhpt_entry_t(tlb_entry_t tentry) 
+static inline vhpt_entry_t tlb_entry_t2vhpt_entry_t(tlb_entry_t tentry)
 {
 	vhpt_entry_t ventry;
Index: kernel/arch/ia64/include/arch/pal/pal.h
===================================================================
--- kernel/arch/ia64/include/arch/pal/pal.h	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/ia64/include/arch/pal/pal.h	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -27,5 +27,5 @@
  */
 
-/** @addtogroup ia64	
+/** @addtogroup ia64
  * @{
  */
Index: kernel/arch/ia64/include/arch/stack.h
===================================================================
--- kernel/arch/ia64/include/arch/stack.h	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/ia64/include/arch/stack.h	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -27,5 +27,5 @@
  */
 
-/** @addtogroup ia64	
+/** @addtogroup ia64
  * @{
  */
Index: kernel/arch/ia64/src/asm.S
===================================================================
--- kernel/arch/ia64/src/asm.S	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/ia64/src/asm.S	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -65,5 +65,5 @@
 	1:
 	
-		add r14 = r16, in1 
+		add r14 = r16, in1
 		add r15 = r16, in0
 		adds r17 = 1, r17 ;;
@@ -113,5 +113,5 @@
 		add in0 = r14, in0
 		adds r15 = -1, r15
-		add r17 = r14, in1 
+		add r17 = r14, in1
 		(p6) br.cond.dpnt 2b ;;
 		mov ar.lc = r15
Index: kernel/arch/ia64/src/context.S
===================================================================
--- kernel/arch/ia64/src/context.S	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/ia64/src/context.S	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -44,5 +44,5 @@
 	 */
 	flushrs
-	mov loc4 = ar.bsp	
+	mov loc4 = ar.bsp
 	
 	/*
@@ -240,5 +240,5 @@
 	ld8 loc6 = [loc15]	/* load ar.lc */
 	
-	.auto	
+	.auto
 
 	/*
@@ -286,5 +286,5 @@
 	ld8.fill r13 = [loc22] ;;
 
-	/* 
+	/*
 	 * Restore branch registers
 	 */
Index: kernel/arch/ia64/src/fpu_context.c
===================================================================
--- kernel/arch/ia64/src/fpu_context.c	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/ia64/src/fpu_context.c	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -27,5 +27,5 @@
  */
 
-/** @addtogroup ia64	
+/** @addtogroup ia64
  * @{
  */
@@ -71,5 +71,5 @@
 		"stf.spill %[f60] = f60\n"
 		"stf.spill %[f61] = f61\n"
-		: 
+		:
 		[f32] "=m" (fctx->fr[0]),
 		[f33] "=m" (fctx->fr[1]),
@@ -102,5 +102,5 @@
 		[f60] "=m" (fctx->fr[28]),
 		[f61] "=m" (fctx->fr[29])
-	); 
+	);
 	
 	asm volatile (
@@ -313,5 +313,5 @@
 		[f60] "m" (fctx->fr[28]),
 		[f61] "m" (fctx->fr[29])
-	); 
+	);
 	
 	asm volatile (
Index: kernel/arch/ia64/src/ia64.c
===================================================================
--- kernel/arch/ia64/src/ia64.c	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/ia64/src/ia64.c	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -114,5 +114,5 @@
 	myeid = ia64_get_cpu_eid();
 
-	for (i = 0; i < 16; i++) { 
+	for (i = 0; i < 16; i++) {
 		if (i == 2)
 			continue;	 /* Disable Cascade interrupt */
@@ -140,5 +140,5 @@
 		irq_init(INR_COUNT, INR_COUNT);
 	}
-	it_init();	
+	it_init();
 }
 
Index: kernel/arch/ia64/src/interrupt.c
===================================================================
--- kernel/arch/ia64/src/interrupt.c	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/ia64/src/interrupt.c	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -320,5 +320,5 @@
 	    vector_to_string(EXC_INST_A_BIT_FAULT), true,
 	    instruction_access_bit_fault);
-	exc_register(EXC_DATA_A_BIT_FAULT, 
+	exc_register(EXC_DATA_A_BIT_FAULT,
 	    vector_to_string(EXC_DATA_A_BIT_FAULT), true,
 	    data_access_bit_fault);
Index: kernel/arch/ia64/src/ivt.S
===================================================================
--- kernel/arch/ia64/src/ivt.S	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/ia64/src/ivt.S	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -48,5 +48,5 @@
 
 /* Speculation vector handler */
-.macro SPECULATION_VECTOR_HANDLER vector 
+.macro SPECULATION_VECTOR_HANDLER vector
     .org ivt + \vector * 0x100
 
@@ -111,5 +111,5 @@
 	/* Set up FPU as in interrupted context. */
 	mov r24 = psr
-	mov r25 = cr.ipsr 
+	mov r25 = cr.ipsr
 	mov r26 = PSR_DFH_MASK
 	mov r27 = ~PSR_DFH_MASK ;;
@@ -175,5 +175,5 @@
 (p6)	st8 [r31] = r38, -STACK_ITEM_SIZE ;;	/* save in6 */
 (p6)	st8 [r31] = r37, -STACK_ITEM_SIZE ;;	/* save in5 */
-(p6)	st8 [r31] = r36, -STACK_ITEM_SIZE ;;	/* save in4 */	
+(p6)	st8 [r31] = r36, -STACK_ITEM_SIZE ;;	/* save in4 */
 (p6)	st8 [r31] = r35, -STACK_ITEM_SIZE ;;	/* save in3 */
 (p6) 	st8 [r31] = r34, -STACK_ITEM_SIZE ;;	/* save in2 */
@@ -182,5 +182,5 @@
 (p5)	add r31 = -(7 * STACK_ITEM_SIZE), r31 ;;
     
-	st8 [r31] = r30, -STACK_ITEM_SIZE ;;	/* save old stack pointer */ 
+	st8 [r31] = r30, -STACK_ITEM_SIZE ;;	/* save old stack pointer */
 	
 	st8 [r31] = r29, -STACK_ITEM_SIZE ;;	/* save predicate registers */
@@ -250,5 +250,5 @@
 	mov r24 = ar.rsc ;;
 	and r30 = ~3, r24 ;;
-	or  r24 = r30 , r27 ;;     
+	or  r24 = r30 , r27 ;;
 	mov ar.rsc = r24 ;;		/* place RSE in enforced lazy mode */
 
@@ -264,10 +264,10 @@
 
 	mov ar.pfs = r25		/* (step 6) */
-	mov cr.ifs = r26	
+	mov cr.ifs = r26
 
 	mov ar.rsc = r24		/* (step 7) */
 
     /* 17. restore interruption state from memory stack */
-	ld8 r28 = [r31], +STACK_ITEM_SIZE ;;	/* load cr.ifa */		
+	ld8 r28 = [r31], +STACK_ITEM_SIZE ;;	/* load cr.ifa */
 	ld8 r27 = [r31], +STACK_ITEM_SIZE ;;	/* load cr.isr */
 	ld8 r26 = [r31], +STACK_ITEM_SIZE ;;	/* load cr.iipa */
@@ -294,5 +294,5 @@
 	
     /* 19. return from interruption */
-    	ld8 r12 = [r31]				/* load stack pointer */ 
+    	ld8 r12 = [r31]				/* load stack pointer */
 	rfi ;;
 
@@ -391,5 +391,5 @@
 	stf.spill [r31] = f15, 8 * FLOAT_ITEM_SIZE ;;
 
-	stf.spill [r24] = f16, 8 * FLOAT_ITEM_SIZE 
+	stf.spill [r24] = f16, 8 * FLOAT_ITEM_SIZE
 	stf.spill [r25] = f17, 8 * FLOAT_ITEM_SIZE
 	stf.spill [r26] = f18, 8 * FLOAT_ITEM_SIZE
@@ -503,5 +503,5 @@
 	mov r24 = loc39
 	mov r25 = loc40
-	mov r26 = loc41 
+	mov r26 = loc41
 	mov r27 = loc42
 	mov r28 = loc43
@@ -575,5 +575,5 @@
 	HEAVYWEIGHT_HANDLER 0x5b
 	HEAVYWEIGHT_HANDLER 0x5c
-	HEAVYWEIGHT_HANDLER 0x5d 
+	HEAVYWEIGHT_HANDLER 0x5d
 	HEAVYWEIGHT_HANDLER 0x5e
 	HEAVYWEIGHT_HANDLER 0x5f
Index: kernel/arch/ia64/src/mm/km.c
===================================================================
--- kernel/arch/ia64/src/mm/km.c	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/ia64/src/mm/km.c	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -40,5 +40,5 @@
 {
 	config.identity_base = KM_IA64_IDENTITY_START;
-	config.identity_size = KM_IA64_IDENTITY_SIZE;	
+	config.identity_size = KM_IA64_IDENTITY_SIZE;
 }
 
Index: kernel/arch/ia64/src/mm/page.c
===================================================================
--- kernel/arch/ia64/src/mm/page.c	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/ia64/src/mm/page.c	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -85,5 +85,5 @@
 	}
 
-#ifdef CONFIG_VHPT	
+#ifdef CONFIG_VHPT
 	vhpt_base = vhpt_set_up();
 #endif
@@ -193,5 +193,5 @@
 	srlz_d();
 
-	return match;		
+	return match;
 }
 
@@ -247,5 +247,5 @@
 	v->present.pl = (flags & PAGE_USER) ? PL_USER : PL_KERNEL;
 	v->present.ar = (flags & PAGE_WRITE) ? AR_WRITE : AR_READ;
-	v->present.ar |= (flags & PAGE_EXEC) ? AR_EXECUTE : 0; 
+	v->present.ar |= (flags & PAGE_EXEC) ? AR_EXECUTE : 0;
 	v->present.ppn = frame >> PPN_SHIFT;
 	v->present.ed = false;  /* exception not deffered */
Index: kernel/arch/ia64/src/mm/tlb.c
===================================================================
--- kernel/arch/ia64/src/mm/tlb.c	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/ia64/src/mm/tlb.c	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -593,5 +593,5 @@
 		if (va < end_of_identity) {
 			/*
-			 * Create kernel identity mapping for low memory. 
+			 * Create kernel identity mapping for low memory.
 			 */
 			dtlb_kernel_mapping_insert(va, KA2PA(va), false, 0);
Index: kernel/arch/ia64/src/start.S
===================================================================
--- kernel/arch/ia64/src/start.S	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/ia64/src/start.S	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -122,7 +122,7 @@
 	# (i.e. location of interruption vector table)
 	#
-	movl r8 = ivt ;; 
+	movl r8 = ivt ;;
 	mov cr.iva = r8
-	srlz.d ;;	
+	srlz.d ;;
 
 	
Index: kernel/arch/mips32/include/arch/cache.h
===================================================================
--- kernel/arch/mips32/include/arch/cache.h	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/mips32/include/arch/cache.h	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -27,5 +27,5 @@
  */
 
-/** @addtogroup mips32	
+/** @addtogroup mips32
  * @{
  */
Index: kernel/arch/mips32/include/arch/context_struct.ag
===================================================================
--- kernel/arch/mips32/include/arch/context_struct.ag	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/mips32/include/arch/context_struct.ag	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -1,3 +1,3 @@
-# Copyright (c) 2014 Jakub Jermar 
+# Copyright (c) 2014 Jakub Jermar
 # All rights reserved.
 #
Index: kernel/arch/mips32/include/arch/fpu_context.h
===================================================================
--- kernel/arch/mips32/include/arch/fpu_context.h	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/mips32/include/arch/fpu_context.h	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -27,5 +27,5 @@
  */
 
-/** @addtogroup mips32	
+/** @addtogroup mips32
  * @{
  */
Index: kernel/arch/mips32/include/arch/fpu_context_struct.ag
===================================================================
--- kernel/arch/mips32/include/arch/fpu_context_struct.ag	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/mips32/include/arch/fpu_context_struct.ag	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -1,3 +1,3 @@
-# Copyright (c) 2014 Jakub Jermar 
+# Copyright (c) 2014 Jakub Jermar
 # All rights reserved.
 #
Index: kernel/arch/mips32/include/arch/istate_struct.ag
===================================================================
--- kernel/arch/mips32/include/arch/istate_struct.ag	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/mips32/include/arch/istate_struct.ag	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -1,3 +1,3 @@
-# Copyright (c) 2014 Jakub Jermar 
+# Copyright (c) 2014 Jakub Jermar
 # All rights reserved.
 #
Index: kernel/arch/mips32/include/arch/mach/malta/malta.h
===================================================================
--- kernel/arch/mips32/include/arch/mach/malta/malta.h	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/mips32/include/arch/mach/malta/malta.h	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -1,4 +1,4 @@
 /*
- * Copyright (c) 2013 Jakub Jermar 
+ * Copyright (c) 2013 Jakub Jermar
  * All rights reserved.
  *
@@ -27,5 +27,5 @@
  */
 
-/** @addtogroup mips32 
+/** @addtogroup mips32
  * @{
  */
Index: kernel/arch/mips32/include/arch/mach/msim/msim.h
===================================================================
--- kernel/arch/mips32/include/arch/mach/msim/msim.h	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/mips32/include/arch/mach/msim/msim.h	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -1,4 +1,4 @@
 /*
- * Copyright (c) 2013 Jakub Jermar 
+ * Copyright (c) 2013 Jakub Jermar
  * All rights reserved.
  *
@@ -27,5 +27,5 @@
  */
 
-/** @addtogroup mips32 
+/** @addtogroup mips32
  * @{
  */
Index: kernel/arch/mips32/include/arch/mm/asid.h
===================================================================
--- kernel/arch/mips32/include/arch/mm/asid.h	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/mips32/include/arch/mm/asid.h	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -27,5 +27,5 @@
  */
 
-/** @addtogroup mips32mm	
+/** @addtogroup mips32mm
  * @{
  */
Index: kernel/arch/mips32/include/arch/mm/page.h
===================================================================
--- kernel/arch/mips32/include/arch/mm/page.h	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/mips32/include/arch/mm/page.h	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -52,5 +52,5 @@
 /*
  * Implementation of generic 4-level page table interface.
- * 
+ *
  * Page table layout:
  * - 32-bit virtual addresses
Index: kernel/arch/mips32/include/arch/mm/tlb.h
===================================================================
--- kernel/arch/mips32/include/arch/mm/tlb.h	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/mips32/include/arch/mm/tlb.h	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -52,5 +52,5 @@
 #endif
 
-#define TLB_WIRED              	0 
+#define TLB_WIRED              	0
 
 #define TLB_PAGE_MASK_4K    (0x000 << 13)
Index: kernel/arch/mips32/src/cpu/cpu.c
===================================================================
--- kernel/arch/mips32/src/cpu/cpu.c	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/mips32/src/cpu/cpu.c	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -125,5 +125,5 @@
 
 	printf("cpu%u: %s %s (rev=%d.%d, imp=%d)\n",
-		m->id, data->vendor, data->model, m->arch.rev_num >> 4, 
+		m->id, data->vendor, data->model, m->arch.rev_num >> 4,
 		m->arch.rev_num & 0x0f, m->arch.imp_num);
 }
Index: kernel/arch/mips32/src/debug/stacktrace.c
===================================================================
--- kernel/arch/mips32/src/debug/stacktrace.c	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/mips32/src/debug/stacktrace.c	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -36,5 +36,5 @@
  * This stack tracing code is based on the suggested algorithm described on page
  * 3-27 and 3-28 of:
- * 
+ *
  * SYSTEM V
  * APPLICATION BINARY INTERFACE
@@ -88,5 +88,5 @@
 #define BASE_MASK	RS_MASK
 #define IMM_MASK	(0xffff << IMM_SHIFT)
-#define OFFSET_MASK	IMM_MASK	
+#define OFFSET_MASK	IMM_MASK
 
 #define RS_GET(inst)		(((inst) & RS_MASK) >> RS_SHIFT)
@@ -94,5 +94,5 @@
 #define IMM_GET(inst)		(int16_t)(((inst) & IMM_MASK) >> IMM_SHIFT)
 #define BASE_GET(inst)		RS_GET(inst)
-#define OFFSET_GET(inst)	IMM_GET(inst)	
+#define OFFSET_GET(inst)	IMM_GET(inst)
 
 #define ADDU_R_SP_R0_TEMPL \
Index: kernel/arch/mips32/src/debugger.c
===================================================================
--- kernel/arch/mips32/src/debugger.c	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/mips32/src/debugger.c	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -386,5 +386,5 @@
 			((uint32_t *)cur->address)[1] = 0x0d;
 			cur->flags |= BKPOINT_REINST;
-		} 
+		}
 		cur->flags |= BKPOINT_INPROG;
 	} else {
Index: kernel/arch/mips32/src/exception.c
===================================================================
--- kernel/arch/mips32/src/exception.c	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/mips32/src/exception.c	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -132,5 +132,5 @@
 	debugger_bpoint(istate);
 #else
-	/* it is necessary to not re-execute BREAK instruction after 
+	/* it is necessary to not re-execute BREAK instruction after
 	   returning from Exception handler
 	   (see page 138 in R4000 Manual for more information) */
Index: kernel/arch/mips32/src/mach/malta/malta.c
===================================================================
--- kernel/arch/mips32/src/mach/malta/malta.c	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/mips32/src/mach/malta/malta.c	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -27,5 +27,5 @@
  */
 
-/** @addtogroup mips32 
+/** @addtogroup mips32
  * @{
  */
@@ -54,5 +54,5 @@
 	.machine_output_init = malta_output_init,
 	.machine_input_init = malta_input_init,
-	.machine_get_platform_name = malta_get_platform_name	
+	.machine_get_platform_name = malta_get_platform_name
 };
 
Index: kernel/arch/mips32/src/mach/msim/msim.c
===================================================================
--- kernel/arch/mips32/src/mach/msim/msim.c	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/mips32/src/mach/msim/msim.c	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -27,5 +27,5 @@
  */
 
-/** @addtogroup mips32 
+/** @addtogroup mips32
  * @{
  */
@@ -57,5 +57,5 @@
 	.machine_output_init = msim_output_init,
 	.machine_input_init = msim_input_init,
-	.machine_get_platform_name = msim_get_platform_name	
+	.machine_get_platform_name = msim_get_platform_name
 };
 
Index: kernel/arch/mips32/src/mm/frame.c
===================================================================
--- kernel/arch/mips32/src/mm/frame.c	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/mips32/src/mm/frame.c	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -141,5 +141,5 @@
 
 	if (!frame_adjust_zone_bounds(low, &base, &size))
-		return; 
+		return;
 
 	pfn_t first = ADDR2PFN(base);
@@ -291,5 +291,5 @@
 		printf("%#010x %10u\n",
 			PFN2ADDR(phys_regions[i].start), PFN2ADDR(phys_regions[i].count));
-	}	
+	}
 }
 
Index: kernel/arch/mips32/src/mm/tlb.c
===================================================================
--- kernel/arch/mips32/src/mm/tlb.c	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/mips32/src/mm/tlb.c	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -219,5 +219,5 @@
 	 * We do not assert on this because this could be a manifestation of
 	 * an emulator bug, such as QEMU Bug #1128935:
-	 * https://bugs.launchpad.net/qemu/+bug/1128935  
+	 * https://bugs.launchpad.net/qemu/+bug/1128935
 	 */
 	if (index.p) {
Index: kernel/arch/ppc32/include/arch/context_struct.ag
===================================================================
--- kernel/arch/ppc32/include/arch/context_struct.ag	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/ppc32/include/arch/context_struct.ag	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -1,3 +1,3 @@
-# Copyright (c) 2014 Jakub Jermar 
+# Copyright (c) 2014 Jakub Jermar
 # All rights reserved.
 #
Index: kernel/arch/ppc32/include/arch/fpu_context.h
===================================================================
--- kernel/arch/ppc32/include/arch/fpu_context.h	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/ppc32/include/arch/fpu_context.h	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -36,5 +36,5 @@
 #define KERN_ppc32_FPU_CONTEXT_H_
 
-#define FPU_CONTEXT_ALIGN	8	
+#define FPU_CONTEXT_ALIGN	8
 
 #include <arch/fpu_context_struct.h>
Index: kernel/arch/ppc32/include/arch/fpu_context_struct.ag
===================================================================
--- kernel/arch/ppc32/include/arch/fpu_context_struct.ag	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/ppc32/include/arch/fpu_context_struct.ag	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -1,3 +1,3 @@
-# Copyright (c) 2014 Jakub Jermar 
+# Copyright (c) 2014 Jakub Jermar
 # All rights reserved.
 #
Index: kernel/arch/ppc32/include/arch/istate_struct.ag
===================================================================
--- kernel/arch/ppc32/include/arch/istate_struct.ag	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/ppc32/include/arch/istate_struct.ag	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -1,3 +1,3 @@
-# Copyright (c) 2014 Jakub Jermar 
+# Copyright (c) 2014 Jakub Jermar
 # All rights reserved.
 #
Index: kernel/arch/ppc32/src/drivers/pic.c
===================================================================
--- kernel/arch/ppc32/src/drivers/pic.c	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/ppc32/src/drivers/pic.c	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -71,5 +71,5 @@
 {
 	if (pic) {
-		if (intnum < 32) 
+		if (intnum < 32)
 			pic[PIC_ACK_LOW] = 1 << intnum;
 		else
Index: kernel/arch/ppc32/src/exception.S
===================================================================
--- kernel/arch/ppc32/src/exception.S	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/ppc32/src/exception.S	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -49,5 +49,5 @@
 	
 	mfsrr1 sp # use sp as a temporary register to hold SRR1
-	andi. sp, sp, MSR_PR 
+	andi. sp, sp, MSR_PR
 	bne 1f
 		# previous mode was kernel
Index: kernel/arch/ppc32/src/ppc32.c
===================================================================
--- kernel/arch/ppc32/src/ppc32.c	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/ppc32/src/ppc32.c	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -123,5 +123,5 @@
 	cpu_node = cpus_node->child;
 	if (!cpu_node)
-		panic("Could not find first cpu.");	
+		panic("Could not find first cpu.");
 
 	freq_prop = ofw_tree_getprop(cpu_node, "timebase-frequency");
Index: kernel/arch/sparc64/include/arch/console.h
===================================================================
--- kernel/arch/sparc64/include/arch/console.h	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/sparc64/include/arch/console.h	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -27,5 +27,5 @@
  */
 
-/** @addtogroup sparc64	
+/** @addtogroup sparc64
  * @{
  */
Index: kernel/arch/sparc64/include/arch/context_struct.ag
===================================================================
--- kernel/arch/sparc64/include/arch/context_struct.ag	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/sparc64/include/arch/context_struct.ag	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -1,3 +1,3 @@
-# Copyright (c) 2014 Jakub Jermar 
+# Copyright (c) 2014 Jakub Jermar
 # All rights reserved.
 #
Index: kernel/arch/sparc64/include/arch/cpu.h
===================================================================
--- kernel/arch/sparc64/include/arch/cpu.h	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/sparc64/include/arch/cpu.h	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -65,5 +65,5 @@
 
 
-#endif	
+#endif
 
 #endif
Index: kernel/arch/sparc64/include/arch/cpu_family.h
===================================================================
--- kernel/arch/sparc64/include/arch/cpu_family.h	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/sparc64/include/arch/cpu_family.h	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -43,5 +43,5 @@
 /**
  * Find the processor (sub)family.
- * 
+ *
  * @return 	true iff the CPU belongs to the US family
  */
@@ -55,5 +55,5 @@
 /**
  * Find the processor (sub)family.
- * 
+ *
  * @return 	true iff the CPU belongs to the US-III subfamily
  */
@@ -68,5 +68,5 @@
 /**
  * Find the processor (sub)family.
- * 
+ *
  * @return 	true iff the CPU belongs to the US-IV subfamily
  */
Index: kernel/arch/sparc64/include/arch/cpu_node.h
===================================================================
--- kernel/arch/sparc64/include/arch/cpu_node.h	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/sparc64/include/arch/cpu_node.h	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -43,5 +43,5 @@
  *  Depending on the machine type (and possibly the OFW version), CPUs can be
  *  at "/" or at "/ssm@0,0".
- */ 
+ */
 static inline ofw_tree_node_t *cpus_parent(void)
 {
Index: kernel/arch/sparc64/include/arch/drivers/fb.h
===================================================================
--- kernel/arch/sparc64/include/arch/drivers/fb.h	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/sparc64/include/arch/drivers/fb.h	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -27,5 +27,5 @@
  */
 
-/** @addtogroup sparc64	
+/** @addtogroup sparc64
  * @{
  */
Index: kernel/arch/sparc64/include/arch/drivers/niagara.h
===================================================================
--- kernel/arch/sparc64/include/arch/drivers/niagara.h	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/sparc64/include/arch/drivers/niagara.h	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -27,5 +27,5 @@
  */
 
-/** @addtogroup sparc64	
+/** @addtogroup sparc64
  * @{
  */
Index: kernel/arch/sparc64/include/arch/drivers/pci.h
===================================================================
--- kernel/arch/sparc64/include/arch/drivers/pci.h	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/sparc64/include/arch/drivers/pci.h	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -27,5 +27,5 @@
  */
 
-/** @addtogroup sparc64	
+/** @addtogroup sparc64
  * @{
  */
Index: kernel/arch/sparc64/include/arch/fpu_context.h
===================================================================
--- kernel/arch/sparc64/include/arch/fpu_context.h	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/sparc64/include/arch/fpu_context.h	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -27,5 +27,5 @@
  */
 
-/** @addtogroup sparc64	
+/** @addtogroup sparc64
  * @{
  */
Index: kernel/arch/sparc64/include/arch/interrupt.h
===================================================================
--- kernel/arch/sparc64/include/arch/interrupt.h	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/sparc64/include/arch/interrupt.h	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -40,5 +40,5 @@
 
 #define IVT_ITEMS  512
-#define IVT_FIRST  0 
+#define IVT_FIRST  0
 
 /* This needs to be defined for inter-architecture API portability. */
Index: kernel/arch/sparc64/include/arch/istate_struct.ag
===================================================================
--- kernel/arch/sparc64/include/arch/istate_struct.ag	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/sparc64/include/arch/istate_struct.ag	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -1,3 +1,3 @@
-# Copyright (c) 2014 Jakub Jermar 
+# Copyright (c) 2014 Jakub Jermar
 # All rights reserved.
 #
Index: kernel/arch/sparc64/include/arch/mm/asid.h
===================================================================
--- kernel/arch/sparc64/include/arch/mm/asid.h	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/sparc64/include/arch/mm/asid.h	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -27,5 +27,5 @@
  */
 
-/** @addtogroup sparc64mm	
+/** @addtogroup sparc64mm
  * @{
  */
Index: kernel/arch/sparc64/include/arch/mm/mmu.h
===================================================================
--- kernel/arch/sparc64/include/arch/mm/mmu.h	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/sparc64/include/arch/mm/mmu.h	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -27,5 +27,5 @@
  */
 
-/** @addtogroup sparc64mm	
+/** @addtogroup sparc64mm
  * @{
  */
Index: kernel/arch/sparc64/include/arch/mm/page.h
===================================================================
--- kernel/arch/sparc64/include/arch/mm/page.h	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/sparc64/include/arch/mm/page.h	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -27,5 +27,5 @@
  */
 
-/** @addtogroup sparc64mm	
+/** @addtogroup sparc64mm
  * @{
  */
Index: kernel/arch/sparc64/include/arch/mm/pagesize.h
===================================================================
--- kernel/arch/sparc64/include/arch/mm/pagesize.h	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/sparc64/include/arch/mm/pagesize.h	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -28,5 +28,5 @@
  */
 
-/** @addtogroup sparc64mm	
+/** @addtogroup sparc64mm
  * @{
  */
Index: kernel/arch/sparc64/include/arch/mm/sun4u/mmu.h
===================================================================
--- kernel/arch/sparc64/include/arch/mm/sun4u/mmu.h	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/sparc64/include/arch/mm/sun4u/mmu.h	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -27,5 +27,5 @@
  */
 
-/** @addtogroup sparc64mm	
+/** @addtogroup sparc64mm
  * @{
  */
@@ -43,5 +43,5 @@
 /* I-MMU ASIs. */
 #define ASI_IMMU			0x50
-#define ASI_IMMU_TSB_8KB_PTR_REG	0x51	
+#define ASI_IMMU_TSB_8KB_PTR_REG	0x51
 #define ASI_IMMU_TSB_64KB_PTR_REG	0x52
 #define ASI_ITLB_DATA_IN_REG		0x54
@@ -63,5 +63,5 @@
 /* D-MMU ASIs. */
 #define ASI_DMMU			0x58
-#define ASI_DMMU_TSB_8KB_PTR_REG	0x59	
+#define ASI_DMMU_TSB_8KB_PTR_REG	0x59
 #define ASI_DMMU_TSB_64KB_PTR_REG	0x5a
 #define ASI_DMMU_TSB_DIRECT_PTR_REG	0x5b
@@ -106,5 +106,5 @@
 		unsigned vw : 1;
 		unsigned : 1;
-		unsigned fm : 16;	
+		unsigned fm : 16;
 		unsigned dm : 1;	/**< D-MMU enable. */
 		unsigned im : 1;	/**< I-MMU enable. */
Index: kernel/arch/sparc64/include/arch/mm/sun4u/tlb.h
===================================================================
--- kernel/arch/sparc64/include/arch/mm/sun4u/tlb.h	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/sparc64/include/arch/mm/sun4u/tlb.h	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -27,5 +27,5 @@
  */
 
-/** @addtogroup sparc64mm	
+/** @addtogroup sparc64mm
  * @{
  */
@@ -143,5 +143,5 @@
  * behind this is to prevent careless mistakes in the code
  * caused by setting only the entry number and not the TLB
- * number in the US3 code (when taking the code from US). 
+ * number in the US3 code (when taking the code from US).
  */
 
@@ -241,5 +241,5 @@
 
 /**
- * Determine the number of entries in the DMMU's small TLB. 
+ * Determine the number of entries in the DMMU's small TLB.
  */
 NO_TRACE static inline uint16_t tlb_dsmall_size(void)
@@ -249,5 +249,5 @@
 
 /**
- * Determine the number of entries in each DMMU's big TLB. 
+ * Determine the number of entries in each DMMU's big TLB.
  */
 NO_TRACE static inline uint16_t tlb_dbig_size(void)
@@ -257,5 +257,5 @@
 
 /**
- * Determine the number of entries in the IMMU's small TLB. 
+ * Determine the number of entries in the IMMU's small TLB.
  */
 NO_TRACE static inline uint16_t tlb_ismall_size(void)
@@ -265,5 +265,5 @@
 
 /**
- * Determine the number of entries in the IMMU's big TLB. 
+ * Determine the number of entries in the IMMU's big TLB.
  */
 NO_TRACE static inline uint16_t tlb_ibig_size(void)
@@ -449,5 +449,5 @@
 /** Read DMMU TLB Data Access Register.
  *
- * @param tlb		TLB number (one of TLB_DSMALL, TLB_DBIG, TLB_DBIG) 
+ * @param tlb		TLB number (one of TLB_DSMALL, TLB_DBIG, TLB_DBIG)
  * @param entry		TLB Entry index.
  *
@@ -467,5 +467,5 @@
 /** Write DMMU TLB Data Access Register.
  *
- * @param tlb		TLB number (one of TLB_DSMALL, TLB_DBIG_0, TLB_DBIG_1)  
+ * @param tlb		TLB number (one of TLB_DSMALL, TLB_DBIG_0, TLB_DBIG_1)
  * @param entry		TLB Entry index.
  * @param value		Value to be written.
@@ -485,5 +485,5 @@
 /** Read IMMU TLB Tag Read Register.
  *
- * @param tlb		TLB number (one of TLB_ISMALL or TLB_IBIG) 
+ * @param tlb		TLB number (one of TLB_ISMALL or TLB_IBIG)
  * @param entry		TLB Entry index.
  *
@@ -646,5 +646,5 @@
 	da.vpn = pg.vpn;
 	
-	/* da.value is the address within the ASI */ 
+	/* da.value is the address within the ASI */
 	asi_u64_write(ASI_IMMU_DEMAP, da.value, 0);
 
@@ -672,5 +672,5 @@
 	da.vpn = pg.vpn;
 	
-	/* da.value is the address within the ASI */ 
+	/* da.value is the address within the ASI */
 	asi_u64_write(ASI_DMMU_DEMAP, da.value, 0);
 
Index: kernel/arch/sparc64/include/arch/mm/sun4u/tsb.h
===================================================================
--- kernel/arch/sparc64/include/arch/mm/sun4u/tsb.h	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/sparc64/include/arch/mm/sun4u/tsb.h	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -27,5 +27,5 @@
  */
 
-/** @addtogroup sparc64mm	
+/** @addtogroup sparc64mm
  * @{
  */
Index: kernel/arch/sparc64/include/arch/mm/sun4u/tte.h
===================================================================
--- kernel/arch/sparc64/include/arch/mm/sun4u/tte.h	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/sparc64/include/arch/mm/sun4u/tte.h	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -27,5 +27,5 @@
  */
 
-/** @addtogroup sparc64mm	
+/** @addtogroup sparc64mm
  * @{
  */
Index: kernel/arch/sparc64/include/arch/mm/sun4v/as.h
===================================================================
--- kernel/arch/sparc64/include/arch/mm/sun4v/as.h	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/sparc64/include/arch/mm/sun4v/as.h	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -28,5 +28,5 @@
  */
 
-/** @addtogroup sparc64mm	
+/** @addtogroup sparc64mm
  * @{
  */
@@ -54,5 +54,5 @@
  * Even though for sun4v the format of the TSB Tag states that the context
  * field has 16 bits, the T1 CPU still only supports 13-bit contexts and the
- * three most significant bits are always zero. 
+ * three most significant bits are always zero.
  */
 typedef union tte_tag {
Index: kernel/arch/sparc64/include/arch/mm/sun4v/page.h
===================================================================
--- kernel/arch/sparc64/include/arch/mm/sun4v/page.h	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/sparc64/include/arch/mm/sun4v/page.h	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -27,5 +27,5 @@
  */
 
-/** @addtogroup sparc64mm	
+/** @addtogroup sparc64mm
  * @{
  */
Index: kernel/arch/sparc64/include/arch/mm/tsb.h
===================================================================
--- kernel/arch/sparc64/include/arch/mm/tsb.h	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/sparc64/include/arch/mm/tsb.h	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -27,5 +27,5 @@
  */
 
-/** @addtogroup sparc64mm	
+/** @addtogroup sparc64mm
  * @{
  */
Index: kernel/arch/sparc64/include/arch/mm/tte.h
===================================================================
--- kernel/arch/sparc64/include/arch/mm/tte.h	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/sparc64/include/arch/mm/tte.h	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -27,5 +27,5 @@
  */
 
-/** @addtogroup sparc64mm	
+/** @addtogroup sparc64mm
  * @{
  */
Index: kernel/arch/sparc64/include/arch/regdef.h
===================================================================
--- kernel/arch/sparc64/include/arch/regdef.h	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/sparc64/include/arch/regdef.h	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -27,5 +27,5 @@
  */
 
-/** @addtogroup sparc64	
+/** @addtogroup sparc64
  * @{
  */
@@ -58,5 +58,5 @@
 /*
  * The following definitions concern the UPA_CONFIG register on US and the
- * FIREPLANE_CONFIG register on US3. 
+ * FIREPLANE_CONFIG register on US3.
  */
 #define ICBUS_CONFIG_MID_SHIFT    17
Index: kernel/arch/sparc64/include/arch/register.h
===================================================================
--- kernel/arch/sparc64/include/arch/register.h	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/sparc64/include/arch/register.h	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -27,5 +27,5 @@
  */
 
-/** @addtogroup sparc64	
+/** @addtogroup sparc64
  * @{
  */
@@ -98,5 +98,5 @@
 	uint64_t value;
 	struct {
-		uint64_t : 47; 
+		uint64_t : 47;
 		unsigned stick_int : 1;
 		unsigned int_level : 15;
Index: kernel/arch/sparc64/include/arch/smp/sun4u/ipi.h
===================================================================
--- kernel/arch/sparc64/include/arch/smp/sun4u/ipi.h	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/sparc64/include/arch/smp/sun4u/ipi.h	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -27,5 +27,5 @@
  */
 
-/** @addtogroup sparc64	
+/** @addtogroup sparc64
  * @{
  */
Index: kernel/arch/sparc64/include/arch/smp/sun4v/smp.h
===================================================================
--- kernel/arch/sparc64/include/arch/smp/sun4v/smp.h	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/sparc64/include/arch/smp/sun4v/smp.h	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -27,5 +27,5 @@
  */
 
-/** @addtogroup sparc64	
+/** @addtogroup sparc64
  * @{
  */
Index: kernel/arch/sparc64/include/arch/stack.h
===================================================================
--- kernel/arch/sparc64/include/arch/stack.h	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/sparc64/include/arch/stack.h	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -27,5 +27,5 @@
  */
 
-/** @addtogroup sparc64	
+/** @addtogroup sparc64
  * @{
  */
Index: kernel/arch/sparc64/include/arch/sun4u/arch.h
===================================================================
--- kernel/arch/sparc64/include/arch/sun4u/arch.h	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/sparc64/include/arch/sun4u/arch.h	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -27,5 +27,5 @@
  */
 
-/** @addtogroup sparc64	
+/** @addtogroup sparc64
  * @{
  */
Index: kernel/arch/sparc64/include/arch/sun4v/arch.h
===================================================================
--- kernel/arch/sparc64/include/arch/sun4v/arch.h	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/sparc64/include/arch/sun4v/arch.h	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -27,5 +27,5 @@
  */
 
-/** @addtogroup sparc64	
+/** @addtogroup sparc64
  * @{
  */
@@ -47,5 +47,5 @@
 
 /* register where the address of the MMU fault status area will be stored */
-#define SCRATCHPAD_MMU_FSA	0x00	
+#define SCRATCHPAD_MMU_FSA	0x00
 
 /* register where the CPUID will be stored */
Index: kernel/arch/sparc64/include/arch/sun4v/ipi.h
===================================================================
--- kernel/arch/sparc64/include/arch/sun4v/ipi.h	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/sparc64/include/arch/sun4v/ipi.h	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -27,5 +27,5 @@
  */
 
-/** @addtogroup sparc64	
+/** @addtogroup sparc64
  * @{
  */
Index: kernel/arch/sparc64/include/arch/sun4v/register.h
===================================================================
--- kernel/arch/sparc64/include/arch/sun4v/register.h	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/sparc64/include/arch/sun4v/register.h	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -27,5 +27,5 @@
  */
 
-/** @addtogroup sparc64	
+/** @addtogroup sparc64
  * @{
  */
Index: kernel/arch/sparc64/include/arch/trap/interrupt.h
===================================================================
--- kernel/arch/sparc64/include/arch/trap/interrupt.h	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/sparc64/include/arch/trap/interrupt.h	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -30,5 +30,5 @@
  * @{
  */
-/** 
+/**
  * @file
  * @brief This file contains level N interrupt and inter-processor interrupt
Index: kernel/arch/sparc64/include/arch/trap/regwin.h
===================================================================
--- kernel/arch/sparc64/include/arch/trap/regwin.h	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/sparc64/include/arch/trap/regwin.h	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -84,5 +84,5 @@
  */
 .macro SPILL_NORMAL_HANDLER_KERNEL
-	stx %l0, [%sp + STACK_BIAS + L0_OFFSET]	
+	stx %l0, [%sp + STACK_BIAS + L0_OFFSET]
 	stx %l1, [%sp + STACK_BIAS + L1_OFFSET]
 	stx %l2, [%sp + STACK_BIAS + L2_OFFSET]
Index: kernel/arch/sparc64/include/arch/trap/sun4u/interrupt.h
===================================================================
--- kernel/arch/sparc64/include/arch/trap/sun4u/interrupt.h	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/sparc64/include/arch/trap/sun4u/interrupt.h	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -30,5 +30,5 @@
  * @{
  */
-/** 
+/**
  * @file
  * @brief This file contains interrupt vector trap handler.
Index: kernel/arch/sparc64/include/arch/trap/sun4u/mmu.h
===================================================================
--- kernel/arch/sparc64/include/arch/trap/sun4u/mmu.h	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/sparc64/include/arch/trap/sun4u/mmu.h	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -77,5 +77,5 @@
 	mov VA_IMMU_TAG_ACCESS, %g5
 	ldxa [%g5] ASI_IMMU, %g5			! read the faulting Context and VPN
-	PREEMPTIBLE_HANDLER exc_dispatch 
+	PREEMPTIBLE_HANDLER exc_dispatch
 .endm
 
@@ -143,5 +143,5 @@
 	mov TT_FAST_DATA_ACCESS_MMU_MISS, %g2
 	ldxa [VA_DMMU_TAG_ACCESS] %asi, %g5		! read the faulting Context and VPN
-	PREEMPTIBLE_HANDLER exc_dispatch 
+	PREEMPTIBLE_HANDLER exc_dispatch
 .endm
 
@@ -163,5 +163,5 @@
 	mov VA_DMMU_TAG_ACCESS, %g5
 	ldxa [%g5] ASI_DMMU, %g5			! read the faulting Context and VPN
-	PREEMPTIBLE_HANDLER exc_dispatch 
+	PREEMPTIBLE_HANDLER exc_dispatch
 .endm
 
Index: kernel/arch/sparc64/include/arch/trap/sun4u/regwin.h
===================================================================
--- kernel/arch/sparc64/include/arch/trap/sun4u/regwin.h	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/sparc64/include/arch/trap/sun4u/regwin.h	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -42,5 +42,5 @@
  */
 .macro SPILL_TO_USPACE_WINDOW_BUFFER
-	stx %l0, [%g7 + L0_OFFSET]	
+	stx %l0, [%g7 + L0_OFFSET]
 	stx %l1, [%g7 + L1_OFFSET]
 	stx %l2, [%g7 + L2_OFFSET]
Index: kernel/arch/sparc64/include/arch/trap/sun4v/interrupt.h
===================================================================
--- kernel/arch/sparc64/include/arch/trap/sun4v/interrupt.h	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/sparc64/include/arch/trap/sun4v/interrupt.h	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -30,5 +30,5 @@
  * @{
  */
-/** 
+/**
  * @file
  * @brief This file contains interrupt vector trap handler.
Index: kernel/arch/sparc64/include/arch/trap/sun4v/mmu.h
===================================================================
--- kernel/arch/sparc64/include/arch/trap/sun4v/mmu.h	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/sparc64/include/arch/trap/sun4v/mmu.h	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -75,5 +75,5 @@
 	mov TT_FAST_INSTRUCTION_ACCESS_MMU_MISS, %g2
 	clr %g5		! XXX
-	PREEMPTIBLE_HANDLER exc_dispatch 
+	PREEMPTIBLE_HANDLER exc_dispatch
 .endm
 
@@ -179,5 +179,5 @@
 	or %g1, %g3, %g5
 
-	PREEMPTIBLE_HANDLER exc_dispatch 
+	PREEMPTIBLE_HANDLER exc_dispatch
 .endm
 #endif /* __ASM__ */
Index: kernel/arch/sparc64/include/arch/trap/sun4v/regwin.h
===================================================================
--- kernel/arch/sparc64/include/arch/trap/sun4v/regwin.h	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/sparc64/include/arch/trap/sun4v/regwin.h	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -48,5 +48,5 @@
 	set SCRATCHPAD_WBUF, \tmpreg2
 	ldxa [\tmpreg2] ASI_SCRATCHPAD, \tmpreg1
-	stx %l0, [\tmpreg1 + L0_OFFSET]	
+	stx %l0, [\tmpreg1 + L0_OFFSET]
 	stx %l1, [\tmpreg1 + L1_OFFSET]
 	stx %l2, [\tmpreg1 + L2_OFFSET]
Index: kernel/arch/sparc64/src/console.c
===================================================================
--- kernel/arch/sparc64/src/console.c	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/sparc64/src/console.c	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -56,5 +56,5 @@
  * Called on UltraSPARC machines with standard keyboard and framebuffer.
  *
- * @param aliases	the "/aliases" OBP node 
+ * @param aliases	the "/aliases" OBP node
  */
 static void standard_console_init(ofw_tree_node_t *aliases)
@@ -89,5 +89,5 @@
 /**
  * Initialize input/output. Auto-detects the type of machine
- * and calls the appropriate I/O init routine. 
+ * and calls the appropriate I/O init routine.
  */
 void standalone_sparc64_console_init(void)
Index: kernel/arch/sparc64/src/context.S
===================================================================
--- kernel/arch/sparc64/src/context.S	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/sparc64/src/context.S	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -32,5 +32,5 @@
 #include <arch/regdef.h>
 
-.text   
+.text
 
 /*
Index: kernel/arch/sparc64/src/cpu/sun4u/cpu.c
===================================================================
--- kernel/arch/sparc64/src/cpu/sun4u/cpu.c	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/sparc64/src/cpu/sun4u/cpu.c	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -86,9 +86,9 @@
 	 * Detect processor frequency.
 	 */
-	if (is_us() || is_us_iii()) { 
+	if (is_us() || is_us_iii()) {
 		node = ofw_tree_find_child_by_device_type(cpus_parent(), "cpu");
 		while (node) {
 			int f = find_cpu_frequency(node);
-			if (f != -1) 
+			if (f != -1)
 				clock_frequency = (uint32_t) f;
 			node = ofw_tree_find_peer_by_device_type(node, "cpu");
@@ -100,9 +100,9 @@
 			f = find_cpu_frequency(
 				ofw_tree_find_child(node, "cpu@0"));
-			if (f != -1) 
+			if (f != -1)
 				clock_frequency = (uint32_t) f;
 			f = find_cpu_frequency(
 				ofw_tree_find_child(node, "cpu@1"));
-			if (f != -1) 
+			if (f != -1)
 				clock_frequency = (uint32_t) f;
 			node = ofw_tree_find_peer_by_name(node, "cmp");
Index: kernel/arch/sparc64/src/drivers/pci.c
===================================================================
--- kernel/arch/sparc64/src/drivers/pci.c	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/sparc64/src/drivers/pci.c	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -79,5 +79,5 @@
  *
  * @return		Address of the initialized PCI structure.
- */ 
+ */
 pci_t *pci_sabre_init(ofw_tree_node_t *node)
 {
@@ -121,5 +121,5 @@
  *
  * @return		Address of the initialized PCI structure.
- */ 
+ */
 pci_t *pci_psycho_init(ofw_tree_node_t *node)
 {
Index: kernel/arch/sparc64/src/drivers/scr.c
===================================================================
--- kernel/arch/sparc64/src/drivers/scr.c	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/sparc64/src/drivers/scr.c	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -27,5 +27,5 @@
  */
 
-/** @addtogroup sparc64	
+/** @addtogroup sparc64
  * @{
  */
@@ -209,5 +209,5 @@
 		
 		break;
-	case SCR_FFB:	
+	case SCR_FFB:
 		fb_scanline = 8192;
 		visual = VISUAL_BGR_0_8_8_8;
Index: kernel/arch/sparc64/src/mm/sun4u/tlb.c
===================================================================
--- kernel/arch/sparc64/src/mm/sun4u/tlb.c	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/sparc64/src/mm/sun4u/tlb.c	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -322,5 +322,5 @@
 		 * Forward the page fault to the address space page fault
 		 * handler.
-		 */		
+		 */
 		as_page_fault(page_16k, PF_ACCESS_WRITE, istate);
 	}
@@ -330,9 +330,9 @@
  *
  * The diag field has been left out in order to make this function more generic
- * (there is no diag field in US3 architeture). 
- *
- * @param i		TLB entry number 
+ * (there is no diag field in US3 architeture).
+ *
+ * @param i		TLB entry number
  * @param t		TLB entry tag
- * @param d		TLB entry data 
+ * @param d		TLB entry data
  */
 static void print_tlb_entry(int i, tlb_tag_read_reg_t t, tlb_data_t d)
Index: kernel/arch/sparc64/src/mm/sun4v/tlb.c
===================================================================
--- kernel/arch/sparc64/src/mm/sun4v/tlb.c	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/sparc64/src/mm/sun4v/tlb.c	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -282,5 +282,5 @@
 		 * Forward the page fault to the address space page fault
 		 * handler.
-		 */		
+		 */
 		as_page_fault(va, PF_ACCESS_READ, istate);
 	}
@@ -323,5 +323,5 @@
 		 * Forward the page fault to the address space page fault
 		 * handler.
-		 */		
+		 */
 		as_page_fault(va, PF_ACCESS_WRITE, istate);
 	}
Index: kernel/arch/sparc64/src/mm/sun4v/tsb.c
===================================================================
--- kernel/arch/sparc64/src/mm/sun4v/tsb.c	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/sparc64/src/mm/sun4v/tsb.c	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -28,5 +28,5 @@
  */
 
-/** @addtogroup sparc64mm	
+/** @addtogroup sparc64mm
  * @{
  */
@@ -86,5 +86,5 @@
 
 	as = t->as;
-	index = (t->page >> MMU_PAGE_WIDTH) & TSB_ENTRY_MASK; 
+	index = (t->page >> MMU_PAGE_WIDTH) & TSB_ENTRY_MASK;
 	
 	tsb = (tsb_entry_t *) PA2KA(as->arch.tsb_description.tsb_base);
Index: kernel/arch/sparc64/src/smp/sun4u/ipi.c
===================================================================
--- kernel/arch/sparc64/src/smp/sun4u/ipi.c	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/sparc64/src/smp/sun4u/ipi.c	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -27,5 +27,5 @@
  */
 
-/** @addtogroup sparc64	
+/** @addtogroup sparc64
  * @{
  */
@@ -122,5 +122,5 @@
 			/*
 			 * Prevent deadlock.
-			 */			
+			 */
 			(void) interrupts_enable();
 			delay(20 + (tick_read() & 0xff));
@@ -180,5 +180,5 @@
  * Interrupts must be disabled.
  *
- * @param cpu_id Destination cpu id (index into cpus array). Must not 
+ * @param cpu_id Destination cpu id (index into cpus array). Must not
  *               be the current cpu.
  * @param ipi    IPI number.
Index: kernel/arch/sparc64/src/smp/sun4u/smp.c
===================================================================
--- kernel/arch/sparc64/src/smp/sun4u/smp.c	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/sparc64/src/smp/sun4u/smp.c	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -27,5 +27,5 @@
  */
 
-/** @addtogroup sparc64	
+/** @addtogroup sparc64
  * @{
  */
@@ -83,5 +83,5 @@
  * Wakes up the CPU which is represented by the "node" OFW tree node.
  * If "node" represents the current CPU, calling the function has
- * no effect. 
+ * no effect.
  */
 static void wakeup_cpu(ofw_tree_node_t *node)
Index: kernel/arch/sparc64/src/smp/sun4u/smp_call.c
===================================================================
--- kernel/arch/sparc64/src/smp/sun4u/smp_call.c	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/sparc64/src/smp/sun4u/smp_call.c	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -42,5 +42,5 @@
 void arch_smp_call_ipi(unsigned int cpu_id)
 {
-	/* 
+	/*
 	 * Required by ipi_unicast_arch(). That functions resolves a potential
 	 * deadlock should both the destination and source cpus be sending
Index: kernel/arch/sparc64/src/smp/sun4v/ipi.c
===================================================================
--- kernel/arch/sparc64/src/smp/sun4v/ipi.c	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/sparc64/src/smp/sun4v/ipi.c	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -27,5 +27,5 @@
  */
 
-/** @addtogroup sparc64	
+/** @addtogroup sparc64
  * @{
  */
Index: kernel/arch/sparc64/src/smp/sun4v/smp.c
===================================================================
--- kernel/arch/sparc64/src/smp/sun4v/smp.c	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/sparc64/src/smp/sun4v/smp.c	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -254,5 +254,5 @@
 			exec_unit_assign_error = 1;
 		}
-	}		
+	}
 
 	/* save the number of CPUs to a globally accessible variable */
Index: kernel/arch/sparc64/src/sun4u/start.S
===================================================================
--- kernel/arch/sparc64/src/sun4u/start.S	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/sparc64/src/sun4u/start.S	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -88,5 +88,5 @@
 	! l5 <= physmem_base[(PHYSMEM_ADDR_SIZE - 1):13]
 	sllx %l5, 13 + (63 - (PHYSMEM_ADDR_SIZE - 1)), %l5
-	srlx %l5, 63 - (PHYSMEM_ADDR_SIZE - 1), %l5	
+	srlx %l5, 63 - (PHYSMEM_ADDR_SIZE - 1), %l5
 
 	/*
@@ -118,5 +118,5 @@
 	wrpr %g1, %lo(trap_table), %tba
 
-	/* 
+	/*
 	 * Take over the DMMU by installing locked TTE entry identically
 	 * mapping the first 4M of memory.
@@ -135,5 +135,5 @@
 	! demap context 0
 	SET_TLB_DEMAP_CMD(g1, TLB_DEMAP_NUCLEUS)
-	stxa %g0, [%g1] ASI_DMMU_DEMAP			
+	stxa %g0, [%g1] ASI_DMMU_DEMAP
 	membar #Sync
 
@@ -143,5 +143,5 @@
 	! write DTLB tag
 	SET_TLB_TAG(g1, MEM_CONTEXT_KERNEL)
-	stxa %g1, [VA_DMMU_TAG_ACCESS] %asi			
+	stxa %g1, [VA_DMMU_TAG_ACCESS] %asi
 	membar #Sync
 
@@ -164,5 +164,5 @@
 	! write DTLB data and install the kernel mapping
 	SET_TLB_DATA(g1, g2, TTE_L | TTE_W)	! use non-global mapping
-	stxa %g1, [%g0] ASI_DTLB_DATA_IN_REG		
+	stxa %g1, [%g0] ASI_DTLB_DATA_IN_REG
 	membar #Sync
 
@@ -175,10 +175,10 @@
 	! write DTLB tag of context 1 (i.e. MEM_CONTEXT_TEMP)
 	SET_TLB_TAG(g1, MEM_CONTEXT_TEMP)
-	stxa %g1, [VA_DMMU_TAG_ACCESS] %asi			
+	stxa %g1, [VA_DMMU_TAG_ACCESS] %asi
 	membar #Sync
 
 	! write DTLB data and install the kernel mapping in context 1
 	SET_TLB_DATA(g1, g2, TTE_W)			! use non-global mapping
-	stxa %g1, [%g0] ASI_DTLB_DATA_IN_REG		
+	stxa %g1, [%g0] ASI_DTLB_DATA_IN_REG
 	membar #Sync
 	
@@ -213,5 +213,5 @@
 	! write ITLB data and install the temporary mapping in context 1
 	SET_TLB_DATA(g1, g2, 0)			! use non-global mapping
-	stxa %g1, [%g0] ASI_ITLB_DATA_IN_REG		
+	stxa %g1, [%g0] ASI_ITLB_DATA_IN_REG
 	flush %g5
 	
@@ -223,5 +223,5 @@
 	! demap context 0
 	SET_TLB_DEMAP_CMD(g1, TLB_DEMAP_NUCLEUS)
-	stxa %g0, [%g1] ASI_IMMU_DEMAP			
+	stxa %g0, [%g1] ASI_IMMU_DEMAP
 	flush %g5
 	
@@ -234,5 +234,5 @@
 	! write ITLB data and install the permanent kernel mapping in context 0
 	SET_TLB_DATA(g1, g2, TTE_L)		! use non-global mapping
-	stxa %g1, [%g0] ASI_ITLB_DATA_IN_REG		
+	stxa %g1, [%g0] ASI_ITLB_DATA_IN_REG
 	flush %g5
 
@@ -242,5 +242,5 @@
 	! demap context 1
 	SET_TLB_DEMAP_CMD(g1, TLB_DEMAP_PRIMARY)
-	stxa %g0, [%g1] ASI_IMMU_DEMAP			
+	stxa %g0, [%g1] ASI_IMMU_DEMAP
 	flush %g5
 	
@@ -406,5 +406,5 @@
  */
 
-.align 32 
+.align 32
 /*
  * This label is used by the fast_data_access_MMU_miss trap handler.
@@ -417,5 +417,5 @@
  */
 SYMBOL(end_of_identity)
-	.quad -1 
+	.quad -1
 /*
  * This variable is used by the fast_data_access_MMU_miss trap handler.
Index: kernel/arch/sparc64/src/sun4v/md.c
===================================================================
--- kernel/arch/sparc64/src/sun4v/md.c	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/sparc64/src/sun4v/md.c	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -126,10 +126,10 @@
  * Returns the value of the integer property of the given node.
  *
- * @param 
+ * @param
  */
 bool md_get_integer_property(md_node_t node, const char *key,
 	uint64_t *result)
 {
-	element_idx_t idx = node;	
+	element_idx_t idx = node;
 
 	while (get_element(idx)->tag != NODE_END) {
@@ -149,5 +149,5 @@
  * Returns the value of the string property of the given node.
  *
- * @param 
+ * @param
  */
 bool md_get_string_property(md_node_t node, const char *key,
@@ -278,5 +278,5 @@
 /**
  * Moves "node" to the node following "node" in the list of all the existing
- * nodes of the MD whose name is "name". 
+ * nodes of the MD whose name is "name".
  */
 bool md_next_node(md_node_t *node, const char *name)
Index: kernel/arch/sparc64/src/sun4v/start.S
===================================================================
--- kernel/arch/sparc64/src/sun4v/start.S	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/sparc64/src/sun4v/start.S	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -118,5 +118,5 @@
 	! l5 <= physmem_base[(PHYSMEM_ADDR_SIZE - 1):13]
 	sllx %l5, 13 + (63 - (PHYSMEM_ADDR_SIZE - 1)), %l5
-	srlx %l5, 63 - (PHYSMEM_ADDR_SIZE - 1), %l5	
+	srlx %l5, 63 - (PHYSMEM_ADDR_SIZE - 1), %l5
 
 	/*
@@ -225,5 +225,5 @@
 	 * Save physmem_base for use by the mm subsystem.
 	 * %l6 contains starting physical address
-	 */	
+	 */
 	sethi %hi(physmem_base), %l4
 	stx %l6, [%l4 + %lo(physmem_base)]
Index: kernel/arch/sparc64/src/trap/interrupt.c
===================================================================
--- kernel/arch/sparc64/src/trap/interrupt.c	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/sparc64/src/trap/interrupt.c	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -112,5 +112,5 @@
 	exc_register(TT_TAG_OVERFLOW,
 	    "tag_overflow", false,
-	    tag_overflow);	
+	    tag_overflow);
 	exc_register(TT_DIVISION_BY_ZERO,
 	    "division_by_zero", false,
@@ -145,5 +145,5 @@
 	    tick_interrupt);
 
-#ifdef SUN4U 
+#ifdef SUN4U
 	exc_register(TT_INTERRUPT_VECTOR_TRAP,
 	    "interrupt_vector_trap", true,
@@ -159,5 +159,5 @@
 	exc_register(TT_FAST_DATA_ACCESS_PROTECTION,
 	    "fast_data_access_protection", true,
-	    fast_data_access_protection);	
+	    fast_data_access_protection);
 
 #ifdef SUN4V
Index: kernel/arch/sparc64/src/trap/sun4u/trap_table.S
===================================================================
--- kernel/arch/sparc64/src/trap/sun4u/trap_table.S	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/sparc64/src/trap/sun4u/trap_table.S	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -64,5 +64,5 @@
 	mov TT_INSTRUCTION_ACCESS_EXCEPTION, %g2
 	clr %g5
-	PREEMPTIBLE_HANDLER exc_dispatch 
+	PREEMPTIBLE_HANDLER exc_dispatch
 
 /* TT = 0x0a, TL = 0, instruction_access_error */
@@ -71,5 +71,5 @@
 	mov TT_INSTRUCTION_ACCESS_ERROR, %g2
 	clr %g5
-	PREEMPTIBLE_HANDLER exc_dispatch 
+	PREEMPTIBLE_HANDLER exc_dispatch
 
 /* TT = 0x10, TL = 0, illegal_instruction */
@@ -78,5 +78,5 @@
 	mov TT_ILLEGAL_INSTRUCTION, %g2
 	clr %g5
-	PREEMPTIBLE_HANDLER exc_dispatch 
+	PREEMPTIBLE_HANDLER exc_dispatch
 
 /* TT = 0x11, TL = 0, privileged_opcode */
@@ -85,5 +85,5 @@
 	mov TT_PRIVILEGED_OPCODE, %g2
 	clr %g5
-	PREEMPTIBLE_HANDLER exc_dispatch 
+	PREEMPTIBLE_HANDLER exc_dispatch
 
 /* TT = 0x12, TL = 0, unimplemented_LDD */
@@ -92,5 +92,5 @@
 	mov TT_UNIMPLEMENTED_LDD, %g2
 	clr %g5
-	PREEMPTIBLE_HANDLER exc_dispatch 
+	PREEMPTIBLE_HANDLER exc_dispatch
 
 /* TT = 0x13, TL = 0, unimplemented_STD */
@@ -106,5 +106,5 @@
 	mov TT_FP_DISABLED, %g2
 	clr %g5
-	PREEMPTIBLE_HANDLER exc_dispatch 
+	PREEMPTIBLE_HANDLER exc_dispatch
 
 /* TT = 0x21, TL = 0, fb_exception_ieee_754 handler */
@@ -168,5 +168,5 @@
 	mov TT_LDDF_MEM_ADDRESS_NOT_ALIGNED, %g2
 	clr %g5
-	PREEMPTIBLE_HANDLER exc_dispatch 
+	PREEMPTIBLE_HANDLER exc_dispatch
 
 /* TT = 0x36, TL = 0, STDF_mem_address_not_aligned */
@@ -382,5 +382,5 @@
 	mov TT_INSTRUCTION_ACCESS_EXCEPTION, %g2
 	clr %g5
-	PREEMPTIBLE_HANDLER exc_dispatch 
+	PREEMPTIBLE_HANDLER exc_dispatch
 
 /* TT = 0x0a, TL > 0, instruction_access_error */
@@ -489,5 +489,5 @@
  * TL1: preemptible trap handler started after a tick interrupt
  * TL2: preemptible trap handler did SAVE
- * TL3: spill handler touched the kernel stack  
+ * TL3: spill handler touched the kernel stack
  * TL4: hardware or software failure
  *
@@ -510,5 +510,5 @@
 	 * trap is resolved. However, because we are in the wrong window from the
 	 * perspective of the MMU trap, we need to synchronize CWP with CWP from TL=0.
-	 */ 
+	 */
 	and %g3, TSTATE_CWP_MASK, %g4
 	wrpr %g4, 0, %cwp			! resynchronize CWP
@@ -566,5 +566,5 @@
 
 	/*
-	 * At this moment, we are using the kernel stack 
+	 * At this moment, we are using the kernel stack
 	 * and have successfully allocated a register window.
 	 */
@@ -585,5 +585,5 @@
 .else
 	! store the syscall number on the stack as 7th argument
-	stx %g2, [%sp + STACK_BIAS + ISTATE_OFFSET_ARG6] 
+	stx %g2, [%sp + STACK_BIAS + ISTATE_OFFSET_ARG6]
 .endif
 
Index: kernel/arch/sparc64/src/trap/sun4v/trap_table.S
===================================================================
--- kernel/arch/sparc64/src/trap/sun4v/trap_table.S	(revision fec0240ef06fc1a62210bc1e0e106291c3ed64fb)
+++ kernel/arch/sparc64/src/trap/sun4v/trap_table.S	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -67,5 +67,5 @@
 	mov TT_INSTRUCTION_ACCESS_EXCEPTION, %g2
 	clr %g5
-	PREEMPTIBLE_HANDLER exc_dispatch 
+	PREEMPTIBLE_HANDLER exc_dispatch
 
 /* TT = 0x09, TL = 0, instruction_access_mmu_miss */
@@ -86,5 +86,5 @@
 	mov TT_IAE_UNAUTH_ACCESS, %g2
 	clr %g5
-	PREEMPTIBLE_HANDLER exc_dispatch 
+	PREEMPTIBLE_HANDLER exc_dispatch
 
 /* TT = 0x0c, TL = 0, IAE_nfo_page */
@@ -93,5 +93,5 @@
 	mov TT_IAE_NFO_PAGE, %g2
 	clr %g5
-	PREEMPTIBLE_HANDLER exc_dispatch 
+	PREEMPTIBLE_HANDLER exc_dispatch
 
 /* TT = 0x10, TL = 0, illegal_instruction */
@@ -100,5 +100,5 @@
 	mov TT_ILLEGAL_INSTRUCTION, %g2
 	clr %g5
-	PREEMPTIBLE_HANDLER exc_dispatch 
+	PREEMPTIBLE_HANDLER exc_dispatch
 
 /* TT = 0x11, TL = 0, privileged_opcode */
@@ -107,5 +107,5 @@
 	mov TT_PRIVILEGED_OPCODE, %g2
 	clr %g5
-	PREEMPTIBLE_HANDLER exc_dispatch 
+	PREEMPTIBLE_HANDLER exc_dispatch
 
 /* TT = 0x12, TL = 0, unimplemented_LDD */
@@ -114,5 +114,5 @@
 	mov TT_UNIMPLEMENTED_LDD, %g2
 	clr %g5
-	PREEMPTIBLE_HANDLER exc_dispatch 
+	PREEMPTIBLE_HANDLER exc_dispatch
 
 /* TT = 0x13, TL = 0, unimplemented_STD */
@@ -121,5 +121,5 @@
 	mov TT_UNIMPLEMENTED_STD, %g2
 	clr %g5
-	PREEMPTIBLE_HANDLER exc_dispatch 
+	PREEMPTIBLE_HANDLER exc_dispatch
 
 /* TT = 0x14, TL = 0, DAE_invalid_asi */
@@ -128,5 +128,5 @@
 	mov TT_DAE_INVALID_ASI, %g2
 	clr %g5
-	PREEMPTIBLE_HANDLER exc_dispatch 
+	PREEMPTIBLE_HANDLER exc_dispatch
 
 /* TT = 0x15, TL = 0, DAE_privilege_violation */
@@ -135,5 +135,5 @@
 	mov TT_DAE_PRIVILEGE_VIOLATION, %g2
 	clr %g5
-	PREEMPTIBLE_HANDLER exc_dispatch 
+	PREEMPTIBLE_HANDLER exc_dispatch
 
 /* TT = 0x16, TL = 0, DAE_nc_page */
@@ -142,5 +142,5 @@
 	mov TT_DAE_NC_PAGE, %g2
 	clr %g5
-	PREEMPTIBLE_HANDLER exc_dispatch 
+	PREEMPTIBLE_HANDLER exc_dispatch
 
 /* TT = 0x17, TL = 0, DAE_nfo_page */
@@ -149,5 +149,5 @@
 	mov TT_DAE_NFO_PAGE, %g2
 	clr %g5
-	PREEMPTIBLE_HANDLER exc_dispatch 
+	PREEMPTIBLE_HANDLER exc_dispatch
 
 /* TT = 0x20, TL = 0, fb_disabled handler */
@@ -156,5 +156,5 @@
 	mov TT_FP_DISABLED, %g2
 	clr %g5
-	PREEMPTIBLE_HANDLER exc_dispatch 
+	PREEMPTIBLE_HANDLER exc_dispatch
 
 /* TT = 0x21, TL = 0, fb_exception_ieee_754 handler */
@@ -163,5 +163,5 @@
 	mov TT_FP_EXCEPTION_IEEE_754, %g2
 	clr %g5
-	PREEMPTIBLE_HANDLER exc_dispatch 
+	PREEMPTIBLE_HANDLER exc_dispatch
 
 /* TT = 0x22, TL = 0, fb_exception_other handler */
@@ -170,5 +170,5 @@
 	mov TT_FP_EXCEPTION_OTHER, %g2
 	clr %g5
-	PREEMPTIBLE_HANDLER exc_dispatch 
+	PREEMPTIBLE_HANDLER exc_dispatch
 
 /* TT = 0x23, TL = 0, tag_overflow */
@@ -177,5 +177,5 @@
 	mov TT_TAG_OVERFLOW, %g2
 	clr %g5
-	PREEMPTIBLE_HANDLER exc_dispatch 
+	PREEMPTIBLE_HANDLER exc_dispatch
 
 /* TT = 0x24, TL = 0, clean_window handler */
@@ -189,5 +189,5 @@
 	mov TT_DIVISION_BY_ZERO, %g2
 	clr %g5
-	PREEMPTIBLE_HANDLER exc_dispatch 
+	PREEMPTIBLE_HANDLER exc_dispatch
 
 /* TT = 0x30, TL = 0, data_access_exception */
@@ -197,5 +197,5 @@
 	mov TT_DATA_ACCESS_EXCEPTION, %g2
 	clr %g5
-	PREEMPTIBLE_HANDLER exc_dispatch 
+	PREEMPTIBLE_HANDLER exc_dispatch
 
 /* TT = 0x31, TL = 0, data_access_mmu_miss */
@@ -209,5 +209,5 @@
 	mov TT_DATA_ACCESS_ERROR, %g2
 	clr %g5
-	PREEMPTIBLE_HANDLER exc_dispatch 
+	PREEMPTIBLE_HANDLER exc_dispatch
 
 /* TT = 0x34, TL = 0, mem_address_not_aligned */
@@ -216,5 +216,5 @@
 	mov TT_MEM_ADDRESS_NOT_ALIGNED, %g2
 	clr %g5
-	PREEMPTIBLE_HANDLER exc_dispatch 
+	PREEMPTIBLE_HANDLER exc_dispatch
 
 /* TT = 0x35, TL = 0, LDDF_mem_address_not_aligned */
@@ -223,5 +223,5 @@
 	mov TT_LDDF_MEM_ADDRESS_NOT_ALIGNED, %g2
 	clr %g5
-	PREEMPTIBLE_HANDLER exc_dispatch 
+	PREEMPTIBLE_HANDLER exc_dispatch
 
 /* TT = 0x36, TL = 0, STDF_mem_address_not_aligned */
@@ -230,5 +230,5 @@
 	mov TT_STDF_MEM_ADDRESS_NOT_ALIGNED, %g2
 	clr %g5
-	PREEMPTIBLE_HANDLER exc_dispatch 
+	PREEMPTIBLE_HANDLER exc_dispatch
 
 /* TT = 0x37, TL = 0, privileged_action */
@@ -237,5 +237,5 @@
 	mov TT_PRIVILEGED_ACTION, %g2
 	clr %g5
-	PREEMPTIBLE_HANDLER exc_dispatch 
+	PREEMPTIBLE_HANDLER exc_dispatch
 
 /* TT = 0x38, TL = 0, LDQF_mem_address_not_aligned */
@@ -244,5 +244,5 @@
 	mov TT_LDQF_MEM_ADDRESS_NOT_ALIGNED, %g2
 	clr %g5
-	PREEMPTIBLE_HANDLER exc_dispatch 
+	PREEMPTIBLE_HANDLER exc_dispatch
 
 /* TT = 0x39, TL = 0, STQF_mem_address_not_aligned */
@@ -251,5 +251,5 @@
 	mov TT_STQF_MEM_ADDRESS_NOT_ALIGNED, %g2
 	clr %g5
-	PREEMPTIBLE_HANDLER exc_dispatch 
+	PREEMPTIBLE_HANDLER exc_dispatch
 
 /* TT = 0x41, TL = 0, interrupt_level_1 handler */
@@ -378,5 +378,5 @@
 	mov TT_CPU_MONDO, %g2
 	clr %g5
-	PREEMPTIBLE_HANDLER exc_dispatch 
+	PREEMPTIBLE_HANDLER exc_dispatch
 
 /* TT = 0x80, TL = 0, spill_0_normal handler */
@@ -437,5 +437,5 @@
 	mov TT_INSTRUCTION_ACCESS_EXCEPTION, %g2
 	clr %g5
-	PREEMPTIBLE_HANDLER exc_dispatch 
+	PREEMPTIBLE_HANDLER exc_dispatch
 
 /* TT = 0x09, TL > 0, instruction_access_mmu_miss */
@@ -451,5 +451,5 @@
 	mov TT_INSTRUCTION_ACCESS_ERROR, %g2
 	clr %g5
-	PREEMPTIBLE_HANDLER exc_dispatch 
+	PREEMPTIBLE_HANDLER exc_dispatch
 
 /* TT = 0x0b, TL > 0, IAE_unauth_access */
@@ -459,5 +459,5 @@
 	mov TT_IAE_UNAUTH_ACCESS, %g2
 	clr %g5
-	PREEMPTIBLE_HANDLER exc_dispatch 
+	PREEMPTIBLE_HANDLER exc_dispatch
 
 /* TT = 0x0c, TL > 0, IAE_nfo_page */
@@ -467,5 +467,5 @@
 	mov TT_IAE_NFO_PAGE, %g2
 	clr %g5
-	PREEMPTIBLE_HANDLER exc_dispatch 
+	PREEMPTIBLE_HANDLER exc_dispatch
 
 /* TT = 0x10, TL > 0, illegal_instruction */
@@ -475,5 +475,5 @@
 	mov TT_ILLEGAL_INSTRUCTION, %g2
 	clr %g5
-	PREEMPTIBLE_HANDLER exc_dispatch 
+	PREEMPTIBLE_HANDLER exc_dispatch
 
 /* TT = 0x14, TL > 0, DAE_invalid_asi */
@@ -483,5 +483,5 @@
 	mov TT_DAE_INVALID_ASI, %g2
 	clr %g5
-	PREEMPTIBLE_HANDLER exc_dispatch 
+	PREEMPTIBLE_HANDLER exc_dispatch
 
 /* TT = 0x15, TL > 0, DAE_privilege_violation */
@@ -491,5 +491,5 @@
 	mov TT_DAE_PRIVILEGE_VIOLATION, %g2
 	clr %g5
-	PREEMPTIBLE_HANDLER exc_dispatch 
+	PREEMPTIBLE_HANDLER exc_dispatch
 
 /* TT = 0x16, TL > 0, DAE_nc_page */
@@ -499,5 +499,5 @@
 	mov TT_DAE_NC_PAGE, %g2
 	clr %g5
-	PREEMPTIBLE_HANDLER exc_dispatch 
+	PREEMPTIBLE_HANDLER exc_dispatch
 
 /* TT = 0x17, TL > 0, DAE_nfo_page */
@@ -507,5 +507,5 @@
 	mov TT_DAE_NFO_PAGE, %g2
 	clr %g5
-	PREEMPTIBLE_HANDLER exc_dispatch 
+	PREEMPTIBLE_HANDLER exc_dispatch
 
 /* TT = 0x24, TL > 0, clean_window handler */
@@ -520,5 +520,5 @@
 	mov TT_DIVISION_BY_ZERO, %g2
 	clr %g5
-	PREEMPTIBLE_HANDLER exc_dispatch 
+	PREEMPTIBLE_HANDLER exc_dispatch
 
 /* TT = 0x30, TL > 0, data_access_exception */
@@ -528,5 +528,5 @@
 	mov TT_DATA_ACCESS_EXCEPTION, %g2
 	clr %g5
-	PREEMPTIBLE_HANDLER exc_dispatch 
+	PREEMPTIBLE_HANDLER exc_dispatch
 
 /* TT = 0x31, TL > 0, data_access_mmu_miss */
@@ -541,5 +541,5 @@
 	mov TT_DATA_ACCESS_ERROR, %g2
 	clr %g5
-	PREEMPTIBLE_HANDLER exc_dispatch 
+	PREEMPTIBLE_HANDLER exc_dispatch
 
 /* TT = 0x34, TL > 0, mem_address_not_aligned */
@@ -549,5 +549,5 @@
 	mov TT_MEM_ADDRESS_NOT_ALIGNED, %g2
 	clr %g5
-	PREEMPTIBLE_HANDLER exc_dispatch 
+	PREEMPTIBLE_HANDLER exc_dispatch
 
 /* TT = 0x68, TL > 0, fast_data_access_MMU_miss */
@@ -567,5 +567,5 @@
 	mov TT_CPU_MONDO, %g2
 	clr %g5
-	PREEMPTIBLE_HANDLER exc_dispatch 
+	PREEMPTIBLE_HANDLER exc_dispatch
 
 /* TT = 0x80, TL > 0, spill_0_normal handler */
@@ -595,5 +595,5 @@
  * Spills the window at CWP + 2 to the kernel stack. This macro is to be
  * used before doing SAVE when the spill trap is undesirable.
- * 
+ *
  * Parameters:
  * 	tmpreg1		global register to be used for scratching purposes
@@ -608,5 +608,5 @@
 	
 	! spill to kernel stack
-	stx %l0, [%sp + STACK_BIAS + L0_OFFSET]	
+	stx %l0, [%sp + STACK_BIAS + L0_OFFSET]
 	stx %l1, [%sp + STACK_BIAS + L1_OFFSET]
 	stx %l2, [%sp + STACK_BIAS + L2_OFFSET]
@@ -634,5 +634,5 @@
  * Fill the window at CWP - 1 from the kernel stack. This macro is to be
  * used before doing RESTORE when the fill trap is undesirable.
- * 
+ *
  * Parameters:
  * 	tmpreg1		global register to be used for scratching purposes
@@ -689,5 +689,5 @@
 .else
 	! store the syscall number on the stack as 7th argument
-	stx %g2, [%sp + STACK_BIAS + ISTATE_OFFSET_ARG6] 
+	stx %g2, [%sp + STACK_BIAS + ISTATE_OFFSET_ARG6]
 .endif
 
@@ -859,5 +859,5 @@
  * Spills the window at CWP + 2 to the userspace window buffer. This macro
  * is to be used before doing SAVE when the spill trap is undesirable.
- * 
+ *
  * Parameters:
  * 	tmpreg1		global register to be used for scratching purposes
@@ -892,5 +892,5 @@
 	 * trap is resolved. However, because we are in the wrong window from the
 	 * perspective of the MMU trap, we need to synchronize CWP with CWP from TL=0.
-	 */ 
+	 */
 .if NOT(\is_syscall)
 	rdpr %tstate, %g3
@@ -927,5 +927,5 @@
 .endif
 
-	mov VA_PRIMARY_CONTEXT_REG, %l0 
+	mov VA_PRIMARY_CONTEXT_REG, %l0
 	stxa %g0, [%l0] ASI_PRIMARY_CONTEXT_REG
 	rd %pc, %l0