Index: kernel/arch/mips32/include/arch/cache.h
===================================================================
--- kernel/arch/mips32/include/arch/cache.h	(revision 5b0cf635022b821f28f7a014ad5b39d005cd7666)
+++ kernel/arch/mips32/include/arch/cache.h	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -27,5 +27,5 @@
  */
 
-/** @addtogroup mips32	
+/** @addtogroup mips32
  * @{
  */
Index: kernel/arch/mips32/include/arch/context_struct.ag
===================================================================
--- kernel/arch/mips32/include/arch/context_struct.ag	(revision 5b0cf635022b821f28f7a014ad5b39d005cd7666)
+++ kernel/arch/mips32/include/arch/context_struct.ag	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -1,3 +1,3 @@
-# Copyright (c) 2014 Jakub Jermar 
+# Copyright (c) 2014 Jakub Jermar
 # All rights reserved.
 #
Index: kernel/arch/mips32/include/arch/fpu_context.h
===================================================================
--- kernel/arch/mips32/include/arch/fpu_context.h	(revision 5b0cf635022b821f28f7a014ad5b39d005cd7666)
+++ kernel/arch/mips32/include/arch/fpu_context.h	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -27,5 +27,5 @@
  */
 
-/** @addtogroup mips32	
+/** @addtogroup mips32
  * @{
  */
Index: kernel/arch/mips32/include/arch/fpu_context_struct.ag
===================================================================
--- kernel/arch/mips32/include/arch/fpu_context_struct.ag	(revision 5b0cf635022b821f28f7a014ad5b39d005cd7666)
+++ kernel/arch/mips32/include/arch/fpu_context_struct.ag	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -1,3 +1,3 @@
-# Copyright (c) 2014 Jakub Jermar 
+# Copyright (c) 2014 Jakub Jermar
 # All rights reserved.
 #
Index: kernel/arch/mips32/include/arch/istate_struct.ag
===================================================================
--- kernel/arch/mips32/include/arch/istate_struct.ag	(revision 5b0cf635022b821f28f7a014ad5b39d005cd7666)
+++ kernel/arch/mips32/include/arch/istate_struct.ag	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -1,3 +1,3 @@
-# Copyright (c) 2014 Jakub Jermar 
+# Copyright (c) 2014 Jakub Jermar
 # All rights reserved.
 #
Index: kernel/arch/mips32/include/arch/mach/malta/malta.h
===================================================================
--- kernel/arch/mips32/include/arch/mach/malta/malta.h	(revision 5b0cf635022b821f28f7a014ad5b39d005cd7666)
+++ kernel/arch/mips32/include/arch/mach/malta/malta.h	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -1,4 +1,4 @@
 /*
- * Copyright (c) 2013 Jakub Jermar 
+ * Copyright (c) 2013 Jakub Jermar
  * All rights reserved.
  *
@@ -27,5 +27,5 @@
  */
 
-/** @addtogroup mips32 
+/** @addtogroup mips32
  * @{
  */
Index: kernel/arch/mips32/include/arch/mach/msim/msim.h
===================================================================
--- kernel/arch/mips32/include/arch/mach/msim/msim.h	(revision 5b0cf635022b821f28f7a014ad5b39d005cd7666)
+++ kernel/arch/mips32/include/arch/mach/msim/msim.h	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -1,4 +1,4 @@
 /*
- * Copyright (c) 2013 Jakub Jermar 
+ * Copyright (c) 2013 Jakub Jermar
  * All rights reserved.
  *
@@ -27,5 +27,5 @@
  */
 
-/** @addtogroup mips32 
+/** @addtogroup mips32
  * @{
  */
Index: kernel/arch/mips32/include/arch/mm/asid.h
===================================================================
--- kernel/arch/mips32/include/arch/mm/asid.h	(revision 5b0cf635022b821f28f7a014ad5b39d005cd7666)
+++ kernel/arch/mips32/include/arch/mm/asid.h	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -27,5 +27,5 @@
  */
 
-/** @addtogroup mips32mm	
+/** @addtogroup mips32mm
  * @{
  */
Index: kernel/arch/mips32/include/arch/mm/page.h
===================================================================
--- kernel/arch/mips32/include/arch/mm/page.h	(revision 5b0cf635022b821f28f7a014ad5b39d005cd7666)
+++ kernel/arch/mips32/include/arch/mm/page.h	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -52,5 +52,5 @@
 /*
  * Implementation of generic 4-level page table interface.
- * 
+ *
  * Page table layout:
  * - 32-bit virtual addresses
Index: kernel/arch/mips32/include/arch/mm/tlb.h
===================================================================
--- kernel/arch/mips32/include/arch/mm/tlb.h	(revision 5b0cf635022b821f28f7a014ad5b39d005cd7666)
+++ kernel/arch/mips32/include/arch/mm/tlb.h	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -52,5 +52,5 @@
 #endif
 
-#define TLB_WIRED              	0 
+#define TLB_WIRED              	0
 
 #define TLB_PAGE_MASK_4K    (0x000 << 13)
Index: kernel/arch/mips32/src/cpu/cpu.c
===================================================================
--- kernel/arch/mips32/src/cpu/cpu.c	(revision 5b0cf635022b821f28f7a014ad5b39d005cd7666)
+++ kernel/arch/mips32/src/cpu/cpu.c	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -125,5 +125,5 @@
 
 	printf("cpu%u: %s %s (rev=%d.%d, imp=%d)\n",
-		m->id, data->vendor, data->model, m->arch.rev_num >> 4, 
+		m->id, data->vendor, data->model, m->arch.rev_num >> 4,
 		m->arch.rev_num & 0x0f, m->arch.imp_num);
 }
Index: kernel/arch/mips32/src/debug/stacktrace.c
===================================================================
--- kernel/arch/mips32/src/debug/stacktrace.c	(revision 5b0cf635022b821f28f7a014ad5b39d005cd7666)
+++ kernel/arch/mips32/src/debug/stacktrace.c	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -36,5 +36,5 @@
  * This stack tracing code is based on the suggested algorithm described on page
  * 3-27 and 3-28 of:
- * 
+ *
  * SYSTEM V
  * APPLICATION BINARY INTERFACE
@@ -88,5 +88,5 @@
 #define BASE_MASK	RS_MASK
 #define IMM_MASK	(0xffff << IMM_SHIFT)
-#define OFFSET_MASK	IMM_MASK	
+#define OFFSET_MASK	IMM_MASK
 
 #define RS_GET(inst)		(((inst) & RS_MASK) >> RS_SHIFT)
@@ -94,5 +94,5 @@
 #define IMM_GET(inst)		(int16_t)(((inst) & IMM_MASK) >> IMM_SHIFT)
 #define BASE_GET(inst)		RS_GET(inst)
-#define OFFSET_GET(inst)	IMM_GET(inst)	
+#define OFFSET_GET(inst)	IMM_GET(inst)
 
 #define ADDU_R_SP_R0_TEMPL \
Index: kernel/arch/mips32/src/debugger.c
===================================================================
--- kernel/arch/mips32/src/debugger.c	(revision 5b0cf635022b821f28f7a014ad5b39d005cd7666)
+++ kernel/arch/mips32/src/debugger.c	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -386,5 +386,5 @@
 			((uint32_t *)cur->address)[1] = 0x0d;
 			cur->flags |= BKPOINT_REINST;
-		} 
+		}
 		cur->flags |= BKPOINT_INPROG;
 	} else {
Index: kernel/arch/mips32/src/exception.c
===================================================================
--- kernel/arch/mips32/src/exception.c	(revision 5b0cf635022b821f28f7a014ad5b39d005cd7666)
+++ kernel/arch/mips32/src/exception.c	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -132,5 +132,5 @@
 	debugger_bpoint(istate);
 #else
-	/* it is necessary to not re-execute BREAK instruction after 
+	/* it is necessary to not re-execute BREAK instruction after
 	   returning from Exception handler
 	   (see page 138 in R4000 Manual for more information) */
Index: kernel/arch/mips32/src/mach/malta/malta.c
===================================================================
--- kernel/arch/mips32/src/mach/malta/malta.c	(revision 5b0cf635022b821f28f7a014ad5b39d005cd7666)
+++ kernel/arch/mips32/src/mach/malta/malta.c	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -27,5 +27,5 @@
  */
 
-/** @addtogroup mips32 
+/** @addtogroup mips32
  * @{
  */
@@ -54,5 +54,5 @@
 	.machine_output_init = malta_output_init,
 	.machine_input_init = malta_input_init,
-	.machine_get_platform_name = malta_get_platform_name	
+	.machine_get_platform_name = malta_get_platform_name
 };
 
Index: kernel/arch/mips32/src/mach/msim/msim.c
===================================================================
--- kernel/arch/mips32/src/mach/msim/msim.c	(revision 5b0cf635022b821f28f7a014ad5b39d005cd7666)
+++ kernel/arch/mips32/src/mach/msim/msim.c	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -27,5 +27,5 @@
  */
 
-/** @addtogroup mips32 
+/** @addtogroup mips32
  * @{
  */
@@ -57,5 +57,5 @@
 	.machine_output_init = msim_output_init,
 	.machine_input_init = msim_input_init,
-	.machine_get_platform_name = msim_get_platform_name	
+	.machine_get_platform_name = msim_get_platform_name
 };
 
Index: kernel/arch/mips32/src/mm/frame.c
===================================================================
--- kernel/arch/mips32/src/mm/frame.c	(revision 5b0cf635022b821f28f7a014ad5b39d005cd7666)
+++ kernel/arch/mips32/src/mm/frame.c	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -141,5 +141,5 @@
 
 	if (!frame_adjust_zone_bounds(low, &base, &size))
-		return; 
+		return;
 
 	pfn_t first = ADDR2PFN(base);
@@ -291,5 +291,5 @@
 		printf("%#010x %10u\n",
 			PFN2ADDR(phys_regions[i].start), PFN2ADDR(phys_regions[i].count));
-	}	
+	}
 }
 
Index: kernel/arch/mips32/src/mm/tlb.c
===================================================================
--- kernel/arch/mips32/src/mm/tlb.c	(revision 5b0cf635022b821f28f7a014ad5b39d005cd7666)
+++ kernel/arch/mips32/src/mm/tlb.c	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
@@ -219,5 +219,5 @@
 	 * We do not assert on this because this could be a manifestation of
 	 * an emulator bug, such as QEMU Bug #1128935:
-	 * https://bugs.launchpad.net/qemu/+bug/1128935  
+	 * https://bugs.launchpad.net/qemu/+bug/1128935
 	 */
 	if (index.p) {